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source: trunk/src/gcc/gcc/config/mn10300/mn10300.md@ 2

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Last change on this file since 2 was 2, checked in by bird, 22 years ago
Initial revision
Property cvs2svn:cvs-rev set to `1.1` Property svn:eol-style set to `native` Property svn:executable set to ``*
File size: 59.2 KB

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1	;; GCC machine description for Matsushita MN10300
2	;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001
3	;; Free Software Foundation, Inc.
4	;; Contributed by Jeff Law (law@cygnus.com).
5
6	;; This file is part of GNU CC.
7
8	;; GNU CC is free software; you can redistribute it and/or modify
9	;; it under the terms of the GNU General Public License as published by
10	;; the Free Software Foundation; either version 2, or (at your option)
11	;; any later version.
12
13	;; GNU CC is distributed in the hope that it will be useful,
14	;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15	;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	;; GNU General Public License for more details.
17
18	;; You should have received a copy of the GNU General Public License
19	;; along with GNU CC; see the file COPYING. If not, write to
20	;; the Free Software Foundation, 59 Temple Place - Suite 330,
21	;; Boston, MA 02111-1307, USA.
22
23	;; The original PO technology requires these to be ordered by speed,
24	;; so that assigner will pick the fastest.
25
26	;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
27
28	;; Condition code settings.
29	;; none - insn does not affect cc
30	;; none_0hit - insn does not affect cc but it does modify operand 0
31	;; This attribute is used to keep track of when operand 0 changes.
32	;; See the description of NOTICE_UPDATE_CC for more info.
33	;; set_znv - insn sets z,n,v to usable values; c is unusable.
34	;; set_zn - insn sets z,n to usable values; v,c are unusable.
35	;; compare - compare instruction
36	;; invert -- like compare, but flags are inverted.
37	;; clobber - value of cc is unknown
38	(define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber,invert"
39	(const_string "clobber"))
40
41
42	;; ----------------------------------------------------------------------
43	;; MOVE INSTRUCTIONS
44	;; ----------------------------------------------------------------------
45
46	;; movqi
47
48	(define_expand "movqi"
49	[(set (match_operand:QI 0 "general_operand" "")
50	(match_operand:QI 1 "general_operand" ""))]
51	""
52	"
53	{
54	/* One of the ops has to be in a register */
55	if (!register_operand (operand0, QImode)
56	&& !register_operand (operand1, QImode))
57	operands[1] = copy_to_mode_reg (QImode, operand1);
58	}")
59
60	(define_insn ""
61	[(set (match_operand:QI 0 "nonimmediate_operand" "=dxa,dx,dxa,dx*a,m")
62	(match_operand:QI 1 "general_operand" "0,I,dxai,m,dxa"))]
63	"TARGET_AM33
64	&& (register_operand (operands[0], QImode)
65	\|\| register_operand (operands[1], QImode))"
66	"*
67	{
68	switch (which_alternative)
69	{
70	case 0:
71	return \"nop\";
72	case 1:
73	return \"clr %0\";
74	case 2:
75	if (GET_CODE (operands[1]) == CONST_DOUBLE)
76	{
77	rtx xoperands[2];
78	xoperands[0] = operands[0];
79	xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
80	output_asm_insn (\"mov %1,%0\", xoperands);
81	return \"\";
82	}
83
84	if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
85	&& GET_CODE (operands[1]) == CONST_INT)
86	{
87	HOST_WIDE_INT val = INTVAL (operands[1]);
88
89	if (((val & 0x80) && ! (val & 0xffffff00))
90	\|\| ((val & 0x800000) && ! (val & 0xff000000)))
91	return \"movu %1,%0\";
92	}
93	return \"mov %1,%0\";
94	case 3:
95	case 4:
96	return \"movbu %1,%0\";
97	default:
98	abort ();
99	}
100	}"
101	[(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
102
103	(define_insn ""
104	[(set (match_operand:QI 0 "nonimmediate_operand" "=da,d,da,d,m")
105	(match_operand:QI 1 "general_operand" "0,I,dai,m,d"))]
106	"register_operand (operands[0], QImode)
107	\|\| register_operand (operands[1], QImode)"
108	"*
109	{
110	switch (which_alternative)
111	{
112	case 0:
113	return \"nop\";
114	case 1:
115	return \"clr %0\";
116	case 2:
117	if (GET_CODE (operands[1]) == CONST_DOUBLE)
118	{
119	rtx xoperands[2];
120	xoperands[0] = operands[0];
121	xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
122	output_asm_insn (\"mov %1,%0\", xoperands);
123	return \"\";
124	}
125
126	return \"mov %1,%0\";
127	case 3:
128	case 4:
129	return \"movbu %1,%0\";
130	default:
131	abort ();
132	}
133	}"
134	[(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
135
136	;; movhi
137
138	(define_expand "movhi"
139	[(set (match_operand:HI 0 "general_operand" "")
140	(match_operand:HI 1 "general_operand" ""))]
141	""
142	"
143	{
144	/* One of the ops has to be in a register */
145	if (!register_operand (operand1, HImode)
146	&& !register_operand (operand0, HImode))
147	operands[1] = copy_to_mode_reg (HImode, operand1);
148	}")
149
150	(define_insn ""
151	[(set (match_operand:HI 0 "nonimmediate_operand" "=dxa,dx,dxa,dx*a,m")
152	(match_operand:HI 1 "general_operand" "0,I,dxai,m,dxa"))]
153	"TARGET_AM33
154	&& (register_operand (operands[0], HImode)
155	\|\| register_operand (operands[1], HImode))"
156	"*
157	{
158	switch (which_alternative)
159	{
160	case 0:
161	return \"nop\";
162	case 1:
163	return \"clr %0\";
164	case 2:
165	if (GET_CODE (operands[1]) == CONST_DOUBLE)
166	{
167	rtx xoperands[2];
168	xoperands[0] = operands[0];
169	xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
170	output_asm_insn (\"mov %1,%0\", xoperands);
171	return \"\";
172	}
173
174	if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
175	&& GET_CODE (operands[1]) == CONST_INT)
176	{
177	HOST_WIDE_INT val = INTVAL (operands[1]);
178
179	if (((val & 0x80) && ! (val & 0xffffff00))
180	\|\| ((val & 0x800000) && ! (val & 0xff000000)))
181	return \"movu %1,%0\";
182	}
183	return \"mov %1,%0\";
184	case 3:
185	case 4:
186	return \"movhu %1,%0\";
187	default:
188	abort ();
189	}
190	}"
191	[(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
192
193	(define_insn ""
194	[(set (match_operand:HI 0 "nonimmediate_operand" "=da,d,da,d,m")
195	(match_operand:HI 1 "general_operand" "0,I,dai,m,d"))]
196	"register_operand (operands[0], HImode)
197	\|\| register_operand (operands[1], HImode)"
198	"*
199	{
200	switch (which_alternative)
201	{
202	case 0:
203	return \"nop\";
204	case 1:
205	return \"clr %0\";
206	case 2:
207	if (GET_CODE (operands[1]) == CONST_DOUBLE)
208	{
209	rtx xoperands[2];
210	xoperands[0] = operands[0];
211	xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
212	output_asm_insn (\"mov %1,%0\", xoperands);
213	return \"\";
214	}
215	return \"mov %1,%0\";
216	case 3:
217	case 4:
218	return \"movhu %1,%0\";
219	default:
220	abort ();
221	}
222	}"
223	[(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
224
225	;; movsi and helpers
226
227	;; We use this to handle addition of two values when one operand is the
228	;; stack pointer and the other is a memory reference of some kind. Reload
229	;; does not handle them correctly without this expander.
230	(define_expand "reload_insi"
231	[(set (match_operand:SI 0 "register_operand" "=a")
232	(match_operand:SI 1 "impossible_plus_operand" ""))
233	(clobber (match_operand:SI 2 "register_operand" "=&r"))]
234	""
235	"
236	{
237	if (XEXP (operands[1], 0) == stack_pointer_rtx)
238	{
239	if (GET_CODE (XEXP (operands[1], 1)) == SUBREG
240	&& (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 1)))
241	> GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 1))))))
242	emit_move_insn (operands[2],
243	gen_rtx_ZERO_EXTEND
244	(GET_MODE (XEXP (operands[1], 1)),
245	SUBREG_REG (XEXP (operands[1], 1))));
246	else
247	emit_move_insn (operands[2], XEXP (operands[1], 1));
248	emit_move_insn (operands[0], XEXP (operands[1], 0));
249	}
250	else
251	{
252	if (GET_CODE (XEXP (operands[1], 0)) == SUBREG
253	&& (GET_MODE_SIZE (GET_MODE (XEXP (operands[1], 0)))
254	> GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (operands[1], 0))))))
255	emit_move_insn (operands[2],
256	gen_rtx_ZERO_EXTEND
257	(GET_MODE (XEXP (operands[1], 0)),
258	SUBREG_REG (XEXP (operands[1], 0))));
259	else
260	emit_move_insn (operands[2], XEXP (operands[1], 0));
261	emit_move_insn (operands[0], XEXP (operands[1], 1));
262	}
263	emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
264	DONE;
265	}")
266
267	(define_expand "movsi"
268	[(set (match_operand:SI 0 "general_operand" "")
269	(match_operand:SI 1 "general_operand" ""))]
270	""
271	"
272	{
273	/* One of the ops has to be in a register */
274	if (!register_operand (operand1, SImode)
275	&& !register_operand (operand0, SImode))
276	operands[1] = copy_to_mode_reg (SImode, operand1);
277	}")
278
279	(define_insn ""
280	[(set (match_operand:SI 0 "nonimmediate_operand"
281	"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,axR,!*y")
282	(match_operand:SI 1 "general_operand"
283	"0,0,I,I,dx,ax,dx,ax,dixm,aixm,dixm,aixm,!*y,axR"))]
284	"register_operand (operands[0], SImode)
285	\|\| register_operand (operands[1], SImode)"
286	"*
287	{
288	switch (which_alternative)
289	{
290	case 0:
291	case 1:
292	return \"nop\";
293	case 2:
294	return \"clr %0\";
295	case 3:
296	case 4:
297	case 5:
298	case 6:
299	case 7:
300	case 8:
301	case 9:
302	case 10:
303	case 11:
304	case 12:
305	case 13:
306	if (GET_CODE (operands[1]) == CONST_DOUBLE)
307	{
308	rtx xoperands[2];
309	xoperands[0] = operands[0];
310	xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
311	output_asm_insn (\"mov %1,%0\", xoperands);
312	return \"\";
313	}
314
315	if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
316	&& GET_CODE (operands[1]) == CONST_INT)
317	{
318	HOST_WIDE_INT val = INTVAL (operands[1]);
319
320	if (((val & 0x80) && ! (val & 0xffffff00))
321	\|\| ((val & 0x800000) && ! (val & 0xff000000)))
322	return \"movu %1,%0\";
323	}
324	return \"mov %1,%0\";
325	default:
326	abort ();
327	}
328	}"
329	[(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
330
331	(define_expand "movsf"
332	[(set (match_operand:SF 0 "general_operand" "")
333	(match_operand:SF 1 "general_operand" ""))]
334	""
335	"
336	{
337	/* One of the ops has to be in a register */
338	if (!register_operand (operand1, SFmode)
339	&& !register_operand (operand0, SFmode))
340	operands[1] = copy_to_mode_reg (SFmode, operand1);
341	}")
342
343	(define_insn ""
344	[(set (match_operand:SF 0 "nonimmediate_operand" "=dx,ax,dx,a,daxm,dax")
345	(match_operand:SF 1 "general_operand" "0,0,G,G,dax,daxFm"))]
346	"register_operand (operands[0], SFmode)
347	\|\| register_operand (operands[1], SFmode)"
348	"*
349	{
350	switch (which_alternative)
351	{
352	case 0:
353	case 1:
354	return \"nop\";
355	case 2:
356	return \"clr %0\";
357	case 3:
358	case 4:
359	case 5:
360	if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
361	&& GET_CODE (operands[1]) == CONST_INT)
362	{
363	HOST_WIDE_INT val = INTVAL (operands[1]);
364
365	if (((val & 0x80) && ! (val & 0xffffff00))
366	\|\| ((val & 0x800000) && ! (val & 0xff000000)))
367	return \"movu %1,%0\";
368	}
369	return \"mov %1,%0\";
370	default:
371	abort ();
372	}
373	}"
374	[(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit")])
375
376	(define_expand "movdi"
377	[(set (match_operand:DI 0 "general_operand" "")
378	(match_operand:DI 1 "general_operand" ""))]
379	""
380	"
381	{
382	/* One of the ops has to be in a register */
383	if (!register_operand (operand1, DImode)
384	&& !register_operand (operand0, DImode))
385	operands[1] = copy_to_mode_reg (DImode, operand1);
386	}")
387
388	(define_insn ""
389	[(set (match_operand:DI 0 "nonimmediate_operand"
390	"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
391	(match_operand:DI 1 "general_operand"
392	"0,0,I,I,dx,ax,dx,ax,dxim,axim,dxim,axim"))]
393	"register_operand (operands[0], DImode)
394	\|\| register_operand (operands[1], DImode)"
395	"*
396	{
397	long val[2];
398	REAL_VALUE_TYPE rv;
399
400	switch (which_alternative)
401	{
402	case 0:
403	case 1:
404	return \"nop\";
405
406	case 2:
407	return \"clr %L0\;clr %H0\";
408
409	case 3:
410	if (rtx_equal_p (operands[0], operands[1]))
411	return \"sub %L1,%L0\;mov %L0,%H0\";
412	else
413	return \"mov %1,%L0\;mov %L0,%H0\";
414	case 4:
415	case 5:
416	case 6:
417	case 7:
418	case 8:
419	case 9:
420	case 10:
421	case 11:
422	if (GET_CODE (operands[1]) == CONST_INT)
423	{
424	rtx low, high;
425	split_double (operands[1], &low, &high);
426	val[0] = INTVAL (low);
427	val[1] = INTVAL (high);
428	}
429	if (GET_CODE (operands[1]) == CONST_DOUBLE)
430	{
431	if (GET_MODE (operands[1]) == DFmode)
432	{
433	REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
434	REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
435	}
436	else if (GET_MODE (operands[1]) == VOIDmode
437	\|\| GET_MODE (operands[1]) == DImode)
438	{
439	val[0] = CONST_DOUBLE_LOW (operands[1]);
440	val[1] = CONST_DOUBLE_HIGH (operands[1]);
441	}
442	}
443
444	if (GET_CODE (operands[1]) == MEM
445	&& reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
446	{
447	rtx temp = operands[0];
448
449	while (GET_CODE (temp) == SUBREG)
450	temp = SUBREG_REG (temp);
451
452	if (GET_CODE (temp) != REG)
453	abort ();
454
455	if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
456	XEXP (operands[1], 0)))
457	return \"mov %H1,%H0\;mov %L1,%L0\";
458	else
459	return \"mov %L1,%L0\;mov %H1,%H0\";
460
461	}
462	else if (GET_CODE (operands[1]) == MEM
463	&& CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
464	&& REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
465	{
466	rtx xoperands[2];
467
468	xoperands[0] = operands[0];
469	xoperands[1] = XEXP (operands[1], 0);
470
471	output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
472	xoperands);
473	return \"\";
474	}
475	else
476	{
477	if ((GET_CODE (operands[1]) == CONST_INT
478	\|\| GET_CODE (operands[1]) == CONST_DOUBLE)
479	&& val[0] == 0)
480	{
481	if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
482	output_asm_insn (\"clr %L0\", operands);
483	else
484	output_asm_insn (\"mov %L1,%L0\", operands);
485	}
486	else if ((GET_CODE (operands[1]) == CONST_INT
487	\|\| GET_CODE (operands[1]) == CONST_DOUBLE)
488	&& (REGNO_REG_CLASS (true_regnum (operands[0]))
489	== EXTENDED_REGS)
490	&& (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
491	\|\| ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
492	output_asm_insn (\"movu %1,%0\", operands);
493	else
494	output_asm_insn (\"mov %L1,%L0\", operands);
495
496	if ((GET_CODE (operands[1]) == CONST_INT
497	\|\| GET_CODE (operands[1]) == CONST_DOUBLE)
498	&& val[1] == 0)
499	{
500	if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
501	output_asm_insn (\"clr %H0\", operands);
502	else
503	output_asm_insn (\"mov %H1,%H0\", operands);
504	}
505	else if ((GET_CODE (operands[1]) == CONST_INT
506	\|\| GET_CODE (operands[1]) == CONST_DOUBLE)
507	&& val[0] == val[1])
508	output_asm_insn (\"mov %L0,%H0\", operands);
509	else if ((GET_CODE (operands[1]) == CONST_INT
510	\|\| GET_CODE (operands[1]) == CONST_DOUBLE)
511	&& (REGNO_REG_CLASS (true_regnum (operands[0]))
512	== EXTENDED_REGS)
513	&& (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
514	\|\| ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
515	output_asm_insn (\"movu %1,%0\", operands);
516	else
517	output_asm_insn (\"mov %H1,%H0\", operands);
518	return \"\";
519	}
520	default:
521	abort ();
522	}
523	}"
524	[(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
525
526	(define_expand "movdf"
527	[(set (match_operand:DF 0 "general_operand" "")
528	(match_operand:DF 1 "general_operand" ""))]
529	""
530	"
531	{
532	/* One of the ops has to be in a register */
533	if (!register_operand (operand1, DFmode)
534	&& !register_operand (operand0, DFmode))
535	operands[1] = copy_to_mode_reg (DFmode, operand1);
536	}")
537
538	(define_insn ""
539	[(set (match_operand:DF 0 "nonimmediate_operand"
540	"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
541	(match_operand:DF 1 "general_operand"
542	"0,0,G,G,dx,ax,dx,ax,dxFm,axFm,dxFm,axFm"))]
543	"register_operand (operands[0], DFmode)
544	\|\| register_operand (operands[1], DFmode)"
545	"*
546	{
547	long val[2];
548	REAL_VALUE_TYPE rv;
549
550	switch (which_alternative)
551	{
552	case 0:
553	case 1:
554	return \"nop\";
555
556	case 2:
557	return \"clr %L0\;clr %H0\";
558
559	case 3:
560	if (rtx_equal_p (operands[0], operands[1]))
561	return \"sub %L1,%L0\;mov %L0,%H0\";
562	else
563	return \"mov %1,%L0\;mov %L0,%H0\";
564	case 4:
565	case 5:
566	case 6:
567	case 7:
568	case 8:
569	case 9:
570	case 10:
571	case 11:
572	if (GET_CODE (operands[1]) == CONST_INT)
573	{
574	rtx low, high;
575	split_double (operands[1], &low, &high);
576	val[0] = INTVAL (low);
577	val[1] = INTVAL (high);
578	}
579	if (GET_CODE (operands[1]) == CONST_DOUBLE)
580	{
581	if (GET_MODE (operands[1]) == DFmode)
582	{
583	REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
584	REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
585	}
586	else if (GET_MODE (operands[1]) == VOIDmode
587	\|\| GET_MODE (operands[1]) == DImode)
588	{
589	val[0] = CONST_DOUBLE_LOW (operands[1]);
590	val[1] = CONST_DOUBLE_HIGH (operands[1]);
591	}
592	}
593
594	if (GET_CODE (operands[1]) == MEM
595	&& reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
596	{
597	rtx temp = operands[0];
598
599	while (GET_CODE (temp) == SUBREG)
600	temp = SUBREG_REG (temp);
601
602	if (GET_CODE (temp) != REG)
603	abort ();
604
605	if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
606	XEXP (operands[1], 0)))
607	return \"mov %H1,%H0\;mov %L1,%L0\";
608	else
609	return \"mov %L1,%L0\;mov %H1,%H0\";
610
611	}
612	else if (GET_CODE (operands[1]) == MEM
613	&& CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
614	&& REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
615	{
616	rtx xoperands[2];
617
618	xoperands[0] = operands[0];
619	xoperands[1] = XEXP (operands[1], 0);
620
621	output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\",
622	xoperands);
623	return \"\";
624	}
625	else
626	{
627	if ((GET_CODE (operands[1]) == CONST_INT
628	\|\| GET_CODE (operands[1]) == CONST_DOUBLE)
629	&& val[0] == 0)
630	{
631	if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
632	output_asm_insn (\"clr %L0\", operands);
633	else
634	output_asm_insn (\"mov %L1,%L0\", operands);
635	}
636	else if ((GET_CODE (operands[1]) == CONST_INT
637	\|\| GET_CODE (operands[1]) == CONST_DOUBLE)
638	&& (REGNO_REG_CLASS (true_regnum (operands[0]))
639	== EXTENDED_REGS)
640	&& (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
641	\|\| ((val[0] & 0x800000) && ! (val[0] & 0xff000000))))
642	output_asm_insn (\"movu %1,%0\", operands);
643	else
644	output_asm_insn (\"mov %L1,%L0\", operands);
645
646	if ((GET_CODE (operands[1]) == CONST_INT
647	\|\| GET_CODE (operands[1]) == CONST_DOUBLE)
648	&& val[1] == 0)
649	{
650	if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
651	output_asm_insn (\"clr %H0\", operands);
652	else
653	output_asm_insn (\"mov %H1,%H0\", operands);
654	}
655	else if ((GET_CODE (operands[1]) == CONST_INT
656	\|\| GET_CODE (operands[1]) == CONST_DOUBLE)
657	&& val[0] == val[1])
658	output_asm_insn (\"mov %L0,%H0\", operands);
659	else if ((GET_CODE (operands[1]) == CONST_INT
660	\|\| GET_CODE (operands[1]) == CONST_DOUBLE)
661	&& (REGNO_REG_CLASS (true_regnum (operands[0]))
662	== EXTENDED_REGS)
663	&& (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
664	\|\| ((val[1] & 0x800000) && ! (val[1] & 0xff000000))))
665	output_asm_insn (\"movu %1,%0\", operands);
666	else
667	output_asm_insn (\"mov %H1,%H0\", operands);
668	return \"\";
669	}
670	default:
671	abort ();
672	}
673	}"
674	[(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
675
676
677
678
679	;; ----------------------------------------------------------------------
680	;; TEST INSTRUCTIONS
681	;; ----------------------------------------------------------------------
682
683	;; Go ahead and define tstsi so we can eliminate redundant tst insns
684	;; when we start trying to optimize this port.
685	(define_insn "tstsi"
686	[(set (cc0) (match_operand:SI 0 "register_operand" "dax"))]
687	""
688	"* return output_tst (operands[0], insn);"
689	[(set_attr "cc" "set_znv")])
690
691	(define_insn ""
692	[(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx,!a")))]
693	"TARGET_AM33"
694	"* return output_tst (operands[0], insn);"
695	[(set_attr "cc" "set_znv")])
696
697	(define_insn ""
698	[(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx")))]
699	""
700	"* return output_tst (operands[0], insn);"
701	[(set_attr "cc" "set_znv")])
702
703	(define_insn ""
704	[(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx,!a")))]
705	"TARGET_AM33"
706	"* return output_tst (operands[0], insn);"
707	[(set_attr "cc" "set_znv")])
708
709	(define_insn ""
710	[(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx")))]
711	""
712	"* return output_tst (operands[0], insn);"
713	[(set_attr "cc" "set_znv")])
714
715	;; Ordinarily, the cmp instruction will set the Z bit of cc0 to 1 if
716	;; its operands hold equal values, but the operands of a cmp
717	;; instruction must be distinct registers. In the case where we'd
718	;; like to compare a register to itself, we can achieve this effect
719	;; with a btst 0,d0 instead. (This will not alter the contents of d0
720	;; but will have the proper effect on cc0. Using d0 is arbitrary; any
721	;; data register would work.)
722
723	;; Even though the first alternative would be preferrable if it can
724	;; possibly match, reload must not be given the opportunity to attempt
725	;; to use it. It assumes that such matches can only occur when one of
726	;; the operands is used for input and the other for output. Since
727	;; this is not the case, it abort()s. Indeed, such a reload cannot be
728	;; possibly satisfied, so just mark the alternative with a `!', so
729	;; that it is not considered by reload.
730
731	(define_insn "cmpsi"
732	[(set (cc0)
733	(compare (match_operand:SI 0 "register_operand" "!da*x,dax")
734	(match_operand:SI 1 "nonmemory_operand" "*0,daxi")))]
735	""
736	"@
737	btst 0,d0
738	cmp %1,%0"
739	[(set_attr "cc" "compare,compare")])
740
741
742	;; ----------------------------------------------------------------------
743	;; ADD INSTRUCTIONS
744	;; ----------------------------------------------------------------------
745
746	(define_expand "addsi3"
747	[(set (match_operand:SI 0 "register_operand" "")
748	(plus:SI (match_operand:SI 1 "register_operand" "")
749	(match_operand:SI 2 "nonmemory_operand" "")))]
750	""
751	"")
752
753	(define_insn ""
754	[(set (match_operand:SI 0 "register_operand" "=dx,a,x,a,dax,!*y,!dax")
755	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,dax")
756	(match_operand:SI 2 "nonmemory_operand" "J,J,L,L,daxi,i,dax")))]
757	"TARGET_AM33"
758	"*
759	{
760	switch (which_alternative)
761	{
762	case 0:
763	case 1:
764	return \"inc %0\";
765	case 2:
766	case 3:
767	return \"inc4 %0\";
768	case 4:
769	case 5:
770	return \"add %2,%0\";
771	case 6:
772	{
773	enum reg_class src1_class, src2_class, dst_class;
774
775	src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
776	src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
777	dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
778
779	/* I'm not sure if this can happen or not. Might as well be prepared
780	and generate the best possible code if it does happen. */
781	if (true_regnum (operands[0]) == true_regnum (operands[1]))
782	return \"add %2,%0\";
783	if (true_regnum (operands[0]) == true_regnum (operands[2]))
784	return \"add %1,%0\";
785
786	/* Catch cases where no extended register was used. These should be
787	handled just like the mn10300. */
788	if (src1_class != EXTENDED_REGS
789	&& src2_class != EXTENDED_REGS
790	&& dst_class != EXTENDED_REGS)
791	{
792	/* We have to copy one of the sources into the destination, then
793	add the other source to the destination.
794
795	Carefully select which source to copy to the destination; a naive
796	implementation will waste a byte when the source classes are
797	different and the destination is an address register. Selecting
798	the lowest cost register copy will optimize this sequence. */
799	if (REGNO_REG_CLASS (true_regnum (operands[1]))
800	== REGNO_REG_CLASS (true_regnum (operands[0])))
801	return \"mov %1,%0\;add %2,%0\";
802	return \"mov %2,%0\;add %1,%0\";
803	}
804
805	/* At least one register is an extended register. */
806
807	/* The three operand add instruction on the am33 is a win iff the
808	output register is an extended register, or if both source
809	registers are extended registers. */
810	if (dst_class == EXTENDED_REGS
811	\|\| src1_class == src2_class)
812	return \"add %2,%1,%0\";
813
814	/* It is better to copy one of the sources to the destination, then
815	perform a 2 address add. The destination in this case must be
816	an address or data register and one of the sources must be an
817	extended register and the remaining source must not be an extended
818	register.
819
820	The best code for this case is to copy the extended reg to the
821	destination, then emit a two address add. */
822	if (src1_class == EXTENDED_REGS)
823	return \"mov %1,%0\;add %2,%0\";
824	return \"mov %2,%0\;add %1,%0\";
825	}
826	default:
827	abort ();
828	}
829	}"
830	[(set_attr "cc" "set_zn,none_0hit,set_zn,none_0hit,set_zn,none_0hit,set_zn")])
831
832	(define_insn ""
833	[(set (match_operand:SI 0 "register_operand" "=dx,a,a,dax,!*y,!dax")
834	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
835	(match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
836	""
837	"*
838	{
839	switch (which_alternative)
840	{
841	case 0:
842	case 1:
843	return \"inc %0\";
844	case 2:
845	return \"inc4 %0\";
846	case 3:
847	case 4:
848	return \"add %2,%0\";
849	case 5:
850	/* I'm not sure if this can happen or not. Might as well be prepared
851	and generate the best possible code if it does happen. */
852	if (true_regnum (operands[0]) == true_regnum (operands[1]))
853	return \"add %2,%0\";
854	if (true_regnum (operands[0]) == true_regnum (operands[2]))
855	return \"add %1,%0\";
856
857	/* We have to copy one of the sources into the destination, then add
858	the other source to the destination.
859
860	Carefully select which source to copy to the destination; a naive
861	implementation will waste a byte when the source classes are different
862	and the destination is an address register. Selecting the lowest
863	cost register copy will optimize this sequence. */
864	if (REGNO_REG_CLASS (true_regnum (operands[1]))
865	== REGNO_REG_CLASS (true_regnum (operands[0])))
866	return \"mov %1,%0\;add %2,%0\";
867	return \"mov %2,%0\;add %1,%0\";
868	default:
869	abort ();
870	}
871	}"
872	[(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
873
874	;; ----------------------------------------------------------------------
875	;; SUBTRACT INSTRUCTIONS
876	;; ----------------------------------------------------------------------
877
878	(define_expand "subsi3"
879	[(set (match_operand:SI 0 "register_operand" "")
880	(minus:SI (match_operand:SI 1 "register_operand" "")
881	(match_operand:SI 2 "nonmemory_operand" "")))]
882	""
883	"")
884
885	(define_insn ""
886	[(set (match_operand:SI 0 "register_operand" "=dax,!dax")
887	(minus:SI (match_operand:SI 1 "register_operand" "0,dax")
888	(match_operand:SI 2 "nonmemory_operand" "daxi,dax")))]
889	"TARGET_AM33"
890	"*
891	{
892	if (true_regnum (operands[0]) == true_regnum (operands[1]))
893	return \"sub %2,%0\";
894	else
895	{
896	enum reg_class src1_class, src2_class, dst_class;
897
898	src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
899	src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
900	dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
901
902	/* If no extended registers are used, then the best way to handle
903	this is to copy the first source operand into the destination
904	and emit a two address subtraction. */
905	if (src1_class != EXTENDED_REGS
906	&& src2_class != EXTENDED_REGS
907	&& dst_class != EXTENDED_REGS
908	&& true_regnum (operands[0]) != true_regnum (operands[2]))
909	return \"mov %1,%0\;sub %2,%0\";
910	return \"sub %2,%1,%0\";
911	}
912	}"
913	[(set_attr "cc" "set_zn")])
914
915	(define_insn ""
916	[(set (match_operand:SI 0 "register_operand" "=dax")
917	(minus:SI (match_operand:SI 1 "register_operand" "0")
918	(match_operand:SI 2 "nonmemory_operand" "daxi")))]
919	""
920	"sub %2,%0"
921	[(set_attr "cc" "set_zn")])
922
923	(define_expand "negsi2"
924	[(set (match_operand:SI 0 "register_operand" "")
925	(neg:SI (match_operand:SI 1 "register_operand" "")))]
926	""
927	"
928	{
929	rtx target = gen_reg_rtx (SImode);
930
931	emit_move_insn (target, GEN_INT (0));
932	emit_insn (gen_subsi3 (target, target, operands[1]));
933	emit_move_insn (operands[0], target);
934	DONE;
935	}")
936
937	;; ----------------------------------------------------------------------
938	;; MULTIPLY INSTRUCTIONS
939	;; ----------------------------------------------------------------------
940
941	(define_insn "mulsidi3"
942	[(set (match_operand:DI 0 "register_operand" "=dax")
943	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "dax"))
944	(sign_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
945	"TARGET_AM33"
946	"mul %1,%2,%H0,%L0"
947	[(set_attr "cc" "set_zn")])
948
949	(define_insn "umulsidi3"
950	[(set (match_operand:DI 0 "register_operand" "=dax")
951	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "dax"))
952	(zero_extend:DI (match_operand:SI 2 "register_operand" "dax"))))]
953	"TARGET_AM33"
954	"mulu %1,%2,%H0,%L0"
955	[(set_attr "cc" "set_zn")])
956
957	(define_expand "mulsi3"
958	[(set (match_operand:SI 0 "register_operand" "")
959	(mult:SI (match_operand:SI 1 "register_operand" "")
960	(match_operand:SI 2 "register_operand" "")))]
961	""
962	"")
963
964	(define_insn ""
965	[(set (match_operand:SI 0 "register_operand" "=dx,!dax")
966	(mult:SI (match_operand:SI 1 "register_operand" "%0,0")
967	(match_operand:SI 2 "nonmemory_operand" "dx,daxi")))]
968	"TARGET_AM33"
969	"*
970	{
971	if (TARGET_MULT_BUG)
972	return \"nop\;nop\;mul %2,%0\";
973	else
974	return \"mul %2,%0\";
975	}"
976	[(set_attr "cc" "set_zn")])
977
978	(define_insn ""
979	[(set (match_operand:SI 0 "register_operand" "=dx")
980	(mult:SI (match_operand:SI 1 "register_operand" "%0")
981	(match_operand:SI 2 "register_operand" "dx")))]
982	""
983	"*
984	{
985	if (TARGET_MULT_BUG)
986	return \"nop\;nop\;mul %2,%0\";
987	else
988	return \"mul %2,%0\";
989	}"
990	[(set_attr "cc" "set_zn")])
991
992	(define_insn "udivmodsi4"
993	[(set (match_operand:SI 0 "nonimmediate_operand" "=dx")
994	(udiv:SI (match_operand:SI 1 "general_operand" "0")
995	(match_operand:SI 2 "general_operand" "dx")))
996	(set (match_operand:SI 3 "nonimmediate_operand" "=&d")
997	(umod:SI (match_dup 1) (match_dup 2)))]
998	""
999	"*
1000	{
1001	output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
1002
1003	if (find_reg_note (insn, REG_UNUSED, operands[3]))
1004	return \"divu %2,%0\";
1005	else
1006	return \"divu %2,%0\;mov mdr,%3\";
1007	}"
1008	[(set_attr "cc" "set_zn")])
1009
1010	(define_insn "divmodsi4"
1011	[(set (match_operand:SI 0 "nonimmediate_operand" "=dx")
1012	(div:SI (match_operand:SI 1 "general_operand" "0")
1013	(match_operand:SI 2 "general_operand" "dx")))
1014	(set (match_operand:SI 3 "nonimmediate_operand" "=d")
1015	(mod:SI (match_dup 1) (match_dup 2)))]
1016	""
1017	"*
1018	{
1019	if (find_reg_note (insn, REG_UNUSED, operands[3]))
1020	return \"ext %0\;div %2,%0\";
1021	else
1022	return \"ext %0\;div %2,%0\;mov mdr,%3\";
1023	}"
1024	[(set_attr "cc" "set_zn")])
1025
1026
1027
1028	;; ----------------------------------------------------------------------
1029	;; AND INSTRUCTIONS
1030	;; ----------------------------------------------------------------------
1031
1032	(define_expand "andsi3"
1033	[(set (match_operand:SI 0 "register_operand" "")
1034	(and:SI (match_operand:SI 1 "register_operand" "")
1035	(match_operand:SI 2 "nonmemory_operand" "")))]
1036	""
1037	"")
1038
1039	(define_insn ""
1040	[(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax")
1041	(and:SI (match_operand:SI 1 "register_operand" "%0,0,dax")
1042	(match_operand:SI 2 "nonmemory_operand" "N,dxi,dax")))]
1043	"TARGET_AM33"
1044	"*
1045	{
1046	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
1047	return \"extbu %0\";
1048	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
1049	return \"exthu %0\";
1050	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
1051	return \"add %0,%0\;lsr 1,%0\";
1052	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
1053	return \"asl2 %0\;lsr 2,%0\";
1054	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
1055	return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
1056	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
1057	return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
1058	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
1059	return \"lsr 1,%0\;add %0,%0\";
1060	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
1061	return \"lsr 2,%0\;asl2 %0\";
1062	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
1063	return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
1064	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
1065	return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
1066	if (REG_P (operands[2]) && REG_P (operands[1])
1067	&& true_regnum (operands[0]) != true_regnum (operands[1])
1068	&& true_regnum (operands[0]) != true_regnum (operands[2])
1069	&& REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1070	&& REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1071	&& REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1072	return \"mov %1,%0\;and %2,%0\";
1073	if (REG_P (operands[2]) && REG_P (operands[1])
1074	&& true_regnum (operands[0]) != true_regnum (operands[1])
1075	&& true_regnum (operands[0]) != true_regnum (operands[2]))
1076	return \"and %1,%2,%0\";
1077	if (REG_P (operands[2]) && REG_P (operands[0])
1078	&& true_regnum (operands[2]) == true_regnum (operands[0]))
1079	return \"and %1,%0\";
1080	return \"and %2,%0\";
1081	}"
1082	[(set_attr "cc" "none_0hit,set_znv,set_znv")])
1083
1084	(define_insn ""
1085	[(set (match_operand:SI 0 "register_operand" "=dx,dx")
1086	(and:SI (match_operand:SI 1 "register_operand" "%0,0")
1087	(match_operand:SI 2 "nonmemory_operand" "N,dxi")))]
1088	""
1089	"*
1090	{
1091	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
1092	return \"extbu %0\";
1093	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
1094	return \"exthu %0\";
1095	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
1096	return \"add %0,%0\;lsr 1,%0\";
1097	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
1098	return \"asl2 %0\;lsr 2,%0\";
1099	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
1100	return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
1101	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
1102	return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
1103	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
1104	return \"lsr 1,%0\;add %0,%0\";
1105	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
1106	return \"lsr 2,%0\;asl2 %0\";
1107	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
1108	return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
1109	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
1110	return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
1111	return \"and %2,%0\";
1112	}"
1113	[(set_attr "cc" "none_0hit,set_znv")])
1114
1115	;; ----------------------------------------------------------------------
1116	;; OR INSTRUCTIONS
1117	;; ----------------------------------------------------------------------
1118
1119	(define_expand "iorsi3"
1120	[(set (match_operand:SI 0 "register_operand" "")
1121	(ior:SI (match_operand:SI 1 "register_operand" "")
1122	(match_operand:SI 2 "nonmemory_operand" "")))]
1123	""
1124	"")
1125
1126	(define_insn ""
1127	[(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1128	(ior:SI (match_operand:SI 1 "register_operand" "%0,dax")
1129	(match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
1130	"TARGET_AM33"
1131	"*
1132	{
1133	if (REG_P (operands[2]) && REG_P (operands[1])
1134	&& true_regnum (operands[0]) != true_regnum (operands[1])
1135	&& true_regnum (operands[0]) != true_regnum (operands[2])
1136	&& REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1137	&& REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1138	&& REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1139	return \"mov %1,%0\;or %2,%0\";
1140	if (REG_P (operands[2]) && REG_P (operands[1])
1141	&& true_regnum (operands[0]) != true_regnum (operands[1])
1142	&& true_regnum (operands[0]) != true_regnum (operands[2]))
1143	return \"or %1,%2,%0\";
1144	if (REG_P (operands[2]) && REG_P (operands[0])
1145	&& true_regnum (operands[2]) == true_regnum (operands[0]))
1146	return \"or %1,%0\";
1147	return \"or %2,%0\";
1148	}"
1149	[(set_attr "cc" "set_znv")])
1150
1151	(define_insn ""
1152	[(set (match_operand:SI 0 "register_operand" "=dx")
1153	(ior:SI (match_operand:SI 1 "register_operand" "%0")
1154	(match_operand:SI 2 "nonmemory_operand" "dxi")))]
1155	""
1156	"or %2,%0"
1157	[(set_attr "cc" "set_znv")])
1158
1159	;; ----------------------------------------------------------------------
1160	;; XOR INSTRUCTIONS
1161	;; ----------------------------------------------------------------------
1162
1163	(define_expand "xorsi3"
1164	[(set (match_operand:SI 0 "register_operand" "")
1165	(xor:SI (match_operand:SI 1 "register_operand" "")
1166	(match_operand:SI 2 "nonmemory_operand" "")))]
1167	""
1168	"")
1169
1170	(define_insn ""
1171	[(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1172	(xor:SI (match_operand:SI 1 "register_operand" "%0,dax")
1173	(match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
1174	"TARGET_AM33"
1175	"*
1176	{
1177	if (REG_P (operands[2]) && REG_P (operands[1])
1178	&& true_regnum (operands[0]) != true_regnum (operands[1])
1179	&& true_regnum (operands[0]) != true_regnum (operands[2])
1180	&& REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1181	&& REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1182	&& REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS)
1183	return \"mov %1,%0\;xor %2,%0\";
1184	if (REG_P (operands[2]) && REG_P (operands[1])
1185	&& true_regnum (operands[0]) != true_regnum (operands[1])
1186	&& true_regnum (operands[0]) != true_regnum (operands[2]))
1187	return \"xor %1,%2,%0\";
1188	if (REG_P (operands[2]) && REG_P (operands[0])
1189	&& true_regnum (operands[2]) == true_regnum (operands[0]))
1190	return \"xor %1,%0\";
1191	return \"xor %2,%0\";
1192	}"
1193	[(set_attr "cc" "set_znv")])
1194
1195	(define_insn ""
1196	[(set (match_operand:SI 0 "register_operand" "=dx")
1197	(xor:SI (match_operand:SI 1 "register_operand" "%0")
1198	(match_operand:SI 2 "nonmemory_operand" "dxi")))]
1199	""
1200	"xor %2,%0"
1201	[(set_attr "cc" "set_znv")])
1202
1203	;; ----------------------------------------------------------------------
1204	;; NOT INSTRUCTIONS
1205	;; ----------------------------------------------------------------------
1206
1207	(define_expand "one_cmplsi2"
1208	[(set (match_operand:SI 0 "register_operand" "")
1209	(not:SI (match_operand:SI 1 "register_operand" "")))]
1210	""
1211	"")
1212
1213	(define_insn ""
1214	[(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1215	(not:SI (match_operand:SI 1 "register_operand" "0,0")))]
1216	"TARGET_AM33"
1217	"not %0"
1218	[(set_attr "cc" "set_znv")])
1219
1220	(define_insn ""
1221	[(set (match_operand:SI 0 "register_operand" "=dx")
1222	(not:SI (match_operand:SI 1 "register_operand" "0")))]
1223	""
1224	"not %0"
1225	[(set_attr "cc" "set_znv")])
1226
1227
1228	;; -----------------------------------------------------------------
1229	;; BIT FIELDS
1230	;; -----------------------------------------------------------------
1231
1232
1233	;; These set/clear memory in byte sized chunks.
1234	;;
1235	;; They are no smaller/faster than loading the value into a register
1236	;; and storing the register, but they don't need a scratch register
1237	;; which may allow for better code generation.
1238	(define_insn ""
1239	[(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int 0))]
1240	""
1241	"@
1242	bclr 255,%A0
1243	clr %0"
1244	[(set_attr "cc" "clobber")])
1245
1246	(define_insn ""
1247	[(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int -1))]
1248	""
1249	"@
1250	bset 255,%A0
1251	mov -1,%0"
1252	[(set_attr "cc" "clobber,none_0hit")])
1253
1254	(define_insn ""
1255	[(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
1256	(subreg:QI
1257	(and:SI (subreg:SI (match_dup 0) 0)
1258	(match_operand:SI 1 "const_int_operand" "i,i")) 0))]
1259	""
1260	"@
1261	bclr %N1,%A0
1262	and %1,%0"
1263	[(set_attr "cc" "clobber,set_znv")])
1264
1265	(define_insn ""
1266	[(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
1267	(subreg:QI
1268	(ior:SI (subreg:SI (match_dup 0) 0)
1269	(match_operand:SI 1 "const_int_operand" "i,i")) 0))]
1270	""
1271	"@
1272	bset %1,%A0
1273	or %1,%0"
1274	[(set_attr "cc" "clobber,set_znv")])
1275
1276	(define_insn ""
1277	[(set (cc0)
1278	(zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
1279	(match_operand 1 "const_int_operand" "")
1280	(match_operand 2 "const_int_operand" "")))]
1281	""
1282	"*
1283	{
1284	int len = INTVAL (operands[1]);
1285	int bit = INTVAL (operands[2]);
1286	int mask = 0;
1287	rtx xoperands[2];
1288
1289	while (len > 0)
1290	{
1291	mask \|= (1 << bit);
1292	bit++;
1293	len--;
1294	}
1295
1296	xoperands[0] = operands[0];
1297	xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
1298	output_asm_insn (\"btst %1,%0\", xoperands);
1299	return \"\";
1300	}"
1301	[(set_attr "cc" "clobber")])
1302
1303	(define_insn ""
1304	[(set (cc0)
1305	(zero_extract:SI (match_operand:QI 0 "general_operand" "R,dx")
1306	(match_operand 1 "const_int_operand" "")
1307	(match_operand 2 "const_int_operand" "")))]
1308	"mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
1309	"*
1310	{
1311	int len = INTVAL (operands[1]);
1312	int bit = INTVAL (operands[2]);
1313	int mask = 0;
1314	rtx xoperands[2];
1315
1316	while (len > 0)
1317	{
1318	mask \|= (1 << bit);
1319	bit++;
1320	len--;
1321	}
1322
1323	/* If the source operand is not a reg (ie it is memory), then extract the
1324	bits from mask that we actually want to test. Note that the mask will
1325	never cross a byte boundary. */
1326	if (!REG_P (operands[0]))
1327	{
1328	if (mask & 0xff)
1329	mask = mask & 0xff;
1330	else if (mask & 0xff00)
1331	mask = (mask >> 8) & 0xff;
1332	else if (mask & 0xff0000)
1333	mask = (mask >> 16) & 0xff;
1334	else if (mask & 0xff000000)
1335	mask = (mask >> 24) & 0xff;
1336	}
1337
1338	xoperands[0] = operands[0];
1339	xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
1340	if (GET_CODE (operands[0]) == REG)
1341	output_asm_insn (\"btst %1,%0\", xoperands);
1342	else
1343	output_asm_insn (\"btst %1,%A0\", xoperands);
1344	return \"\";
1345	}"
1346	[(set_attr "cc" "clobber")])
1347
1348	(define_insn ""
1349	[(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "dx")
1350	(match_operand:SI 1 "const_int_operand" "")))]
1351	""
1352	"btst %1,%0"
1353	[(set_attr "cc" "clobber")])
1354
1355	(define_insn ""
1356	[(set (cc0)
1357	(and:SI
1358	(subreg:SI (match_operand:QI 0 "general_operand" "R,dx") 0)
1359	(match_operand:SI 1 "const_8bit_operand" "")))]
1360	""
1361	"@
1362	btst %1,%A0
1363	btst %1,%0"
1364	[(set_attr "cc" "clobber")])
1365
1366
1367
1368	;; ----------------------------------------------------------------------
1369	;; JUMP INSTRUCTIONS
1370	;; ----------------------------------------------------------------------
1371
1372	;; Conditional jump instructions
1373
1374	(define_expand "ble"
1375	[(set (pc)
1376	(if_then_else (le (cc0)
1377	(const_int 0))
1378	(label_ref (match_operand 0 "" ""))
1379	(pc)))]
1380	""
1381	"")
1382
1383	(define_expand "bleu"
1384	[(set (pc)
1385	(if_then_else (leu (cc0)
1386	(const_int 0))
1387	(label_ref (match_operand 0 "" ""))
1388	(pc)))]
1389	""
1390	"")
1391
1392	(define_expand "bge"
1393	[(set (pc)
1394	(if_then_else (ge (cc0)
1395	(const_int 0))
1396	(label_ref (match_operand 0 "" ""))
1397	(pc)))]
1398	""
1399	"")
1400
1401	(define_expand "bgeu"
1402	[(set (pc)
1403	(if_then_else (geu (cc0)
1404	(const_int 0))
1405	(label_ref (match_operand 0 "" ""))
1406	(pc)))]
1407	""
1408	"")
1409
1410	(define_expand "blt"
1411	[(set (pc)
1412	(if_then_else (lt (cc0)
1413	(const_int 0))
1414	(label_ref (match_operand 0 "" ""))
1415	(pc)))]
1416	""
1417	"")
1418
1419	(define_expand "bltu"
1420	[(set (pc)
1421	(if_then_else (ltu (cc0)
1422	(const_int 0))
1423	(label_ref (match_operand 0 "" ""))
1424	(pc)))]
1425	""
1426	"")
1427
1428	(define_expand "bgt"
1429	[(set (pc)
1430	(if_then_else (gt (cc0)
1431	(const_int 0))
1432	(label_ref (match_operand 0 "" ""))
1433	(pc)))]
1434	""
1435	"")
1436
1437	(define_expand "bgtu"
1438	[(set (pc)
1439	(if_then_else (gtu (cc0)
1440	(const_int 0))
1441	(label_ref (match_operand 0 "" ""))
1442	(pc)))]
1443	""
1444	"")
1445
1446	(define_expand "beq"
1447	[(set (pc)
1448	(if_then_else (eq (cc0)
1449	(const_int 0))
1450	(label_ref (match_operand 0 "" ""))
1451	(pc)))]
1452	""
1453	"")
1454
1455	(define_expand "bne"
1456	[(set (pc)
1457	(if_then_else (ne (cc0)
1458	(const_int 0))
1459	(label_ref (match_operand 0 "" ""))
1460	(pc)))]
1461	""
1462	"")
1463
1464	(define_insn ""
1465	[(set (pc)
1466	(if_then_else (match_operator 1 "comparison_operator"
1467	[(cc0) (const_int 0)])
1468	(label_ref (match_operand 0 "" ""))
1469	(pc)))]
1470	""
1471	"*
1472	{
1473	if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1474	&& (GET_CODE (operands[1]) == GT
1475	\|\| GET_CODE (operands[1]) == GE
1476	\|\| GET_CODE (operands[1]) == LE
1477	\|\| GET_CODE (operands[1]) == LT))
1478	return 0;
1479	return \"b%b1 %0\";
1480	}"
1481	[(set_attr "cc" "none")])
1482
1483	(define_insn ""
1484	[(set (pc)
1485	(if_then_else (match_operator 1 "comparison_operator"
1486	[(cc0) (const_int 0)])
1487	(pc)
1488	(label_ref (match_operand 0 "" ""))))]
1489	""
1490	"*
1491	{
1492	if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1493	&& (GET_CODE (operands[1]) == GT
1494	\|\| GET_CODE (operands[1]) == GE
1495	\|\| GET_CODE (operands[1]) == LE
1496	\|\| GET_CODE (operands[1]) == LT))
1497	return 0;
1498	return \"b%B1 %0\";
1499	}"
1500	[(set_attr "cc" "none")])
1501
1502	;; Unconditional and other jump instructions.
1503
1504	(define_insn "jump"
1505	[(set (pc)
1506	(label_ref (match_operand 0 "" "")))]
1507	""
1508	"jmp %l0"
1509	[(set_attr "cc" "none")])
1510
1511	(define_insn "indirect_jump"
1512	[(set (pc) (match_operand:SI 0 "register_operand" "a"))]
1513	""
1514	"jmp (%0)"
1515	[(set_attr "cc" "none")])
1516
1517	(define_insn "tablejump"
1518	[(set (pc) (match_operand:SI 0 "register_operand" "a"))
1519	(use (label_ref (match_operand 1 "" "")))]
1520	""
1521	"jmp (%0)"
1522	[(set_attr "cc" "none")])
1523
1524	;; Call subroutine with no return value.
1525
1526	(define_expand "call"
1527	[(call (match_operand:QI 0 "general_operand" "")
1528	(match_operand:SI 1 "general_operand" ""))]
1529	""
1530	"
1531	{
1532	if (! call_address_operand (XEXP (operands[0], 0), VOIDmode))
1533	XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
1534	emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1]));
1535	DONE;
1536	}")
1537
1538	(define_insn "call_internal"
1539	[(call (mem:QI (match_operand:SI 0 "call_address_operand" "aS"))
1540	(match_operand:SI 1 "general_operand" "g"))]
1541	""
1542	"*
1543	{
1544	if (REG_P (operands[0]))
1545	return \"calls %C0\";
1546	else
1547	return \"call %C0,[],0\";
1548	}"
1549	[(set_attr "cc" "clobber")])
1550
1551	;; Call subroutine, returning value in operand 0
1552	;; (which must be a hard register).
1553
1554	(define_expand "call_value"
1555	[(set (match_operand 0 "" "")
1556	(call (match_operand:QI 1 "general_operand" "")
1557	(match_operand:SI 2 "general_operand" "")))]
1558	""
1559	"
1560	{
1561	if (! call_address_operand (XEXP (operands[1], 0), VOIDmode))
1562	XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
1563	emit_call_insn (gen_call_value_internal (operands[0],
1564	XEXP (operands[1], 0),
1565	operands[2]));
1566	DONE;
1567	}")
1568
1569	(define_insn "call_value_internal"
1570	[(set (match_operand 0 "" "=dax")
1571	(call (mem:QI (match_operand:SI 1 "call_address_operand" "aS"))
1572	(match_operand:SI 2 "general_operand" "g")))]
1573	""
1574	"*
1575	{
1576	if (REG_P (operands[1]))
1577	return \"calls %C1\";
1578	else
1579	return \"call %C1,[],0\";
1580	}"
1581	[(set_attr "cc" "clobber")])
1582
1583	(define_expand "untyped_call"
1584	[(parallel [(call (match_operand 0 "" "")
1585	(const_int 0))
1586	(match_operand 1 "" "")
1587	(match_operand 2 "" "")])]
1588	""
1589	"
1590	{
1591	int i;
1592
1593	emit_call_insn (gen_call (operands[0], const0_rtx));
1594
1595	for (i = 0; i < XVECLEN (operands[2], 0); i++)
1596	{
1597	rtx set = XVECEXP (operands[2], 0, i);
1598	emit_move_insn (SET_DEST (set), SET_SRC (set));
1599	}
1600	DONE;
1601	}")
1602
1603	(define_insn "nop"
1604	[(const_int 0)]
1605	""
1606	"nop"
1607	[(set_attr "cc" "none")])
1608
1609
1610	;; ----------------------------------------------------------------------
1611	;; EXTEND INSTRUCTIONS
1612	;; ----------------------------------------------------------------------
1613
1614	(define_expand "zero_extendqisi2"
1615	[(set (match_operand:SI 0 "general_operand" "")
1616	(zero_extend:SI
1617	(match_operand:QI 1 "general_operand" "")))]
1618	""
1619	"")
1620
1621	(define_insn ""
1622	[(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx,!dax,!dax,!dax")
1623	(zero_extend:SI
1624	(match_operand:QI 1 "general_operand" "0,dax,m,0,dax,m")))]
1625	"TARGET_AM33"
1626	"@
1627	extbu %0
1628	mov %1,%0\;extbu %0
1629	movbu %1,%0
1630	extbu %0
1631	mov %1,%0\;extbu %0
1632	movbu %1,%0"
1633	[(set_attr "cc" "none_0hit")])
1634
1635	(define_insn ""
1636	[(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx")
1637	(zero_extend:SI
1638	(match_operand:QI 1 "general_operand" "0,d,m")))]
1639	""
1640	"@
1641	extbu %0
1642	mov %1,%0\;extbu %0
1643	movbu %1,%0"
1644	[(set_attr "cc" "none_0hit")])
1645
1646	(define_expand "zero_extendhisi2"
1647	[(set (match_operand:SI 0 "general_operand" "")
1648	(zero_extend:SI
1649	(match_operand:HI 1 "general_operand" "")))]
1650	""
1651	"")
1652
1653	(define_insn ""
1654	[(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx,!dax,!dax,!dax")
1655	(zero_extend:SI
1656	(match_operand:HI 1 "general_operand" "0,dax,m,0,dax,m")))]
1657	"TARGET_AM33"
1658	"@
1659	exthu %0
1660	mov %1,%0\;exthu %0
1661	movhu %1,%0
1662	exthu %0
1663	mov %1,%0\;exthu %0
1664	movhu %1,%0"
1665	[(set_attr "cc" "none_0hit")])
1666
1667	(define_insn ""
1668	[(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx")
1669	(zero_extend:SI
1670	(match_operand:HI 1 "general_operand" "0,dx,m")))]
1671	""
1672	"@
1673	exthu %0
1674	mov %1,%0\;exthu %0
1675	movhu %1,%0"
1676	[(set_attr "cc" "none_0hit")])
1677
1678	;;- sign extension instructions
1679
1680	(define_expand "extendqisi2"
1681	[(set (match_operand:SI 0 "general_operand" "")
1682	(sign_extend:SI
1683	(match_operand:QI 1 "general_operand" "")))]
1684	""
1685	"")
1686
1687	(define_insn ""
1688	[(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,!dax,!dax")
1689	(sign_extend:SI
1690	(match_operand:QI 1 "general_operand" "0,dx,0,dax")))]
1691	"TARGET_AM33"
1692	"@
1693	extb %0
1694	mov %1,%0\;extb %0
1695	extb %0
1696	mov %1,%0\;extb %0"
1697	[(set_attr "cc" "none_0hit")])
1698
1699	(define_insn ""
1700	[(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx")
1701	(sign_extend:SI
1702	(match_operand:QI 1 "general_operand" "0,dx")))]
1703	""
1704	"@
1705	extb %0
1706	mov %1,%0\;extb %0"
1707	[(set_attr "cc" "none_0hit")])
1708
1709	(define_expand "extendhisi2"
1710	[(set (match_operand:SI 0 "general_operand" "")
1711	(sign_extend:SI
1712	(match_operand:HI 1 "general_operand" "")))]
1713	""
1714	"")
1715
1716	(define_insn ""
1717	[(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,!dax,!dax")
1718	(sign_extend:SI
1719	(match_operand:HI 1 "general_operand" "0,dax,0,dax")))]
1720	"TARGET_AM33"
1721	"@
1722	exth %0
1723	mov %1,%0\;exth %0
1724	exth %0
1725	mov %1,%0\;exth %0"
1726	[(set_attr "cc" "none_0hit")])
1727
1728	(define_insn ""
1729	[(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx")
1730	(sign_extend:SI
1731	(match_operand:HI 1 "general_operand" "0,dx")))]
1732	""
1733	"@
1734	exth %0
1735	mov %1,%0\;exth %0"
1736	[(set_attr "cc" "none_0hit")])
1737
1738
1739	;; ----------------------------------------------------------------------
1740	;; SHIFTS
1741	;; ----------------------------------------------------------------------
1742
1743	(define_expand "ashlsi3"
1744	[(set (match_operand:SI 0 "register_operand" "")
1745	(ashift:SI
1746	(match_operand:SI 1 "register_operand" "")
1747	(match_operand:QI 2 "nonmemory_operand" "")))]
1748	""
1749	"")
1750
1751	(define_insn ""
1752	[(set (match_operand:SI 0 "register_operand" "=dax,dx,!dax")
1753	(ashift:SI
1754	(match_operand:SI 1 "register_operand" "0,0,dax")
1755	(match_operand:QI 2 "nonmemory_operand" "J,dxi,dax")))]
1756	"TARGET_AM33"
1757	"*
1758	{
1759	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 1)
1760	return \"add %0,%0\";
1761
1762	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 2)
1763	return \"asl2 %0\";
1764
1765	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 3
1766	&& REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
1767	return \"asl2 %0\;add %0,%0\";
1768
1769	if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 4
1770	&& REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
1771	return \"asl2 %0\;asl2 %0\";
1772
1773	if (true_regnum (operands[1]) == true_regnum (operands[0]))
1774	return \"asl %S2,%0\";
1775
1776	if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1777	&& REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1778	&& true_regnum (operands[0]) != true_regnum (operands[2]))
1779	return \"mov %1,%0\;asl %S2,%0\";
1780	return \"asl %2,%1,%0\";
1781	}"
1782	[(set_attr "cc" "set_zn")])
1783
1784	(define_insn ""
1785	[(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx")
1786	(ashift:SI
1787	(match_operand:SI 1 "register_operand" "0,0,0,0,0")
1788	(match_operand:QI 2 "nonmemory_operand" "J,K,M,L,dxi")))]
1789	""
1790	"@
1791	add %0,%0
1792	asl2 %0
1793	asl2 %0\;add %0,%0
1794	asl2 %0\;asl2 %0
1795	asl %S2,%0"
1796	[(set_attr "cc" "set_zn")])
1797
1798	(define_expand "lshrsi3"
1799	[(set (match_operand:SI 0 "register_operand" "")
1800	(lshiftrt:SI
1801	(match_operand:SI 1 "register_operand" "")
1802	(match_operand:QI 2 "nonmemory_operand" "")))]
1803	""
1804	"")
1805
1806	(define_insn ""
1807	[(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1808	(lshiftrt:SI
1809	(match_operand:SI 1 "register_operand" "0,dax")
1810	(match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
1811	"TARGET_AM33"
1812	"*
1813	{
1814	if (true_regnum (operands[1]) == true_regnum (operands[0]))
1815	return \"lsr %S2,%0\";
1816
1817	if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1818	&& REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1819	&& true_regnum (operands[0]) != true_regnum (operands[2]))
1820	return \"mov %1,%0\;lsr %S2,%0\";
1821	return \"lsr %2,%1,%0\";
1822	}"
1823	[(set_attr "cc" "set_zn")])
1824
1825	(define_insn ""
1826	[(set (match_operand:SI 0 "register_operand" "=dx")
1827	(lshiftrt:SI
1828	(match_operand:SI 1 "register_operand" "0")
1829	(match_operand:QI 2 "nonmemory_operand" "dxi")))]
1830	""
1831	"lsr %S2,%0"
1832	[(set_attr "cc" "set_zn")])
1833
1834	(define_expand "ashrsi3"
1835	[(set (match_operand:SI 0 "register_operand" "")
1836	(ashiftrt:SI
1837	(match_operand:SI 1 "register_operand" "")
1838	(match_operand:QI 2 "nonmemory_operand" "")))]
1839	""
1840	"")
1841
1842	(define_insn ""
1843	[(set (match_operand:SI 0 "register_operand" "=dx,!dax")
1844	(ashiftrt:SI
1845	(match_operand:SI 1 "register_operand" "0,dax")
1846	(match_operand:QI 2 "nonmemory_operand" "dxi,dax")))]
1847	"TARGET_AM33"
1848	"*
1849	{
1850	if (true_regnum (operands[1]) == true_regnum (operands[0]))
1851	return \"asr %S2,%0\";
1852
1853	if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS
1854	&& REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS
1855	&& true_regnum (operands[0]) != true_regnum (operands[2]))
1856	return \"mov %1,%0\;asr %S2,%0\";
1857	return \"asr %2,%1,%0\";
1858	}"
1859	[(set_attr "cc" "set_zn")])
1860
1861	(define_insn ""
1862	[(set (match_operand:SI 0 "register_operand" "=dx")
1863	(ashiftrt:SI
1864	(match_operand:SI 1 "register_operand" "0")
1865	(match_operand:QI 2 "nonmemory_operand" "dxi")))]
1866	""
1867	"asr %S2,%0"
1868	[(set_attr "cc" "set_zn")])
1869
1870	;; ----------------------------------------------------------------------
1871	;; FP INSTRUCTIONS
1872	;; ----------------------------------------------------------------------
1873	;;
1874	;; The mn103 series does not have floating point instructions, but since
1875	;; FP values are held in integer regs, we can clear the high bit easily
1876	;; which gives us an efficient inline floating point absolute value.
1877	;;
1878	;; Similarly for negation of a FP value.
1879	;;
1880
1881	(define_expand "absdf2"
1882	[(set (match_operand:DF 0 "register_operand" "")
1883	(abs:DF (match_operand:DF 1 "register_operand" "")))]
1884	""
1885	"
1886	{
1887	rtx target, result, insns;
1888
1889	start_sequence ();
1890	target = operand_subword (operands[0], 1, 1, DFmode);
1891	result = expand_binop (SImode, and_optab,
1892	operand_subword_force (operands[1], 1, DFmode),
1893	GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
1894
1895	if (result == 0)
1896	abort ();
1897
1898	if (result != target)
1899	emit_move_insn (result, target);
1900
1901	emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
1902	operand_subword_force (operands[1], 0, DFmode));
1903
1904	insns = get_insns ();
1905	end_sequence ();
1906
1907	emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
1908	DONE;
1909	}")
1910
1911	(define_expand "abssf2"
1912	[(set (match_operand:SF 0 "register_operand" "")
1913	(abs:SF (match_operand:SF 1 "register_operand" "")))]
1914	""
1915	"
1916	{
1917	rtx result;
1918	rtx target;
1919
1920	target = operand_subword_force (operands[0], 0, SFmode);
1921	result = expand_binop (SImode, and_optab,
1922	operand_subword_force (operands[1], 0, SFmode),
1923	GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
1924	if (result == 0)
1925	abort ();
1926
1927	if (result != target)
1928	emit_move_insn (result, target);
1929
1930	/* Make a place for REG_EQUAL. */
1931	emit_move_insn (operands[0], operands[0]);
1932	DONE;
1933	}")
1934
1935
1936	(define_expand "negdf2"
1937	[(set (match_operand:DF 0 "register_operand" "")
1938	(neg:DF (match_operand:DF 1 "register_operand" "")))]
1939	""
1940	"
1941	{
1942	rtx target, result, insns;
1943
1944	start_sequence ();
1945	target = operand_subword (operands[0], 1, 1, DFmode);
1946	result = expand_binop (SImode, xor_optab,
1947	operand_subword_force (operands[1], 1, DFmode),
1948	GEN_INT (trunc_int_for_mode (0x80000000, SImode)),
1949	target, 0, OPTAB_WIDEN);
1950
1951	if (result == 0)
1952	abort ();
1953
1954	if (result != target)
1955	emit_move_insn (result, target);
1956
1957	emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
1958	operand_subword_force (operands[1], 0, DFmode));
1959
1960	insns = get_insns ();
1961	end_sequence ();
1962
1963	emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
1964	DONE;
1965	}")
1966
1967	(define_expand "negsf2"
1968	[(set (match_operand:SF 0 "register_operand" "")
1969	(neg:SF (match_operand:SF 1 "register_operand" "")))]
1970	""
1971	"
1972	{
1973	rtx result;
1974	rtx target;
1975
1976	target = operand_subword_force (operands[0], 0, SFmode);
1977	result = expand_binop (SImode, xor_optab,
1978	operand_subword_force (operands[1], 0, SFmode),
1979	GEN_INT (trunc_int_for_mode (0x80000000, SImode)),
1980	target, 0, OPTAB_WIDEN);
1981	if (result == 0)
1982	abort ();
1983
1984	if (result != target)
1985	emit_move_insn (result, target);
1986
1987	/* Make a place for REG_EQUAL. */
1988	emit_move_insn (operands[0], operands[0]);
1989	DONE;
1990	}")
1991
1992
1993	;; ----------------------------------------------------------------------
1994	;; PROLOGUE/EPILOGUE
1995	;; ----------------------------------------------------------------------
1996	(define_expand "prologue"
1997	[(const_int 0)]
1998	""
1999	"expand_prologue (); DONE;")
2000
2001	(define_expand "epilogue"
2002	[(return)]
2003	""
2004	"
2005	{
2006	expand_epilogue ();
2007	DONE;
2008	}")
2009
2010	(define_insn "return_internal"
2011	[(const_int 2)
2012	(return)]
2013	""
2014	"rets"
2015	[(set_attr "cc" "clobber")])
2016
2017	;; This insn restores the callee saved registers and does a return, it
2018	;; can also deallocate stack space.
2019	(define_insn "return_internal_regs"
2020	[(const_int 0)
2021	(match_operand:SI 0 "const_int_operand" "i")
2022	(return)]
2023	""
2024	"*
2025	{
2026	fputs (\"\\tret \", asm_out_file);
2027	mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs ());
2028	fprintf (asm_out_file, \",%d\\n\", (int) INTVAL (operands[0]));
2029	return \"\";
2030	}"
2031	[(set_attr "cc" "clobber")])
2032
2033	;; This instruction matches one generated by mn10300_gen_multiple_store()
2034	(define_insn "store_movm"
2035	[(match_parallel 0 "store_multiple_operation"
2036	[(set (reg:SI 9) (plus:SI (reg:SI 9) (match_operand 1 "" "")))])]
2037	""
2038	"*
2039	{
2040	fputs (\"\\tmovm \", asm_out_file);
2041	mn10300_print_reg_list (asm_out_file,
2042	store_multiple_operation (operands[0], VOIDmode));
2043	fprintf (asm_out_file, \",(sp)\\n\");
2044	return \"\";
2045	}"
2046	[(set_attr "cc" "clobber")])
2047
2048	(define_insn "return"
2049	[(return)]
2050	"can_use_return_insn ()"
2051	"*
2052	{
2053	rtx next = next_active_insn (insn);
2054
2055	if (next
2056	&& GET_CODE (next) == JUMP_INSN
2057	&& GET_CODE (PATTERN (next)) == RETURN)
2058	return \"\";
2059	else
2060	return \"rets\";
2061	}"
2062	[(set_attr "cc" "clobber")])
2063
2064	;; Try to combine consecutive updates of the stack pointer (or any
2065	;; other register for that matter).
2066	(define_peephole
2067	[(set (match_operand:SI 0 "register_operand" "=dxay")
2068	(plus:SI (match_dup 0)
2069	(match_operand 1 "const_int_operand" "")))
2070	(set (match_dup 0)
2071	(plus:SI (match_dup 0)
2072	(match_operand 2 "const_int_operand" "")))]
2073	""
2074	"*
2075	{
2076	operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
2077	return \"add %1,%0\";
2078	}"
2079	[(set_attr "cc" "clobber")])
2080
2081	;;
2082	;; We had patterns to check eq/ne, but the they don't work because
2083	;; 0x80000000 + 0x80000000 = 0x0 with a carry out.
2084	;;
2085	;; The Z flag and C flag would be set, and we have no way to
2086	;; check for the Z flag set and C flag clear.
2087	;;
2088	;; This will work on the mn10200 because we can check the ZX flag
2089	;; if the comparison is in HImode.
2090	(define_peephole
2091	[(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2092	(set (pc) (if_then_else (ge (cc0) (const_int 0))
2093	(match_operand 1 "" "")
2094	(pc)))]
2095	"dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2096	"add %0,%0\;bcc %1"
2097	[(set_attr "cc" "clobber")])
2098
2099	(define_peephole
2100	[(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2101	(set (pc) (if_then_else (lt (cc0) (const_int 0))
2102	(match_operand 1 "" "")
2103	(pc)))]
2104	"dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2105	"add %0,%0\;bcs %1"
2106	[(set_attr "cc" "clobber")])
2107
2108	(define_peephole
2109	[(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2110	(set (pc) (if_then_else (ge (cc0) (const_int 0))
2111	(pc)
2112	(match_operand 1 "" "")))]
2113	"dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2114	"add %0,%0\;bcs %1"
2115	[(set_attr "cc" "clobber")])
2116
2117	(define_peephole
2118	[(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
2119	(set (pc) (if_then_else (lt (cc0) (const_int 0))
2120	(pc)
2121	(match_operand 1 "" "")))]
2122	"dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2123	"add %0,%0\;bcc %1"
2124	[(set_attr "cc" "clobber")])
2125

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