Ignore:
Timestamp:
Feb 6, 2017, 1:00:00 PM (8 years ago)
Author:
Silvan Scherrer
Message:

binutils: update trunk to version 2.27

Location:
binutils/trunk
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • binutils/trunk

  • TabularUnified binutils/trunk/opcodes/arm-dis.c

    r970 r1973  
    11/* Instruction printing code for the ARM
    2    Copyright (C) 1994-2014 Free Software Foundation, Inc.
     2   Copyright (C) 1994-2016 Free Software Foundation, Inc.
    33   Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
    44   Modification by James G. Smith (jsmith@cygnus.co.uk)
    … …  
    3535#include "elf/internal.h"
    3636#include "elf/arm.h"
     37#include "mach-o.h"
    3738
    3839/* FIXME: Belongs in global header.  */
    … …  
    7273struct opcode32
    7374{
    74   unsigned long arch;           /* Architecture defining this insn.  */
    75   unsigned long value;          /* If arch == 0 then value is a sentinel.  */
     75  arm_feature_set arch;         /* Architecture defining this insn.  */
     76  unsigned long value;          /* If arch is 0 then value is a sentinel.  */
    7677  unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
    7778  const char *  assembler;      /* How to disassemble this insn.  */
    … …  
    8081struct opcode16
    8182{
    82   unsigned long arch;           /* Architecture defining this insn.  */
     83  arm_feature_set arch;         /* Architecture defining this insn.  */
    8384  unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
    8485  const char *assembler;        /* How to disassemble this insn.  */
    … …  
    116117   %<bitfield>D         print as a NEON D register
    117118   %<bitfield>Q         print as a NEON Q register
     119   %<bitfield>E         print a quarter-float immediate value
    118120
    119121   %y<code>             print a single precision VFP reg.
    … …  
    125127   %<bitfield>`c        print specified char iff bitfield is all zeroes
    126128   %<bitfield>?ab...    select from array of values in big endian order
    127    
     129
    128130   %L                   print as an iWMMXt N/M width field.
    129131   %Z                   print the Immediate of a WSHUFH instruction.
    … …  
    149151{
    150152  /* XScale instructions.  */
    151   {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
    152   {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
    153   {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
    154   {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
    155   {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
     153  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     154    0x0e200010, 0x0fff0ff0,
     155    "mia%c\tacc0, %0-3r, %12-15r"},
     156  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     157    0x0e280010, 0x0fff0ff0,
     158    "miaph%c\tacc0, %0-3r, %12-15r"},
     159  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     160    0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
     161  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     162    0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
     163  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     164    0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
    156165
    157166  /* Intel Wireless MMX technology instructions.  */
    158   { 0, SENTINEL_IWMMXT_START, 0, "" },
    159   {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
    160   {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
    161   {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
    162   {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
    163   {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
    164   {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
    165   {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
    166   {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
    167   {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
    168   {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
    169   {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
    170   {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
    171   {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
    172   {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
    173   {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
    174   {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
    175   {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
    176   {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
    177   {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
    178   {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
    179   {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
    180   {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
    181   {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
    182   {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
    183   {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
    184   {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
    185   {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
    186   {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
    187   {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
    188   {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
    189   {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
    190   {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
    191   {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
    192   {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
    193   {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
    194   {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
    195   {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
    196   {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
    197   {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
    198   {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
    199   {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
    200   {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
    201   {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
    202   {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
    203   {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
    204   {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
    205   {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
    206   {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
    207   {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
    208   {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
    209   {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
    210   {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
    211   {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
    212   {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
    213   {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
    214   {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
    215   {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
    216   {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
    217   {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
    218   {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
    219   {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
    220   {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
    221   {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
    222   {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
    223   {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
    224   {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
    225   {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
    226   {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
    227   {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
    228   {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
    229   {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
    230   {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
    231   {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
    232   {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
    233   {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
    234   { 0, SENTINEL_IWMMXT_END, 0, "" },
     167  {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
     168  {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
     169    0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
     170  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     171    0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
     172  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     173    0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
     174  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     175    0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
     176  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     177    0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
     178  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     179    0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
     180  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     181    0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
     182  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     183    0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
     184  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     185    0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
     186  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     187    0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
     188  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     189    0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
     190  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     191    0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
     192  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     193    0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
     194  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     195    0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
     196  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     197    0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
     198  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     199    0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
     200  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     201    0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
     202  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     203    0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
     204  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     205    0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
     206  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     207    0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
     208  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     209    0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
     210  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     211    0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
     212  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     213    0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
     214  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     215    0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
     216  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     217    0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
     218  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     219    0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
     220  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     221    0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
     222  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     223    0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
     224  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     225    0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
     226  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     227    0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
     228  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     229    0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
     230  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     231    0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
     232  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     233    0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
     234  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     235    0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
     236  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     237    0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
     238  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     239    0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
     240  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     241    0x0e800120, 0x0f800ff0,
     242    "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
     243  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     244    0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
     245  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     246    0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
     247  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     248    0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
     249  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     250    0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
     251  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     252    0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
     253  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     254    0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
     255  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     256    0x0e8000a0, 0x0f800ff0,
     257    "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
     258  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     259    0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
     260  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     261    0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
     262  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     263    0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
     264  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     265    0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
     266  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     267    0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
     268  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     269    0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
     270  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     271    0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
     272  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     273    0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
     274  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     275    0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
     276  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     277    0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
     278  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     279    0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
     280  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     281    0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
     282  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     283    0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
     284  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     285    0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
     286  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     287    0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
     288  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     289    0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
     290  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     291    0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
     292  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     293    0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
     294  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     295    0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
     296  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     297    0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
     298  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     299    0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
     300  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     301    0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
     302  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     303    0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
     304  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     305    0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
     306  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     307    0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
     308  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     309    0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
     310  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     311    0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
     312  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     313    0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
     314  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     315    0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
     316  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     317    0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
     318  {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
     319    0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
     320  {ARM_FEATURE_CORE_LOW (0),
     321    SENTINEL_IWMMXT_END, 0, "" },
    235322
    236323  /* Floating point coprocessor (FPA) instructions.  */
    237   {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
    238   {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
    239   {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
    240   {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
    241   {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
    242   {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
    243   {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
    244   {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
    245   {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
    246   {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
    247   {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
    248   {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
    249   {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
    250   {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
    251   {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
    252   {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
    253   {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
    254   {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
    255   {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
    256   {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
    257   {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
    258   {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
    259   {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
    260   {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
    261   {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
    262   {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
    263   {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
    264   {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
    265   {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
    266   {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
    267   {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
    268   {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
    269   {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
    270   {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
    271   {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
    272   {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
    273   {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
    274   {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
    275   {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
    276   {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
    277   {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
    278   {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
    279   {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
     324  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     325    0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
     326  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     327    0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
     328  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     329    0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
     330  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     331    0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
     332  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     333    0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
     334  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     335    0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
     336  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     337    0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
     338  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     339    0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
     340  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     341    0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
     342  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     343    0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
     344  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     345    0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
     346  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     347    0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
     348  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     349    0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
     350  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     351    0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
     352  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     353    0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
     354  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     355    0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
     356  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     357    0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
     358  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     359    0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
     360  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     361    0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
     362  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     363    0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
     364  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     365    0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
     366  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     367    0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
     368  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     369    0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
     370  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     371    0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
     372  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     373    0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
     374  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     375    0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
     376  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     377    0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
     378  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     379    0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
     380  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     381    0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
     382  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     383    0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
     384  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     385    0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
     386  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     387    0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
     388  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     389    0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
     390  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     391    0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
     392  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     393    0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
     394  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     395    0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
     396  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     397    0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
     398  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     399    0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
     400  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     401    0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
     402  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     403    0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
     404  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
     405    0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
     406  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
     407    0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
     408  {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
     409    0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
     410
     411  /* ARMv8-M Mainline Security Extensions instructions.  */
     412  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
     413    0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
     414  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
     415    0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
    280416
    281417  /* Register load/store.  */
    282   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
    283   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
    284   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
    285   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
    286   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
    287   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
    288   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
    289   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
    290   {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
    291   {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
    292   {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
    293   {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
    294   {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
    295   {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
    296   {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
    297   {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
    298 
    299   {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
    300   {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
    301   {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
    302   {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
     418  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
     419    0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
     420  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
     421    0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
     422  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
     423    0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
     424  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
     425    0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
     426  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
     427    0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
     428  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
     429    0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
     430  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
     431    0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
     432  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
     433    0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
     434  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     435    0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
     436  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     437    0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
     438  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     439    0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
     440  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     441    0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
     442  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     443    0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
     444  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     445    0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
     446  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     447    0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
     448  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     449    0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
     450
     451  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     452    0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
     453  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     454    0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
     455  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     456    0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
     457  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     458    0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
    303459
    304460  /* Data transfer between ARM and NEON registers.  */
    305   {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
    306   {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
    307   {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
    308   {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
    309   {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
    310   {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
    311   {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
    312   {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
    313   {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
    314   {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
    315   {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
    316   {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
    317   {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
    318   {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
     461  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     462    0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
     463  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     464    0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
     465  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     466    0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
     467  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     468    0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
     469  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     470    0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
     471  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     472    0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
     473  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     474    0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
     475  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     476    0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
     477  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     478    0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
     479  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     480    0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
     481  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     482    0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
     483  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     484    0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
     485  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     486    0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
     487  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     488    0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
    319489  /* Half-precision conversion instructions.  */
    320   {FPU_VFP_EXT_ARMV8, 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
    321   {FPU_VFP_EXT_ARMV8, 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
    322   {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
    323   {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
     490  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     491    0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
     492  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     493    0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
     494  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
     495    0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
     496  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
     497    0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
    324498
    325499  /* Floating point coprocessor (VFP) instructions.  */
    326   {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
    327   {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
    328   {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
    329   {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
    330   {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
    331   {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
    332   {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
    333   {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
    334   {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
    335   {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
    336   {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
    337   {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
    338   {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
    339   {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
    340   {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
    341   {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
    342   {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
    343   {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
    344   {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
    345   {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
    346   {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
    347   {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
    348   {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
    349   {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
    350   {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
    351   {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
    352   {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
    353   {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
    354   {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
    355   {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
    356   {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
    357   {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
    358   {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
    359   {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
    360   {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
    361   {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
    362   {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
    363   {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
    364   {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
    365   {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
    366   {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
    367   {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
    368   {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
    369   {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
    370   {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
    371   {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
    372   {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
    373   {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
    374   {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
    375   {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
    376   {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
    377   {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
    378   {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
    379   {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
    380   {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
    381   {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
    382   {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
    383   {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
    384   {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
    385   {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
    386   {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
    387   {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
    388   {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
    389   {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
    390   {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
    391   {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
    392   {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
     500  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     501    0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
     502  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     503    0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
     504  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     505    0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
     506  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     507    0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
     508  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     509    0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
     510  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     511    0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
     512  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     513    0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
     514  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     515    0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
     516  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     517    0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
     518  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     519    0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
     520  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     521    0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
     522  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     523    0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
     524  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     525    0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
     526  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     527    0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
     528  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     529    0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
     530  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     531    0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
     532  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     533    0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
     534  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     535    0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
     536  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     537    0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
     538  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     539    0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
     540  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     541    0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
     542  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     543    0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
     544  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     545    0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
     546  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     547    0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
     548  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     549    0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
     550  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     551    0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
     552  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     553    0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
     554  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     555    0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
     556  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     557    0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
     558  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     559    0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
     560  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     561    0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
     562  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     563    0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
     564  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     565    0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
     566  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     567    0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
     568  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     569    0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
     570  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     571    0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
     572  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     573    0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
     574  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
     575    0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
     576  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
     577    0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
     578  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     579    0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
     580  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     581    0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
     582  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
     583    0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
     584  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
     585    0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
     586  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     587    0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
     588  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
     589    0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
     590  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
     591    0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
     592  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
     593    0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
     594  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
     595    0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
     596  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
     597    0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
     598  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     599    0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
     600  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     601    0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
     602  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     603    0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
     604  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     605    0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
     606  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     607    0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
     608  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     609    0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
     610  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     611    0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
     612  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     613    0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
     614  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     615    0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
     616  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     617    0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
     618  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     619    0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
     620  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     621    0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
     622  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     623    0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
     624  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     625    0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
     626  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     627    0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
     628  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     629    0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
     630  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     631    0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
     632  {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     633    0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
    393634
    394635  /* Cirrus coprocessor instructions.  */
    395   {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
    396   {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
    397   {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
    398   {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
    399   {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
    400   {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
    401   {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
    402   {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
    403   {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
    404   {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
    405   {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
    406   {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
    407   {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
    408   {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
    409   {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
    410   {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
    411   {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
    412   {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
    413   {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
    414   {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
    415   {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
    416   {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
    417   {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
    418   {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
    419   {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
    420   {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
    421   {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
    422   {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
    423   {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
    424   {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
    425   {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
    426   {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
    427   {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
    428   {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
    429   {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
    430   {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
    431   {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
    432   {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
    433   {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
    434   {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
    435   {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
    436   {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
    437   {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
    438   {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
    439   {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
    440   {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
    441   {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
    442   {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
    443   {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
    444   {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
    445   {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
    446   {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
    447   {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
    448   {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
    449   {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
    450   {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
    451   {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
    452   {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
    453   {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
    454   {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
    455   {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
    456   {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
    457   {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
    458   {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
    459   {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
    460   {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
    461   {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
    462   {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
    463   {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
    464   {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
    465   {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
    466   {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
    467   {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
    468   {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
    469   {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
    470   {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
    471   {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
    472   {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
    473   {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
    474   {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
    475   {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
    476   {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
    477   {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
    478   {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
     636  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     637    0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
     638  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     639    0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
     640  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     641    0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
     642  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     643    0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
     644  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     645    0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
     646  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     647    0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
     648  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     649    0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
     650  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     651    0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
     652  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     653    0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
     654  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     655    0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
     656  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     657    0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
     658  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     659    0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
     660  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     661    0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
     662  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     663    0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
     664  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     665    0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
     666  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     667    0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
     668  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     669    0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
     670  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     671    0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
     672  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     673    0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
     674  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     675    0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
     676  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     677    0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
     678  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     679    0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
     680  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     681    0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
     682  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     683    0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
     684  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     685    0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
     686  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     687    0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
     688  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     689    0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
     690  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     691    0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
     692  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     693    0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
     694  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     695    0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
     696  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     697    0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
     698  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     699    0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
     700  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     701    0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
     702  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     703    0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
     704  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     705    0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
     706  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     707    0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
     708  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     709    0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
     710  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     711    0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
     712  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     713    0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
     714  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     715    0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
     716  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     717    0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
     718  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     719    0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
     720  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     721    0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
     722  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     723    0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
     724  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     725    0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
     726  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     727    0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
     728  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     729    0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
     730  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     731    0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
     732  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     733    0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
     734  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     735    0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
     736  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     737    0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
     738  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     739    0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
     740  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     741    0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
     742  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     743    0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
     744  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     745    0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
     746  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     747    0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
     748  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     749    0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
     750  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     751    0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
     752  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     753    0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
     754  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     755    0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
     756  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     757    0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
     758  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     759    0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
     760  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     761    0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
     762  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     763    0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
     764  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     765    0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
     766  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     767    0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
     768  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     769    0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
     770  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     771    0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
     772  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     773    0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
     774  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     775    0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
     776  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     777    0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
     778  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     779    0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
     780  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     781    0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
     782  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     783    0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
     784  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     785    0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
     786  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     787    0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
     788  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     789    0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
     790  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     791    0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
     792  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     793    0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
     794  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     795    0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
     796  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     797    0x0e000600, 0x0ff00f10,
     798    "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
     799  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     800    0x0e100600, 0x0ff00f10,
     801    "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
     802  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     803    0x0e200600, 0x0ff00f10,
     804    "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
     805  {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
     806    0x0e300600, 0x0ff00f10,
     807    "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
    479808
    480809  /* VFP Fused multiply add instructions.  */
    481   {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
    482   {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
    483   {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
    484   {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
    485   {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
    486   {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
    487   {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
    488   {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
     810  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
     811    0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
     812  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
     813    0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
     814  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
     815    0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
     816  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
     817    0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
     818  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
     819    0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
     820  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
     821    0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
     822  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
     823    0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
     824  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
     825    0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
    489826
    490827  /* FP v5.  */
    491   {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
    492   {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
    493   {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
    494   {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
    495   {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
    496   {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
    497   {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
    498   {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
    499   {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
    500   {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
    501   {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
    502   {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
     828  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     829    0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
     830  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     831    0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
     832  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     833    0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
     834  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     835    0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
     836  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     837    0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
     838  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     839    0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
     840  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     841    0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
     842  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     843    0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
     844  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     845    0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
     846  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     847    0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
     848  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     849    0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
     850  {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     851    0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
    503852
    504853  /* Generic coprocessor instructions.  */
    505   { 0, SENTINEL_GENERIC_START, 0, "" },
    506   {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
    507   {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
    508   {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
    509   {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
    510   {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
    511   {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
    512   {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
    513   {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
     854  {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
     855  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
     856    0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
     857  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
     858    0x0c500000, 0x0ff00000,
     859    "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
     860  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
     861    0x0e000000, 0x0f000010,
     862    "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
     863  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
     864    0x0e10f010, 0x0f10f010,
     865    "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
     866  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
     867    0x0e100010, 0x0f100010,
     868    "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
     869  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
     870    0x0e000010, 0x0f100010,
     871    "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
     872  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
     873    0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
     874  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
     875    0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
    514876
    515877  /* V6 coprocessor instructions.  */
    516   {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
    517   {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
     878  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     879    0xfc500000, 0xfff00000,
     880    "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
     881  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     882    0xfc400000, 0xfff00000,
     883    "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
    518884
    519885  /* V5 coprocessor instructions.  */
    520   {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
    521   {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
    522   {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
    523   {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
    524   {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
    525 
    526   {0, 0, 0, 0}
     886  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
     887    0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
     888  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
     889    0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
     890  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
     891    0xfe000000, 0xff000010,
     892    "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
     893  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
     894    0xfe000010, 0xff100010,
     895    "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
     896  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
     897    0xfe100010, 0xff100010,
     898    "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
     899
     900  /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
     901     cp_num: bit <11:8> == 0b1001.
     902     cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
     903  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     904    0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
     905  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     906    0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
     907  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     908    0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
     909  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     910    0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
     911  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     912    0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
     913  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     914    0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
     915  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     916    0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
     917  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     918    0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
     919  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     920    0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
     921  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     922    0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
     923  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     924    0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
     925  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     926    0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
     927  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     928    0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
     929  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     930    0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
     931  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     932    0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
     933  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     934    0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
     935  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     936    0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
     937  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     938    0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
     939  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     940    0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
     941  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     942    0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
     943  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     944    0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
     945  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     946    0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
     947  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     948    0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
     949  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     950    0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
     951  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     952    0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
     953  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     954    0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
     955  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     956    0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
     957  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     958    0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
     959  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     960    0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
     961  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     962    0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
     963  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     964    0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
     965  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     966    0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
     967  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     968    0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
     969  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     970    0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
     971  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     972    0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
     973
     974  {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
    527975};
    528976
    … …  
    5541002   %<bitfield>Tn        print short scaled width limited by n
    5551003   %<bitfield>Un        print long scaled width limited by n
    556    
     1004
    5571005   %<bitfield>'c        print specified char iff bitfield is all ones
    5581006   %<bitfield>`c        print specified char iff bitfield is all zeroes
    … …  
    5621010{
    5631011  /* Extract.  */
    564   {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
    565   {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
     1012  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1013    0xf2b00840, 0xffb00850,
     1014    "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
     1015  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1016    0xf2b00000, 0xffb00810,
     1017    "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
    5661018
    5671019  /* Move data element to all lanes.  */
    568   {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
    569   {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
    570   {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
     1020  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1021    0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
     1022  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1023    0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
     1024  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1025    0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
    5711026
    5721027  /* Table lookup.  */
    573   {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
    574   {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
    575  
     1028  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1029    0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
     1030  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1031    0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
     1032
    5761033  /* Half-precision conversions.  */
    577   {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
    578   {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
     1034  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
     1035    0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
     1036  {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
     1037    0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
    5791038
    5801039  /* NEON fused multiply add instructions.  */
    581   {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    582   {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1040  {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
     1041    0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1042  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1043    0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1044  {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
     1045    0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1046  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1047    0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
    5831048
    5841049  /* Two registers, miscellaneous.  */
    585   {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
    586   {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
    587   {FPU_CRYPTO_EXT_ARMV8, 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
    588   {FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
    589   {FPU_CRYPTO_EXT_ARMV8, 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
    590   {FPU_CRYPTO_EXT_ARMV8, 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
    591   {FPU_CRYPTO_EXT_ARMV8, 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
    592   {FPU_CRYPTO_EXT_ARMV8, 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
    593   {FPU_CRYPTO_EXT_ARMV8, 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
    594   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
    595   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
    596   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
    597   {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
    598   {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
    599   {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
    600   {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
    601   {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
    602   {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
    603   {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
    604   {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
    605   {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
    606   {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
    607   {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
    608   {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
    609   {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
    610   {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
    611   {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
    612   {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
    613   {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
    614   {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
    615   {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
    616   {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
    617   {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
    618   {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
    619   {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
    620   {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
    621   {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
    622   {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
    623   {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
    624   {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
    625   {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
    626   {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
     1050  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
     1051    0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
     1052  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1053    0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
     1054  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
     1055    0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
     1056  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1057    0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
     1058  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1059    0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
     1060  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1061    0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
     1062  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1063    0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
     1064  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1065    0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
     1066  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1067    0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
     1068  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1069    0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
     1070  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1071    0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
     1072  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1073    0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
     1074  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1075    0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
     1076  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1077    0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
     1078  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1079    0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
     1080  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1081    0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
     1082  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1083    0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
     1084  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1085    0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
     1086  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1087    0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
     1088  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1089    0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
     1090  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1091    0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
     1092  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1093    0xf3b20300, 0xffb30fd0,
     1094    "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
     1095  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1096    0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
     1097  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1098    0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
     1099  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1100    0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
     1101  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1102    0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
     1103  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1104    0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
     1105  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1106    0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
     1107  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1108    0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
     1109  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1110    0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
     1111  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1112    0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
     1113  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1114    0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
     1115  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1116    0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
     1117  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1118    0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
     1119  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1120    0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
     1121  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1122    0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
     1123  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1124    0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
     1125  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1126    0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
     1127  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1128    0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
     1129  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1130    0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
     1131  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1132    0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
     1133  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1134    0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
     1135  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1136    0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
     1137  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1138    0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
     1139  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1140    0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
     1141  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1142    0xf3bb0600, 0xffbf0e10,
     1143    "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
     1144  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1145    0xf3b70600, 0xffbf0e10,
     1146    "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
    6271147
    6281148  /* Three registers of the same length.  */
    629   {FPU_CRYPTO_EXT_ARMV8, 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
    630   {FPU_CRYPTO_EXT_ARMV8, 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
    631   {FPU_CRYPTO_EXT_ARMV8, 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
    632   {FPU_CRYPTO_EXT_ARMV8, 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
    633   {FPU_CRYPTO_EXT_ARMV8, 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
    634   {FPU_CRYPTO_EXT_ARMV8, 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
    635   {FPU_CRYPTO_EXT_ARMV8, 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
    636   {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    637   {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    638   {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
    639   {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
    640   {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
    641   {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
    642   {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
    643   {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
    644   {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
    645   {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
    646   {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    647   {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    648   {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    649   {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    650   {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    651   {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    652   {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    653   {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    654   {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    655   {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    656   {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    657   {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    658   {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    659   {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    660   {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    661   {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    662   {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    663   {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
    664   {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
    665   {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    666   {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    667   {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
    668   {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    669   {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
    670   {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    671   {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    672   {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
    673   {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    674   {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
    675   {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    676   {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    677   {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
    678   {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    679   {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    680   {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
    681   {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
    682   {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
    683   {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
    684   {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    685   {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    686   {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    687   {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    688   {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    689   {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
    690   {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1149  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1150    0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
     1151  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1152    0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
     1153  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1154    0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
     1155  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1156    0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
     1157  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1158    0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
     1159  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1160    0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
     1161  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1162    0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
     1163  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
     1164    0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1165  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1166    0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1167  {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
     1168    0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1169  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1170    0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1171  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1172    0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1173  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1174    0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1175  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1176    0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1177  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1178    0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1179  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1180    0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1181  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1182    0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1183  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1184    0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1185  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1186    0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1187  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1188    0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1189  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1190    0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1191  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1192    0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1193  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1194    0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1195  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1196    0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1197  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1198    0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1199  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1200    0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1201  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1202    0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1203  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1204    0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1205  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1206    0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1207  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1208    0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1209  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1210    0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1211  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1212    0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1213  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1214    0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1215  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1216    0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1217  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1218    0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1219  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1220    0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1221  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1222    0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1223  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1224    0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1225  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1226    0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1227  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1228    0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1229  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1230    0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1231  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1232    0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1233  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1234    0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1235  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1236    0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1237  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1238    0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1239  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1240    0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1241  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1242    0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1243  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1244    0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1245  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1246    0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1247  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1248    0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1249  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1250    0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1251  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1252    0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1253  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1254    0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1255  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1256    0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1257  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1258    0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1259  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1260    0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1261  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1262    0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1263  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1264    0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1265  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1266    0xf2000b00, 0xff800f10,
     1267    "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1268  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1269    0xf2000b10, 0xff800f10,
     1270    "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1271  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1272    0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1273  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1274    0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1275  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1276    0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1277  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1278    0xf3000b00, 0xff800f10,
     1279    "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1280  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1281    0xf2000000, 0xfe800f10,
     1282    "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1283  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1284    0xf2000010, 0xfe800f10,
     1285    "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1286  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1287    0xf2000100, 0xfe800f10,
     1288    "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1289  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1290    0xf2000200, 0xfe800f10,
     1291    "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1292  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1293    0xf2000210, 0xfe800f10,
     1294    "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1295  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1296    0xf2000300, 0xfe800f10,
     1297    "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1298  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1299    0xf2000310, 0xfe800f10,
     1300    "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1301  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1302    0xf2000400, 0xfe800f10,
     1303    "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
     1304  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1305    0xf2000410, 0xfe800f10,
     1306    "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
     1307  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1308    0xf2000500, 0xfe800f10,
     1309    "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
     1310  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1311    0xf2000510, 0xfe800f10,
     1312    "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
     1313  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1314    0xf2000600, 0xfe800f10,
     1315    "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1316  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1317    0xf2000610, 0xfe800f10,
     1318    "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1319  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1320    0xf2000700, 0xfe800f10,
     1321    "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1322  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1323    0xf2000710, 0xfe800f10,
     1324    "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1325  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1326    0xf2000910, 0xfe800f10,
     1327    "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1328  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1329    0xf2000a00, 0xfe800f10,
     1330    "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1331  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1332    0xf2000a10, 0xfe800f10,
     1333    "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1334  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
     1335    0xf3000b10, 0xff800f10,
     1336    "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
     1337  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
     1338    0xf3000c10, 0xff800f10,
     1339    "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
    6911340
    6921341  /* One register and an immediate value.  */
    693   {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
    694   {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
    695   {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
    696   {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
    697   {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
    698   {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
    699   {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
    700   {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
    701   {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
    702   {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
    703   {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
    704   {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
    705   {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
     1342  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1343    0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
     1344  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1345    0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
     1346  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1347    0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
     1348  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1349    0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
     1350  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1351    0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
     1352  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1353    0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
     1354  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1355    0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
     1356  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1357    0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
     1358  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1359    0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
     1360  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1361    0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
     1362  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1363    0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
     1364  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1365    0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
     1366  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1367    0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
    7061368
    7071369  /* Two registers and a shift amount.  */
    708   {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
    709   {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
    710   {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
    711   {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
    712   {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
    713   {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
    714   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
    715   {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
    716   {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
    717   {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
    718   {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
    719   {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
    720   {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
    721   {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
    722   {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
    723   {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
    724   {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
    725   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
    726   {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
    727   {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
    728   {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
    729   {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
    730   {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
    731   {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
    732   {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
    733   {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
    734   {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
    735   {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
    736   {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
    737   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
    738   {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
    739   {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
    740   {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
    741   {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
    742   {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
    743   {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
    744   {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
    745   {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
    746   {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
    747   {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
    748   {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
    749   {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
    750   {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
    751   {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
    752   {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
    753   {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
    754   {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
    755   {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
    756   {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
    757   {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
    758   {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
    759   {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
    760   {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
    761   {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
    762   {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
    763   {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
    764   {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
    765   {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
     1370  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1371    0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
     1372  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1373    0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
     1374  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1375    0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
     1376  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1377    0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
     1378  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1379    0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
     1380  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1381    0xf2880950, 0xfeb80fd0,
     1382    "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
     1383  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1384    0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
     1385  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1386    0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
     1387  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1388    0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
     1389  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1390    0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
     1391  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1392    0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
     1393  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1394    0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
     1395  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1396    0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
     1397  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1398    0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
     1399  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1400    0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
     1401  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1402    0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
     1403  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1404    0xf2900950, 0xfeb00fd0,
     1405    "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
     1406  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1407    0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
     1408  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1409    0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
     1410  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1411    0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
     1412  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1413    0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
     1414  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1415    0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
     1416  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1417    0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
     1418  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1419    0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
     1420  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1421    0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
     1422  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1423    0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
     1424  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1425    0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
     1426  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1427    0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
     1428  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1429    0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
     1430  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1431    0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
     1432  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1433    0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
     1434  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1435    0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
     1436  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1437    0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
     1438  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1439    0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
     1440  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1441    0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
     1442  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1443    0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
     1444  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1445    0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
     1446  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1447    0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
     1448  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1449    0xf2a00950, 0xfea00fd0,
     1450    "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
     1451  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1452    0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
     1453  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1454    0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
     1455  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1456    0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
     1457  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1458    0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
     1459  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1460    0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
     1461  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1462    0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
     1463  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1464    0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
     1465  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1466    0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
     1467  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1468    0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
     1469  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1470    0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
     1471  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1472    0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
     1473  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1474    0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
     1475  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1476    0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
     1477  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1478    0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
     1479  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1480    0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
     1481  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1482    0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
     1483  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1484    0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
     1485  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1486    0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
     1487  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1488    0xf2a00e10, 0xfea00e90,
     1489    "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
     1490  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
     1491    0xf2a00c10, 0xfea00e90,
     1492    "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
    7661493
    7671494  /* Three registers of different lengths.  */
    768   {FPU_CRYPTO_EXT_ARMV8, 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    769   {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    770   {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
    771   {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
    772   {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    773   {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    774   {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    775   {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
    776   {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
    777   {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    778   {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
    779   {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    780   {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
    781   {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    782   {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    783   {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    784   {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    785   {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1495  {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
     1496    0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1497  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1498    0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1499  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1500    0xf2800400, 0xff800f50,
     1501    "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
     1502  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1503    0xf2800600, 0xff800f50,
     1504    "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
     1505  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1506    0xf2800900, 0xff800f50,
     1507    "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1508  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1509    0xf2800b00, 0xff800f50,
     1510    "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1511  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1512    0xf2800d00, 0xff800f50,
     1513    "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1514  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1515    0xf3800400, 0xff800f50,
     1516    "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
     1517  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1518    0xf3800600, 0xff800f50,
     1519    "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
     1520  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1521    0xf2800000, 0xfe800f50,
     1522    "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1523  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1524    0xf2800100, 0xfe800f50,
     1525    "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
     1526  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1527    0xf2800200, 0xfe800f50,
     1528    "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1529  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1530    0xf2800300, 0xfe800f50,
     1531    "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
     1532  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1533    0xf2800500, 0xfe800f50,
     1534    "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1535  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1536    0xf2800700, 0xfe800f50,
     1537    "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1538  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1539    0xf2800800, 0xfe800f50,
     1540    "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1541  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1542    0xf2800a00, 0xfe800f50,
     1543    "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
     1544  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1545    0xf2800c00, 0xfe800f50,
     1546    "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
    7861547
    7871548  /* Two registers and a scalar.  */
    788   {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
    789   {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
    790   {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
    791   {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
    792   {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
    793   {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
    794   {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
    795   {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
    796   {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
    797   {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
    798   {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
    799   {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
    800   {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
    801   {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
    802   {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
    803   {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
    804   {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
    805   {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
    806   {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
    807   {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
    808   {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
    809   {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
     1549  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1550    0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
     1551  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1552    0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
     1553  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
     1554    0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
     1555  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1556    0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
     1557  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1558    0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
     1559  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1560    0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
     1561  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
     1562    0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
     1563  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1564    0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
     1565  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1566    0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
     1567  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1568    0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
     1569  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
     1570    0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
     1571  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1572    0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
     1573  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1574    0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
     1575  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1576    0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
     1577  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1578    0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
     1579  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1580    0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
     1581  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
     1582    0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
     1583  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1584    0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
     1585  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1586    0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
     1587  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
     1588    0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
     1589  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1590    0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
     1591  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1592    0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
     1593  {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
     1594    0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
     1595  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1596    0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
     1597  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1598    0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
     1599  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1600    0xf2800240, 0xfe800f50,
     1601    "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
     1602  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1603    0xf2800640, 0xfe800f50,
     1604    "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
     1605  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1606    0xf2800a40, 0xfe800f50,
     1607    "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
     1608  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
     1609    0xf2800e40, 0xff800f50,
     1610   "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
     1611  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
     1612    0xf2800f40, 0xff800f50,
     1613   "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
     1614  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
     1615    0xf3800e40, 0xff800f50,
     1616   "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
     1617  {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
     1618    0xf3800f40, 0xff800f50,
     1619   "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
     1620  },
    8101621
    8111622  /* Element and structure load/store.  */
    812   {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
    813   {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
    814   {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
    815   {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
    816   {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
    817   {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
    818   {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
    819   {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
    820   {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
    821   {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
    822   {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
    823   {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
    824   {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
    825   {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
    826   {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
    827   {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
    828   {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
    829   {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
    830   {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
    831 
    832   {0,0 ,0, 0}
     1623  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1624    0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
     1625  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1626    0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
     1627  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1628    0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
     1629  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1630    0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
     1631  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1632    0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
     1633  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1634    0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
     1635  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1636    0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
     1637  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1638    0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
     1639  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1640    0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
     1641  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1642    0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
     1643  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1644    0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
     1645  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1646    0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
     1647  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1648    0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
     1649  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1650    0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
     1651  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1652    0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
     1653  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1654    0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
     1655  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1656    0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
     1657  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1658    0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
     1659  {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
     1660    0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
     1661
     1662  {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
    8331663};
    8341664
    … …  
    8611691   %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
    8621692   %<bitfield>d         print the bitfield in decimal
    863    %<bitfield>W         print the bitfield plus one in decimal 
     1693   %<bitfield>W         print the bitfield plus one in decimal
    8641694   %<bitfield>x         print the bitfield in hex
    8651695   %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
    866    
     1696
    8671697   %<bitfield>'c        print specified char iff bitfield is all ones
    8681698   %<bitfield>`c        print specified char iff bitfield is all zeroes
    … …  
    8771707{
    8781708  /* ARM instructions.  */
    879   {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
    880   {ARM_EXT_V1, 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
    881 
    882   {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
    883   {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
    884   {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
    885   {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
    886   {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
    887   {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
     1709  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     1710    0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
     1711  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     1712    0xe7f000f0, 0xfff000f0, "udf\t#%e"},
     1713
     1714  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
     1715    0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
     1716  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
     1717    0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
     1718  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
     1719    0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
     1720  {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
     1721    0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
     1722  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
     1723    0x00800090, 0x0fa000f0,
     1724    "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
     1725  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
     1726    0x00a00090, 0x0fa000f0,
     1727    "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
     1728
     1729  /* V8.2 RAS extension instructions.  */
     1730  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
     1731    0xe320f010, 0xffffffff, "esb"},
    8881732
    8891733  /* V8 instructions.  */
    890   {ARM_EXT_V8,   0x0320f005, 0x0fffffff, "sevl"},
    891   {ARM_EXT_V8,   0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
    892   {ARM_EXT_V8,   0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
    893   {ARM_EXT_V8,   0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
    894   {ARM_EXT_V8,   0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
    895   {ARM_EXT_V8,   0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
    896   {ARM_EXT_V8,   0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
    897   {ARM_EXT_V8,   0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
    898   {ARM_EXT_V8,   0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
    899   {ARM_EXT_V8,   0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
    900   {ARM_EXT_V8,   0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
    901   {ARM_EXT_V8,   0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
    902   {ARM_EXT_V8,   0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
    903   {ARM_EXT_V8,   0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
    904   {ARM_EXT_V8,   0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
    905   {ARM_EXT_V8,   0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
     1734  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     1735    0x0320f005, 0x0fffffff, "sevl"},
     1736  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     1737    0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
     1738  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
     1739    0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
     1740  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     1741    0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
     1742  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     1743    0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
     1744  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     1745    0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
     1746  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     1747    0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
     1748  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     1749    0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
     1750  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     1751    0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
     1752  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     1753    0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
     1754  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     1755    0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
     1756  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     1757    0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
     1758  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     1759    0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
     1760  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     1761    0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
     1762  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     1763    0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
     1764  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     1765    0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
    9061766  /* CRC32 instructions.  */
    907   {CRC_EXT_ARMV8, 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
    908   {CRC_EXT_ARMV8, 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
    909   {CRC_EXT_ARMV8, 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
    910   {CRC_EXT_ARMV8, 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
    911   {CRC_EXT_ARMV8, 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
    912   {CRC_EXT_ARMV8, 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
     1767  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     1768    0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
     1769  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     1770    0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
     1771  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     1772    0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
     1773  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     1774    0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
     1775  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     1776    0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
     1777  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     1778    0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
     1779
     1780  /* Privileged Access Never extension instructions.  */
     1781  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
     1782    0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
    9131783
    9141784  /* Virtualization Extension instructions.  */
    915   {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
    916   {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
     1785  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
     1786  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
    9171787
    9181788  /* Integer Divide Extension instructions.  */
    919   {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
    920   {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
     1789  {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
     1790    0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
     1791  {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
     1792    0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
    9211793
    9221794  /* MP Extension instructions.  */
    923   {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"},
     1795  {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
    9241796
    9251797  /* V7 instructions.  */
    926   {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
    927   {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
    928   {ARM_EXT_V8, 0xf57ff051, 0xfffffff3, "dmb\t%U"},
    929   {ARM_EXT_V8, 0xf57ff041, 0xfffffff3, "dsb\t%U"},
    930   {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
    931   {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
    932   {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
     1798  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
     1799  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
     1800  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
     1801  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
     1802  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
     1803  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
     1804  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
     1805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
     1806    0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
    9331807
    9341808  /* ARM V6T2 instructions.  */
    935   {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
    936   {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
    937   {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
    938   {ARM_EXT_V6T2, 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
    939 
    940   {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
    941   {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
    942  
    943   {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
    944   {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
    945   {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
    946   {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
     1809  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     1810    0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
     1811  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     1812    0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
     1813  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     1814    0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
     1815  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     1816    0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
     1817
     1818  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     1819    0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
     1820  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     1821    0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
     1822
     1823  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     1824    0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
     1825  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     1826    0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
     1827  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     1828    0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
     1829  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     1830    0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
    9471831
    9481832  /* ARM Security extension instructions.  */
    949   {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
     1833  {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
     1834    0x01600070, 0x0ff000f0, "smc%c\t%e"},
    9501835
    9511836  /* ARM V6K instructions.  */
    952   {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
    953   {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
    954   {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
    955   {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
    956   {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
    957   {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
    958   {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
     1837  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1838    0xf57ff01f, 0xffffffff, "clrex"},
     1839  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1840    0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
     1841  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1842    0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
     1843  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1844    0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
     1845  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1846    0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
     1847  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1848    0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
     1849  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1850    0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
    9591851
    9601852  /* ARM V6K NOP hints.  */
    961   {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
    962   {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
    963   {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
    964   {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
    965   {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
     1853  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1854    0x0320f001, 0x0fffffff, "yield%c"},
     1855  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1856    0x0320f002, 0x0fffffff, "wfe%c"},
     1857  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1858    0x0320f003, 0x0fffffff, "wfi%c"},
     1859  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1860    0x0320f004, 0x0fffffff, "sev%c"},
     1861  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     1862    0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
    9661863
    9671864  /* ARM V6 instructions.  */
    968   {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
    969   {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
    970   {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
    971   {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
    972   {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
    973   {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
    974   {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
    975   {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
    976   {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
    977   {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
    978   {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
    979   {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
    980   {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
    981   {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
    982   {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
    983   {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
    984   {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
    985   {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
    986   {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
    987   {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
    988   {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
    989   {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
    990   {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
    991   {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
    992   {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
    993   {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
    994   {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
    995   {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
    996   {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
    997   {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
    998   {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
    999   {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
    1000   {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
    1001   {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
    1002   {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
    1003   {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
    1004   {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
    1005   {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
    1006   {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
    1007   {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
    1008   {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
    1009   {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
    1010   {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
    1011   {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
    1012   {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
    1013   {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
    1014   {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
    1015   {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
    1016   {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
    1017   {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
    1018   {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
    1019   {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
    1020   {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
    1021   {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
    1022   {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
    1023   {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
    1024   {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
    1025   {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
    1026   {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
    1027   {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
    1028   {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
    1029   {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
    1030   {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
    1031   {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
    1032   {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
    1033   {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
    1034   {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
    1035   {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
    1036   {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
    1037   {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
    1038   {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
    1039   {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
    1040   {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
    1041   {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
    1042   {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
    1043   {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
    1044   {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
    1045   {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
    1046   {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
    1047   {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
    1048   {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
    1049   {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
    1050   {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
    1051   {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
    1052   {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
    1053   {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
    1054   {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
    1055   {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
    1056   {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
    1057   {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
    1058   {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
    1059   {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
    1060   {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
    1061   {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
    1062   {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
    1063   {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
    1064   {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
    1065   {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
    1066   {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
    1067   {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
    1068   {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
    1069   {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
    1070   {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
    1071   {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
    1072   {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
    1073   {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
    1074   {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
    1075   {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
    1076   {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
    1077   {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
    1078   {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
    1079   {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
    1080   {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
    1081   {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
    1082   {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
    1083   {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
    1084   {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
    1085   {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
    1086   {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
    1087   {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
    1088   {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
    1089   {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
     1865  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1866    0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
     1867  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1868    0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
     1869  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1870    0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
     1871  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1872    0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
     1873  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1874    0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
     1875  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1876    0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
     1877  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1878    0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
     1879  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1880    0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
     1881  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1882    0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
     1883  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1884    0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
     1885  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1886    0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
     1887  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1888    0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
     1889  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1890    0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
     1891  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1892    0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
     1893  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1894    0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
     1895  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1896    0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
     1897  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1898    0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
     1899  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1900    0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
     1901  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1902    0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
     1903  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1904    0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
     1905  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1906    0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
     1907  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1908    0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
     1909  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1910    0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
     1911  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1912    0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
     1913  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1914    0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
     1915  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1916    0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
     1917  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1918    0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
     1919  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1920    0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
     1921  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1922    0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
     1923  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1924    0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
     1925  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1926    0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
     1927  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1928    0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
     1929  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1930    0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
     1931  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1932    0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
     1933  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1934    0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
     1935  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1936    0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
     1937  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1938    0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
     1939  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1940    0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
     1941  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1942    0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
     1943  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1944    0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
     1945  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1946    0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
     1947  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1948    0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
     1949  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1950    0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
     1951  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1952    0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
     1953  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1954    0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
     1955  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1956    0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
     1957  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1958    0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
     1959  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1960    0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
     1961  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1962    0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
     1963  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1964    0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
     1965  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1966    0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
     1967  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1968    0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
     1969  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1970    0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
     1971  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1972    0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
     1973  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1974    0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
     1975  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1976    0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
     1977  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1978    0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
     1979  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1980    0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
     1981  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1982    0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
     1983  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1984    0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
     1985  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1986    0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
     1987  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1988    0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
     1989  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1990    0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
     1991  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1992    0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
     1993  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1994    0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
     1995  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1996    0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
     1997  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     1998    0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
     1999  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2000    0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
     2001  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2002    0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
     2003  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2004    0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
     2005  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2006    0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
     2007  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2008    0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
     2009  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2010    0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
     2011  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2012    0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
     2013  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2014    0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
     2015  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2016    0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
     2017  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2018    0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
     2019  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2020    0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
     2021  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2022    0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
     2023  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2024    0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
     2025  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2026    0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
     2027  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2028    0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
     2029  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2030    0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
     2031  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2032    0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
     2033  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2034    0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
     2035  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2036    0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
     2037  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2038    0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
     2039  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2040    0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
     2041  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2042    0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
     2043  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2044    0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
     2045  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2046    0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
     2047  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2048    0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
     2049  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2050    0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
     2051  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2052    0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
     2053  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2054    0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
     2055  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2056    0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
     2057  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2058    0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
     2059  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2060    0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
     2061  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2062    0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
     2063  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2064    0xf1010000, 0xfffffc00, "setend\t%9?ble"},
     2065  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2066    0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
     2067  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2068    0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
     2069  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2070    0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
     2071  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2072    0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
     2073  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2074    0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
     2075  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2076    0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
     2077  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2078    0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
     2079  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2080    0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
     2081  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2082    0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
     2083  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2084    0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
     2085  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2086    0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
     2087  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2088    0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
     2089  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2090    0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
     2091  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2092    0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
     2093  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2094    0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
     2095  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2096    0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
     2097  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2098    0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
     2099  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2100    0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
     2101  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2102    0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
     2103  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2104    0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
     2105  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2106    0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
     2107  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     2108    0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
    10902109
    10912110  /* V5J instruction.  */
    1092   {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
     2111  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
     2112    0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
    10932113
    10942114  /* V5 Instructions.  */
    1095   {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
    1096   {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
    1097   {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
    1098   {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
    1099 
    1100   /* V5E "El Segundo" Instructions.  */   
    1101   {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
    1102   {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
    1103   {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
    1104   {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
    1105   {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
    1106   {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
    1107   {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
    1108 
    1109   {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
    1110   {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
    1111 
    1112   {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
    1113   {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
    1114   {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
    1115   {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
    1116 
    1117   {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
    1118   {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
    1119   {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
    1120   {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
    1121 
    1122   {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
    1123   {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
    1124 
    1125   {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
    1126   {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
    1127   {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
    1128   {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
     2115  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
     2116    0xe1200070, 0xfff000f0,
     2117    "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
     2118  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
     2119    0xfa000000, 0xfe000000, "blx\t%B"},
     2120  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
     2121    0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
     2122  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
     2123    0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
     2124
     2125  /* V5E "El Segundo" Instructions.  */
     2126  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
     2127    0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
     2128  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
     2129    0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
     2130  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
     2131    0xf450f000, 0xfc70f000, "pld\t%a"},
     2132  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2133    0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
     2134  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2135    0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
     2136  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2137    0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
     2138  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2139    0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
     2140
     2141  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2142    0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
     2143  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2144    0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
     2145
     2146  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2147    0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
     2148  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2149    0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
     2150  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2151    0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
     2152  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2153    0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
     2154
     2155  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2156    0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
     2157  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2158    0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
     2159  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2160    0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
     2161  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2162    0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
     2163
     2164  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2165    0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
     2166  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2167    0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
     2168
     2169  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2170    0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
     2171  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2172    0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
     2173  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2174    0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
     2175  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
     2176    0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
    11292177
    11302178  /* ARM Instructions.  */
    1131   {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
    1132  
    1133   {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
    1134   {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
    1135   {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
    1136   {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
    1137   {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
    1138   {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
    1139  
    1140   {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
    1141   {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
    1142   {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
    1143   {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
    1144 
    1145   {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
    1146   {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
    1147   {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
    1148   {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
    1149 
    1150   {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
    1151   {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
    1152   {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
    1153 
    1154   {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
    1155   {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
    1156   {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
    1157 
    1158   {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
    1159   {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
    1160   {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
    1161 
    1162   {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
    1163   {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
    1164   {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
    1165 
    1166   {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
    1167   {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
    1168   {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
    1169 
    1170   {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
    1171   {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
    1172   {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
    1173 
    1174   {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
    1175   {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
    1176   {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
    1177 
    1178   {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
    1179   {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
    1180   {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
    1181 
    1182   {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
    1183   {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
    1184   {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
    1185 
    1186   {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
    1187   {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
    1188   {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
    1189 
    1190   {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
    1191   {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
    1192   {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
    1193 
    1194   {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
    1195   {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
    1196   {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
    1197 
    1198   {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
    1199   {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
    1200   {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
    1201 
    1202   {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
    1203   {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
    1204   {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
    1205 
    1206   {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
    1207   {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
    1208   {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
    1209   {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
    1210   {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
    1211   {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
    1212   {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
    1213 
    1214   {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
    1215   {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
    1216   {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
    1217 
    1218   {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
    1219   {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
    1220   {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
    1221 
    1222   {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
    1223   {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
    1224  
    1225   {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
    1226 
    1227   {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
    1228   {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
    1229  
    1230   {ARM_EXT_V1, 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1231   {ARM_EXT_V1, 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1232   {ARM_EXT_V1, 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1233   {ARM_EXT_V1, 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1234   {ARM_EXT_V1, 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1235   {ARM_EXT_V1, 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1236   {ARM_EXT_V1, 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1237   {ARM_EXT_V1, 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1238   {ARM_EXT_V1, 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1239   {ARM_EXT_V1, 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1240   {ARM_EXT_V1, 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1241   {ARM_EXT_V1, 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1242   {ARM_EXT_V1, 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1243   {ARM_EXT_V1, 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1244   {ARM_EXT_V1, 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1245   {ARM_EXT_V1, 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
    1246   {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
    1247   {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
    1248   {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
    1249 
    1250   {ARM_EXT_V1, 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1251   {ARM_EXT_V1, 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1252   {ARM_EXT_V1, 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1253   {ARM_EXT_V1, 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1254   {ARM_EXT_V1, 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1255   {ARM_EXT_V1, 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1256   {ARM_EXT_V1, 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1257   {ARM_EXT_V1, 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1258   {ARM_EXT_V1, 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1259   {ARM_EXT_V1, 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1260   {ARM_EXT_V1, 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1261   {ARM_EXT_V1, 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1262   {ARM_EXT_V1, 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1263   {ARM_EXT_V1, 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1264   {ARM_EXT_V1, 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1265   {ARM_EXT_V1, 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
    1266   {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
    1267   {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
    1268   {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
    1269 
    1270   {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
    1271   {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
     2179  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2180    0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
     2181
     2182  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2183    0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
     2184  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2185    0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
     2186  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2187    0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
     2188  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2189    0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
     2190  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2191    0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
     2192  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2193    0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
     2194
     2195  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2196    0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
     2197  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2198    0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
     2199  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2200    0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
     2201  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2202    0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
     2203
     2204  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2205    0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
     2206  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2207    0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
     2208  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2209    0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
     2210  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2211    0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
     2212
     2213  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2214    0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
     2215  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2216    0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
     2217  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2218    0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
     2219
     2220  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2221    0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
     2222  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2223    0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
     2224  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2225    0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
     2226
     2227  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2228    0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
     2229  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2230    0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
     2231  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2232    0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
     2233
     2234  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2235    0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
     2236  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2237    0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
     2238  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2239    0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
     2240
     2241  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2242    0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
     2243  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2244    0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
     2245  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2246    0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
     2247
     2248  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2249    0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
     2250  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2251    0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
     2252  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2253    0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
     2254
     2255  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2256    0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
     2257  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2258    0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
     2259  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2260    0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
     2261
     2262  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2263    0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
     2264  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2265    0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
     2266  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2267    0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
     2268
     2269  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
     2270    0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
     2271  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
     2272    0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
     2273  {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
     2274    0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
     2275
     2276  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2277    0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
     2278  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2279    0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
     2280  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2281    0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
     2282
     2283  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2284    0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
     2285  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2286    0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
     2287  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2288    0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
     2289  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
     2290    0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
     2291
     2292  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2293    0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
     2294  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2295    0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
     2296  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2297    0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
     2298
     2299  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2300    0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
     2301  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2302    0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
     2303  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2304    0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
     2305
     2306  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2307    0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
     2308  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2309    0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
     2310  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2311    0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
     2312
     2313  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2314    0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
     2315  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2316    0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
     2317  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2318    0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
     2319  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2320    0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
     2321  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2322    0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
     2323  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2324    0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
     2325  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2326    0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
     2327
     2328  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2329    0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
     2330  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2331    0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
     2332  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2333    0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
     2334
     2335  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2336    0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
     2337  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2338    0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
     2339  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2340    0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
     2341
     2342  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2343    0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
     2344  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2345    0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
     2346
     2347  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2348    0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
     2349
     2350  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2351    0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
     2352  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2353    0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
     2354
     2355  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2356    0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2357  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2358    0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2359  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2360    0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2361  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2362    0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2363  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2364    0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2365  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2366    0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2367  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2368    0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2369  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2370    0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2371  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2372    0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2373  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2374    0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2375  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2376    0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2377  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2378    0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2379  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2380    0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2381  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2382    0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2383  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2384    0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2385  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2386    0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
     2387  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2388    0x092d0000, 0x0fff0000, "push%c\t%m"},
     2389  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2390    0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
     2391  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2392    0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
     2393
     2394  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2395    0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2396  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2397    0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2398  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2399    0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2400  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2401    0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2402  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2403    0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2404  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2405    0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2406  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2407    0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2408  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2409    0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2410  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2411    0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2412  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2413    0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2414  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2415    0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2416  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2417    0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2418  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2419    0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2420  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2421    0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2422  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2423    0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2424  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2425    0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
     2426  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2427    0x08bd0000, 0x0fff0000, "pop%c\t%m"},
     2428  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2429    0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
     2430  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2431    0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
     2432
     2433  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2434    0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
     2435  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2436    0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
    12722437
    12732438  /* The rest.  */
    1274   {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
    1275   {0, 0x00000000, 0x00000000, 0}
     2439  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
     2440    0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
     2441  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     2442    0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
     2443  {ARM_FEATURE_CORE_LOW (0),
     2444    0x00000000, 0x00000000, 0}
    12762445};
    12772446
    … …  
    13072476  /* Thumb instructions.  */
    13082477
     2478  /* ARMv8-M Security Extensions instructions.  */
     2479  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
     2480  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
     2481
    13092482  /* ARM V8 instructions.  */
    1310   {ARM_EXT_V8,  0xbf50, 0xffff, "sevl%c"},
    1311   {ARM_EXT_V8,  0xba80, 0xffc0, "hlt\t%0-5x"},
     2483  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
     2484  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
     2485  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
    13122486
    13132487  /* ARM V6K no-argument instructions.  */
    1314   {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
    1315   {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
    1316   {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
    1317   {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
    1318   {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
    1319   {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
     2488  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
     2489  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
     2490  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
     2491  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
     2492  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
     2493  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
    13202494
    13212495  /* ARM V6T2 instructions.  */
    1322   {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
    1323   {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
    1324   {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
     2496  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     2497    0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
     2498  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     2499    0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
     2500  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
    13252501
    13262502  /* ARM V6.  */
    1327   {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
    1328   {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
    1329   {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
    1330   {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
    1331   {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
    1332   {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
    1333   {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
    1334   {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
    1335   {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
    1336   {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
    1337   {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
     2503  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
     2504  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
     2505  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
     2506  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
     2507  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
     2508  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
     2509  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
     2510  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
     2511  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
     2512  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
     2513  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
    13382514
    13392515  /* ARM V5 ISA extends Thumb.  */
    1340   {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
     2516  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
     2517    0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
    13412518  /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
    1342   {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"},      /* note: 4 bit register number.  */
     2519  {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
     2520    0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
    13432521  /* ARM V4T ISA (Thumb v1).  */
    1344   {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
     2522  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2523    0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
    13452524  /* Format 4.  */
    1346   {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
    1347   {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
    1348   {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
    1349   {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
    1350   {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
    1351   {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
    1352   {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
    1353   {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
    1354   {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
    1355   {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
    1356   {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
    1357   {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
    1358   {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
    1359   {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
    1360   {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
    1361   {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
     2525  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
     2526  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
     2527  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
     2528  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
     2529  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
     2530  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
     2531  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
     2532  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
     2533  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
     2534  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
     2535  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
     2536  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
     2537  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
     2538  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
     2539  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
     2540  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
    13622541  /* format 13 */
    1363   {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
    1364   {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
     2542  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
     2543  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
    13652544  /* format 5 */
    1366   {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
    1367   {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
    1368   {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
    1369   {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
     2545  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
     2546  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
     2547  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
     2548  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
    13702549  /* format 14 */
    1371   {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
    1372   {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
     2550  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
     2551  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
    13732552  /* format 2 */
    1374   {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
    1375   {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
    1376   {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
    1377   {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
     2553  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2554    0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
     2555  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2556    0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
     2557  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2558    0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
     2559  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2560    0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
    13782561  /* format 8 */
    1379   {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
    1380   {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
    1381   {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
     2562  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2563    0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
     2564  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2565    0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
     2566  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2567    0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
    13822568  /* format 7 */
    1383   {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
    1384   {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
     2569  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2570    0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
     2571  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2572    0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
    13852573  /* format 1 */
    1386   {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
    1387   {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
    1388   {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
    1389   {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
     2574  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
     2575  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2576    0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
     2577  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
     2578  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
    13902579  /* format 3 */
    1391   {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
    1392   {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
    1393   {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
    1394   {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
     2580  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
     2581  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
     2582  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
     2583  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
    13952584  /* format 6 */
    1396   {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
     2585  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
     2586  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2587    0x4800, 0xF800,
     2588    "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
    13972589  /* format 9 */
    1398   {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
    1399   {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
    1400   {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
    1401   {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
     2590  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2591    0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
     2592  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2593    0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
     2594  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2595    0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
     2596  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2597    0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
    14022598  /* format 10 */
    1403   {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
    1404   {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
     2599  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2600    0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
     2601  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2602    0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
    14052603  /* format 11 */
    1406   {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
    1407   {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
     2604  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2605    0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
     2606  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2607    0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
    14082608  /* format 12 */
    1409   {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
    1410   {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
     2609  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2610    0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
     2611  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     2612    0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
    14112613  /* format 15 */
    1412   {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
    1413   {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
     2614  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
     2615  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
    14142616  /* format 17 */
    1415   {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
     2617  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
    14162618  /* format 16 */
    1417   {ARM_EXT_V4T, 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
    1418   {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
    1419   {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
     2619  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
     2620  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
     2621  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
    14202622  /* format 18 */
    1421   {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
     2623  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
    14222624
    14232625  /* The E800 .. FFFF range is unconditionally redirected to the
    … …  
    14252627     are processed via that table.  Thus, we can never encounter a
    14262628     bare "second half of BL/BLX(1)" instruction here.  */
    1427   {ARM_EXT_V1,  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
    1428   {0, 0, 0, 0}
     2629  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
     2630  {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
    14292631};
    14302632
    … …  
    14622664
    14632665       %<bitfield>d     print bitfield in decimal
     2666       %<bitfield>D     print bitfield plus one in decimal
    14642667       %<bitfield>W     print bitfield*4 in decimal
    14652668       %<bitfield>r     print bitfield as an ARM register
    … …  
    14822685static const struct opcode32 thumb32_opcodes[] =
    14832686{
     2687  /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
     2688  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
     2689  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
     2690    0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
     2691  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
     2692    0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
     2693  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
     2694    0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
     2695  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
     2696    0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
     2697
     2698  /* ARM V8.2 RAS extension instructions.  */
     2699  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
     2700    0xf3af8010, 0xffffffff, "esb"},
     2701
    14842702  /* V8 instructions.  */
    1485   {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
    1486   {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
    1487   {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
    1488   {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
    1489   {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
    1490   {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
    1491   {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
    1492   {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
    1493   {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
    1494   {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
    1495   {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
    1496   {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
    1497   {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
    1498   {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
    1499   {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
    1500   {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
     2703  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2704    0xf3af8005, 0xffffffff, "sevl%c.w"},
     2705  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2706    0xf78f8000, 0xfffffffc, "dcps%0-1d"},
     2707  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2708    0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
     2709  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2710    0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
     2711  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2712    0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
     2713  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2714    0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
     2715  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2716    0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
     2717  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2718    0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
     2719  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2720    0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
     2721  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2722    0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
     2723  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2724    0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
     2725  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2726    0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
     2727  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2728    0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
     2729  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2730    0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
     2731  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2732    0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
     2733  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     2734    0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
    15012735
    15022736  /* CRC32 instructions.  */
    1503   {CRC_EXT_ARMV8, 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
    1504   {CRC_EXT_ARMV8, 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
    1505   {CRC_EXT_ARMV8, 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
    1506   {CRC_EXT_ARMV8, 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
    1507   {CRC_EXT_ARMV8, 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
    1508   {CRC_EXT_ARMV8, 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
     2737  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     2738    0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
     2739  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     2740    0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
     2741  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     2742    0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
     2743  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     2744    0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
     2745  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     2746    0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
     2747  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
     2748    0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
    15092749
    15102750  /* V7 instructions.  */
    1511   {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
    1512   {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
    1513   {ARM_EXT_V8, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
    1514   {ARM_EXT_V8, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
    1515   {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
    1516   {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
    1517   {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
    1518   {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
    1519   {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
     2751  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
     2752  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
     2753  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
     2754  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
     2755  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
     2756  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
     2757  {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
     2758  {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
     2759    0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
     2760  {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
     2761    0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
    15202762
    15212763  /* Virtualization Extension instructions.  */
    1522   {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
     2764  {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
    15232765  /* We skip ERET as that is SUBS pc, lr, #0.  */
    15242766
    15252767  /* MP Extension instructions.  */
    1526   {ARM_EXT_MP,   0xf830f000, 0xff70f000, "pldw%c\t%a"},
     2768  {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
    15272769
    15282770  /* Security extension instructions.  */
    1529   {ARM_EXT_SEC,  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
     2771  {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
    15302772
    15312773  /* Instructions defined in the basic V6T2 set.  */
    1532   {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
    1533   {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
    1534   {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
    1535   {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
    1536   {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
    1537   {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
    1538   {ARM_EXT_V6T2, 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
    1539 
    1540   {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
    1541   {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
    1542   {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
    1543   {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
    1544   {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
    1545   {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
    1546   {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
    1547   {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
    1548   {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
    1549   {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
    1550   {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
    1551   {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
    1552   {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
    1553   {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
    1554   {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
    1555   {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
    1556   {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
    1557   {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
    1558   {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
    1559   {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
    1560   {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
    1561   {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
    1562   {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
    1563   {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
    1564   {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
    1565   {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
    1566   {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
    1567   {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
    1568   {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
    1569   {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
    1570   {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
    1571   {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
    1572   {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
    1573   {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
    1574   {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
    1575   {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
    1576   {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
    1577   {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
    1578   {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
    1579   {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
    1580   {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
    1581   {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
    1582   {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
    1583   {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
    1584   {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
    1585   {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
    1586   {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
    1587   {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
    1588   {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
    1589   {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
    1590   {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
    1591   {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
    1592   {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
    1593   {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
    1594   {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
    1595   {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
    1596   {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
    1597   {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
    1598   {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
    1599   {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
    1600   {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
    1601   {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
    1602   {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
    1603   {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
    1604   {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
    1605   {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
    1606   {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
    1607   {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
    1608   {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
    1609   {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
    1610   {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
    1611   {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
    1612   {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
    1613   {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
    1614   {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
    1615   {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
    1616   {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
    1617   {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
    1618   {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
    1619   {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
    1620   {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
    1621   {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
    1622   {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
    1623   {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
    1624   {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
    1625   {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
    1626   {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
    1627   {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
    1628   {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
    1629   {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
    1630   {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
    1631   {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
    1632   {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
    1633   {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
    1634   {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
    1635   {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
    1636   {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
    1637   {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
    1638   {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
    1639   {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
    1640   {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
    1641   {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
    1642   {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
    1643   {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
    1644   {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
    1645   {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
    1646   {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
    1647   {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
    1648   {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
    1649   {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
    1650   {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
    1651   {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
    1652   {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
    1653   {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
    1654   {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
    1655   {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
    1656   {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
    1657   {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
    1658   {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
    1659   {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
    1660   {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
    1661   {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
    1662   {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
    1663   {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
    1664   {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
    1665   {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
    1666   {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
    1667   {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
    1668   {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
    1669   {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
    1670   {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
    1671   {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
    1672   {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
    1673   {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
    1674   {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
    1675   {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
    1676   {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
    1677   {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
    1678   {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
    1679   {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
    1680   {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
    1681   {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
    1682   {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
    1683   {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
    1684   {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
    1685   {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
    1686   {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
    1687   {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
    1688   {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
    1689   {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
    1690   {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
    1691   {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
    1692   {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
    1693   {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
    1694   {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
    1695   {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
    1696   {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
    1697   {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
    1698   {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
    1699   {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
    1700   {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
    1701   {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
    1702   {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
    1703   {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
    1704   {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
    1705   {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
    1706   {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
    1707   {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
    1708   {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
    1709   {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
    1710   {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
     2774  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
     2775  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
     2776  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
     2777  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
     2778  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
     2779  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2780    0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
     2781  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
     2782
     2783  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     2784    0xf3bf8f2f, 0xffffffff, "clrex%c"},
     2785  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2786    0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
     2787  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2788    0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
     2789  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2790    0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
     2791  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2792    0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
     2793  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2794    0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
     2795  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2796    0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
     2797  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2798    0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
     2799  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2800    0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
     2801  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2802    0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
     2803  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2804    0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
     2805  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2806    0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
     2807  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2808    0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
     2809  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2810    0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
     2811  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     2812    0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
     2813  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     2814    0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
     2815  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2816    0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
     2817  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2818    0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
     2819  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2820    0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
     2821  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2822    0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
     2823  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2824    0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
     2825  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2826    0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
     2827  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2828    0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
     2829  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2830    0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
     2831  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     2832    0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
     2833  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2834    0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
     2835  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2836    0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
     2837  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2838    0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
     2839  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2840    0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
     2841  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2842    0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
     2843  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2844    0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
     2845  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2846    0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
     2847  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2848    0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
     2849  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2850    0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
     2851  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2852    0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
     2853  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2854    0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
     2855  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2856    0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
     2857  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2858    0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
     2859  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2860    0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
     2861  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2862    0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
     2863  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2864    0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
     2865  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2866    0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
     2867  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2868    0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
     2869  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2870    0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
     2871  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2872    0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
     2873  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2874    0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
     2875  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2876    0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
     2877  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2878    0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
     2879  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2880    0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
     2881  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2882    0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
     2883  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2884    0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
     2885  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2886    0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
     2887  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2888    0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
     2889  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2890    0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
     2891  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2892    0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
     2893  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2894    0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
     2895  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2896    0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
     2897  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2898    0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
     2899  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2900    0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
     2901  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2902    0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
     2903  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2904    0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
     2905  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2906    0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
     2907  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2908    0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
     2909  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2910    0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
     2911  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2912    0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
     2913  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2914    0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
     2915  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2916    0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
     2917  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2918    0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
     2919  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2920    0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
     2921  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2922    0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
     2923  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2924    0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
     2925  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2926    0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
     2927  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2928    0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
     2929  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2930    0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
     2931  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2932    0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
     2933  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2934    0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
     2935  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2936    0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
     2937  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2938    0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
     2939  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     2940    0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
     2941  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2942    0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
     2943  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2944    0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
     2945  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2946    0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
     2947  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2948    0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
     2949  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2950    0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
     2951  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2952    0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
     2953  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2954    0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
     2955  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2956    0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
     2957  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2958    0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
     2959  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2960    0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
     2961  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2962    0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
     2963  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2964    0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
     2965  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2966    0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
     2967  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2968    0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
     2969  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2970    0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
     2971  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2972    0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
     2973  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2974    0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
     2975  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2976    0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
     2977  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2978    0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
     2979  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2980    0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
     2981  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2982    0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
     2983  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2984    0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
     2985  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2986    0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
     2987  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2988    0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
     2989  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2990    0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
     2991  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2992    0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
     2993  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2994    0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
     2995  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2996    0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
     2997  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     2998    0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
     2999  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3000    0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
     3001  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3002    0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
     3003  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3004    0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
     3005  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3006    0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
     3007  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     3008    0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
     3009  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3010    0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
     3011  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3012    0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
     3013  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3014    0xf810f000, 0xff70f000, "pld%c\t%a"},
     3015  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3016    0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
     3017  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3018    0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
     3019  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3020    0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
     3021  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3022    0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
     3023  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3024    0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
     3025  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3026    0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
     3027  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3028    0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
     3029  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3030    0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
     3031  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3032    0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
     3033  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3034    0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
     3035  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3036    0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
     3037  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3038    0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
     3039  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3040    0xfb100000, 0xfff000c0,
     3041    "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
     3042  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3043    0xfbc00080, 0xfff000c0,
     3044    "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
     3045  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3046    0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
     3047  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3048    0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
     3049  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3050    0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
     3051  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3052    0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
     3053  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3054    0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
     3055  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     3056    0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
     3057  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3058    0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
     3059  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     3060    0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
     3061  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3062    0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
     3063  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3064    0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
     3065  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3066    0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
     3067  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3068    0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
     3069  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3070    0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
     3071  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3072    0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
     3073  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3074    0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
     3075  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3076    0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
     3077  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3078    0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
     3079  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3080    0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
     3081  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
     3082    0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
     3083  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3084    0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
     3085  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3086    0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
     3087  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3088    0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
     3089  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3090    0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
     3091  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3092    0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
     3093  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3094    0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
     3095  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3096    0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
     3097  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3098    0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
     3099  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3100    0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
     3101  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3102    0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
     3103  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3104    0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
     3105  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3106    0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
     3107  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3108    0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
     3109  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3110    0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
     3111  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3112    0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
     3113  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3114    0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
     3115  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3116    0xe9400000, 0xff500000,
     3117    "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
     3118  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3119    0xe9500000, 0xff500000,
     3120    "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
     3121  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3122    0xe8600000, 0xff700000,
     3123    "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
     3124  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3125    0xe8700000, 0xff700000,
     3126    "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
     3127  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3128    0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
     3129  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3130    0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
    17113131
    17123132  /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
    1713   {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
    1714   {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
    1715   {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
    1716   {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
     3133  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3134    0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
     3135  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3136    0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
     3137  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3138    0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
     3139  {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
     3140    0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
    17173141
    17183142  /* These have been 32-bit since the invention of Thumb.  */
    1719   {ARM_EXT_V4T,  0xf000c000, 0xf800d001, "blx%c\t%B%x"},
    1720   {ARM_EXT_V4T,  0xf000d000, 0xf800d000, "bl%c\t%B%x"},
     3143  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     3144     0xf000c000, 0xf800d001, "blx%c\t%B%x"},
     3145  {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
     3146     0xf000d000, 0xf800d000, "bl%c\t%B%x"},
    17213147
    17223148  /* Fallback.  */
    1723   {ARM_EXT_V1,   0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
    1724   {0, 0, 0, 0}
     3149  {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
     3150      0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
     3151  {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
    17253152};
    17263153
    … …  
    18413268  unsigned long value = 0;
    18423269  int width = 0;
    1843  
    1844   do 
     3270
     3271  do
    18453272    {
    18463273      int start, end;
    … …  
    19313358  unsigned long mask;
    19323359  unsigned long value = 0;
     3360  int cond;
     3361  int cp_num;
    19333362  struct arm_private_data *private_data = info->private_data;
    1934   unsigned long allowed_arches = private_data->features.coproc;
    1935   int cond;
     3363  arm_feature_set allowed_arches = ARM_ARCH_NONE;
     3364
     3365  ARM_FEATURE_COPY (allowed_arches, private_data->features);
    19363366
    19373367  for (insn = coprocessor_opcodes; insn->assembler; insn++)
    … …  
    19423372      const char *c;
    19433373
    1944       if (insn->arch == 0)
     3374      if (ARM_FEATURE_ZERO (insn->arch))
    19453375        switch (insn->value)
    19463376          {
    … …  
    19513381              do
    19523382                insn++;
    1953               while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END);
     3383              while ((! ARM_FEATURE_ZERO (insn->arch))
     3384                     && insn->value != SENTINEL_IWMMXT_END);
    19543385            continue;
    19553386
    … …  
    19583389
    19593390          case SENTINEL_GENERIC_START:
    1960             allowed_arches = private_data->features.core;
     3391            ARM_FEATURE_COPY (allowed_arches, private_data->features);
    19613392            continue;
    19623393
    … …  
    19673398      mask = insn->mask;
    19683399      value = insn->value;
     3400      cp_num = (given >> 8) & 0xf;
     3401
    19693402      if (thumb)
    19703403        {
    … …  
    19953428            }
    19963429        }
    1997      
     3430
    19983431      if ((given & mask) != value)
    19993432        continue;
    20003433
    2001       if ((insn->arch & allowed_arches) == 0)
     3434      if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
    20023435        continue;
     3436
     3437      if (insn->value == 0xfe000010     /* mcr2  */
     3438          || insn->value == 0xfe100010  /* mrc2  */
     3439          || insn->value == 0xfc100000  /* ldc2  */
     3440          || insn->value == 0xfc000000) /* stc2  */
     3441        {
     3442          if (cp_num == 9 || cp_num == 10 || cp_num == 11)
     3443            is_unpredictable = TRUE;
     3444        }
     3445      else if (insn->value == 0x0e000000     /* cdp  */
     3446               || insn->value == 0xfe000000  /* cdp2  */
     3447               || insn->value == 0x0e000010  /* mcr  */
     3448               || insn->value == 0x0e100010  /* mrc  */
     3449               || insn->value == 0x0c100000  /* ldc  */
     3450               || insn->value == 0x0c000000) /* stc  */
     3451        {
     3452          /* Floating-point instructions.  */
     3453          if (cp_num == 9 || cp_num == 10 || cp_num == 11)
     3454            continue;
     3455        }
    20033456
    20043457      for (c = insn->assembler; *c; c++)
    … …  
    20153468                  {
    20163469                    int rn = (given >> 16) & 0xf;
    2017                     bfd_vma offset = given & 0xff;
     3470                    bfd_vma offset = given & 0xff;
    20183471
    20193472                    func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
    … …  
    20223475                      {
    20233476                        /* Not unindexed.  The offset is scaled.  */
    2024                         offset = offset * 4;
     3477                        if (cp_num == 9)
     3478                          /* vldr.16/vstr.16 will shift the address
     3479                             left by 1 bit only.  */
     3480                          offset = offset * 2;
     3481                        else
     3482                          offset = offset * 4;
     3483
    20253484                        if (NEGATIVE_BIT_SET)
    20263485                          offset = - offset;
    … …  
    20643523                        /* For unaligned PCs, apply off-by-alignment
    20653524                           correction.  */
    2066                         info->print_address_func (offset + pc 
     3525                        info->print_address_func (offset + pc
    20673526                                                  + info->bytes_per_chunk * 2
    20683527                                                  - (pc & 3),
    … …  
    20923551                  /* Fall through.  */
    20933552                case 'c':
     3553                  if (cond != COND_UNCOND && cp_num == 9)
     3554                    is_unpredictable = TRUE;
     3555
    20943556                  func (stream, "%s", arm_conditional[cond]);
    20953557                  break;
    … …  
    21073569                    /* Is ``imm'' a negative number?  */
    21083570                    if (imm & 0x40)
    2109                       imm |= (-1 << 7);
     3571                      imm -= 0x80;
    21103572
    21113573                    func (stream, "%d", imm);
    … …  
    22223684                        value_in_comment = value;
    22233685                        break;
     3686                      case 'E':
     3687                        {
     3688                          /* Converts immediate 8 bit back to float value.  */
     3689                          unsigned floatVal = (value & 0x80) << 24
     3690                            | (value & 0x3F) << 19
     3691                            | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
     3692
     3693                          /* Quarter float have a maximum value of 31.0.
     3694                             Get floating point value multiplied by 1e7.
     3695                             The maximum value stays in limit of a 32-bit int.  */
     3696                          unsigned decVal =
     3697                            (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
     3698                            (16 + (value & 0xF));
     3699
     3700                          if (!(decVal % 1000000))
     3701                            func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
     3702                                  floatVal, value & 0x80 ? '-' : ' ',
     3703                                  decVal / 10000000,
     3704                                  decVal % 10000000 / 1000000);
     3705                          else if (!(decVal % 10000))
     3706                            func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
     3707                                  floatVal, value & 0x80 ? '-' : ' ',
     3708                                  decVal / 10000000,
     3709                                  decVal % 10000000 / 10000);
     3710                          else
     3711                            func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
     3712                                  floatVal, value & 0x80 ? '-' : ' ',
     3713                                  decVal / 10000000, decVal % 10000000);
     3714                          break;
     3715                        }
    22243716                      case 'k':
    22253717                        {
    … …  
    26214113        return FALSE;
    26224114    }
    2623  
     4115
    26244116  for (insn = neon_opcodes; insn->assembler; insn++)
    26254117    {
    … …  
    26524144                    case 'A':
    26534145                      {
    2654                         static const unsigned char enc[16] = 
     4146                        static const unsigned char enc[16] =
    26554147                        {
    26564148                          0x4, 0x14, /* st4 0,1 */
    … …  
    26744166                        int stride = (enc[type] >> 4) + 1;
    26754167                        int ix;
    2676                        
     4168
    26774169                        func (stream, "{");
    26784170                        if (stride > 1)
    … …  
    26934185                      }
    26944186                      break;
    2695                      
     4187
    26964188                    case 'B':
    26974189                      {
    … …  
    27094201                        if (length > 1 && size > 0)
    27104202                          stride = (idx_align & (1 << size)) ? 2 : 1;
    2711                        
     4203
    27124204                        switch (length)
    27134205                          {
    … …  
    27264218                              }
    27274219                            break;
    2728                          
     4220
    27294221                          case 2:
    27304222                            if (size == 2 && (idx_align & 2) != 0)
    … …  
    27324224                            align = (idx_align & 1) ? 16 << size : 0;
    27334225                            break;
    2734                          
     4226
    27354227                          case 3:
    27364228                            if ((size == 2 && (idx_align & 3) != 0)
    … …  
    27384230                              return FALSE;
    27394231                            break;
    2740                          
     4232
    27414233                          case 4:
    27424234                            if (size == 2)
    … …  
    27494241                              align = (idx_align & 1) ? 32 << size : 0;
    27504242                            break;
    2751                          
     4243
    27524244                          default:
    27534245                            abort ();
    27544246                          }
    2755                                
     4247
    27564248                        func (stream, "{");
    27574249                        for (i = 0; i < length; i++)
    … …  
    27684260                      }
    27694261                      break;
    2770                      
     4262
    27714263                    case 'C':
    27724264                      {
    … …  
    27804272                        int stride = ((given >> 5) & 0x1);
    27814273                        int ix;
    2782                        
     4274
    27834275                        if (stride && (n == 1))
    27844276                          n++;
    27854277                        else
    27864278                          stride++;
    2787                        
     4279
    27884280                        func (stream, "{");
    27894281                        if (stride > 1)
    … …  
    28124304                      }
    28134305                      break;
    2814                      
     4306
    28154307                    case 'D':
    28164308                      {
    … …  
    28194311                        int reg = raw_reg & ((4 << size) - 1);
    28204312                        int ix = raw_reg >> size >> 2;
    2821                        
     4313
    28224314                        func (stream, "d%d[%d]", reg, ix);
    28234315                      }
    28244316                      break;
    2825                      
     4317
    28264318                    case 'E':
    28274319                      /* Neon encoded constant for mov, mvn, vorr, vbic.  */
    … …  
    28344326                        int size = 0;
    28354327                        int isfloat = 0;
    2836                        
     4328
    28374329                        bits |= ((given >> 24) & 1) << 7;
    28384330                        bits |= ((given >> 16) & 7) << 4;
    28394331                        bits |= ((given >> 0) & 15) << 0;
    2840                        
     4332
    28414333                        if (cmode < 8)
    28424334                          {
    … …  
    28654357                                int ix;
    28664358                                unsigned long mask;
    2867                                
     4359
    28684360                                value = 0;
    28694361                                hival = 0;
    … …  
    28894381                            /* Floating point encoding.  */
    28904382                            int tmp;
    2891                            
     4383
    28924384                            value = (unsigned long)  (bits & 0x7f) << 19;
    28934385                            value |= (unsigned long) (bits & 0x80) << 24;
    … …  
    29094401                            func (stream, "#%ld\t; 0x%.2lx", value, value);
    29104402                            break;
    2911                          
     4403
    29124404                          case 16:
    29134405                            func (stream, "#%ld\t; 0x%.4lx", value, value);
    … …  
    29194411                                unsigned char valbytes[4];
    29204412                                double fvalue;
    2921                                
     4413
    29224414                                /* Do this a byte at a time so we don't have to
    29234415                                   worry about the host's endianness.  */
    … …  
    29264418                                valbytes[2] = (value >> 16) & 0xff;
    29274419                                valbytes[3] = (value >> 24) & 0xff;
    2928                                
    2929                                 floatformat_to_double 
     4420
     4421                                floatformat_to_double
    29304422                                  (& floatformat_ieee_single_little, valbytes,
    29314423                                  & fvalue);
    2932                                                                
     4424
    29334425                                func (stream, "#%.7g\t; 0x%.8lx", fvalue,
    29344426                                      value);
    … …  
    29364428                            else
    29374429                              func (stream, "#%ld\t; 0x%.8lx",
    2938                                     (long) (((value & 0x80000000L) != 0) 
     4430                                    (long) (((value & 0x80000000L) != 0)
    29394431                                            ? value | ~0xffffffffL : value),
    29404432                                    value);
    … …  
    29444436                            func (stream, "#0x%.8lx%.8lx", hival, value);
    29454437                            break;
    2946                          
     4438
    29474439                          default:
    29484440                            abort ();
    … …  
    29504442                      }
    29514443                      break;
    2952                      
     4444
    29534445                    case 'F':
    29544446                      {
    29554447                        int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
    29564448                        int num = (given >> 8) & 0x3;
    2957                        
     4449
    29584450                        if (!num)
    29594451                          func (stream, "{d%d}", regno);
    … …  
    29734465
    29744466                        c = arm_decode_bitfield (c, given, &value, &width);
    2975                        
     4467
    29764468                        switch (*c)
    29774469                          {
    … …  
    29864478                            func (stream, "%ld", (1ul << width) - value);
    29874479                            break;
    2988                            
     4480
    29894481                          case 'S':
    29904482                          case 'T':
    … …  
    30264518                              func (stream, "q%ld", value >> 1);
    30274519                            break;
    3028                            
     4520
    30294521                          case '`':
    30304522                            c++;
    … …  
    30694561/* Return the name of a v7A special register.  */
    30704562
    3071 static const char * 
     4563static const char *
    30724564banked_regname (unsigned reg)
    30734565{
    … …  
    30754567    {
    30764568      case 15: return "CPSR";
    3077       case 32: return "R8_usr"; 
     4569      case 32: return "R8_usr";
    30784570      case 33: return "R9_usr";
    30794571      case 34: return "R10_usr";
    … …  
    30824574      case 37: return "SP_usr";
    30834575      case 38: return "LR_usr";
    3084       case 40: return "R8_fiq"; 
     4576      case 40: return "R8_fiq";
    30854577      case 41: return "R9_fiq";
    30864578      case 42: return "R10_fiq";
    … …  
    31554647      if ((given & insn->mask) != insn->value)
    31564648        continue;
    3157    
    3158       if ((insn->arch & private_data->features.core) == 0)
     4649
     4650      if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
    31594651        continue;
    31604652
    … …  
    33704862                      if ((given & 0x0000f000) == 0x0000f000)
    33714863                        {
     4864                          arm_feature_set arm_ext_v6 =
     4865                            ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
     4866
    33724867                          /* The p-variants of tst/cmp/cmn/teq are the pre-V6
    33734868                             mechanism for setting PSR flag bits.  They are
    33744869                             obsolete in V6 onwards.  */
    3375                           if ((private_data->features.core & ARM_EXT_V6) == 0)
     4870                          if (! ARM_CPU_HAS_FEATURE (private_data->features, \
     4871                                                     arm_ext_v6))
    33764872                            func (stream, "p");
     4873                          else
     4874                            is_unpredictable = TRUE;
    33774875                        }
    33784876                      break;
    … …  
    34594957                      else
    34604958                        {
    3461                           func (stream, "%cPSR_", 
     4959                          func (stream, "%cPSR_",
    34624960                                (given & 0x00400000) ? 'S' : 'C');
    34634961                          if (given & 0x80000)
    … …  
    34734971
    34744972                    case 'U':
    3475                       if ((given & 0xf0) == 0x60) 
     4973                      if ((given & 0xf0) == 0x60)
    34764974                        {
    34774975                          switch (given & 0xf)
    … …  
    34824980                              break;
    34834981                            }
    3484                         } 
    3485                       else 
     4982                        }
     4983                      else
    34864984                        {
    34874985                          const char * opt = data_barrier_option (given & 0xf);
    … …  
    35004998
    35014999                        c = arm_decode_bitfield (c, given, &value, &width);
    3502                        
     5000
    35035001                        switch (*c)
    35045002                          {
    … …  
    39455443    case 19: return "FAULTMASK";
    39465444    case 20: return "CONTROL";
     5445    case 0x88: return "MSP_NS";
     5446    case 0x89: return "PSP_NS";
    39475447    default: return "<unknown>";
    39485448    }
    … …  
    40375537                }
    40385538                break;
    4039                  
     5539
    40405540              case 'J':
    40415541                {
    … …  
    43675867
    43685868              case 'U':
    4369                 if ((given & 0xf0) == 0x60) 
     5869                if ((given & 0xf0) == 0x60)
    43705870                  {
    43715871                    switch (given & 0xf)
    … …  
    43775877                      }
    43785878                  }
    4379                 else 
     5879                else
    43805880                  {
    43815881                    const char * opt = data_barrier_option (given & 0xf);
    … …  
    44085908                    sysm |= (given & 0x00100000) >> 14;
    44095909                    name = banked_regname (sysm);
    4410                    
     5910
    44115911                    if (name != NULL)
    44125912                      func (stream, "%s", name);
    … …  
    44475947
    44485948                  c = arm_decode_bitfield (c, given, &val, &width);
    4449                        
     5949
    44505950                  switch (*c)
    44515951                    {
    … …  
    44535953                      func (stream, "%lu", val);
    44545954                      value_in_comment = val;
     5955                      break;
     5956
     5957                    case 'D':
     5958                      func (stream, "%lu", val + 1);
     5959                      value_in_comment = val + 1;
    44555960                      break;
    44565961
    … …  
    44815986                        func (stream, "%c", *c);
    44825987                      break;
    4483                      
     5988
    44845989                    case '`':
    44855990                      c++;
    … …  
    44925997                      c += 1 << width;
    44935998                      break;
    4494                      
     5999
    44956000                    case 'x':
    44966001                      func (stream, "0x%lx", val & 0xffffffffUL);
    … …  
    45606065
    45616066/* Disallow mapping symbols ($a, $b, $d, $t etc) from
    4562    being displayed in symbol relative addresses.  */
     6067   being displayed in symbol relative addresses.
     6068
     6069   Also disallow private symbol, with __tagsym$$ prefix,
     6070   from ARM RVCT toolchain being displayed.  */
    45636071
    45646072bfd_boolean
    … …  
    45676075{
    45686076  const char * name;
    4569  
     6077
    45706078  if (sym == NULL)
    45716079    return FALSE;
    … …  
    45736081  name = bfd_asymbol_name (sym);
    45746082
    4575   return (name && *name != '$');
     6083  return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
    45766084}
    45776085
    … …  
    46306138      /* Skip forward past seperators.  */
    46316139      while (ISSPACE (*options) || (*options == ','))
    4632         ++ options;     
     6140        ++ options;
    46336141    }
    46346142}
     6143
     6144static bfd_boolean
     6145mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
     6146                         enum map_type *map_symbol);
    46356147
    46366148/* Search back through the insn stream to determine if this instruction is
    … …  
    46966208      if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
    46976209        {
    4698           /* This could be an IT instruction.  */
    4699           seen_it = insn;
    4700           it_count = count >> 1;
     6210          enum map_type type = MAP_ARM;
     6211          bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
     6212
     6213          if (!found || (found && type == MAP_THUMB))
     6214            {
     6215              /* This could be an IT instruction.  */
     6216              seen_it = insn;
     6217              it_count = count >> 1;
     6218            }
    47016219        }
    47026220      if ((insn & 0xf800) >= 0xe800)
    … …  
    47726290  if (type == STT_FUNC || type == STT_GNU_IFUNC)
    47736291    {
    4774       if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
     6292      if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
     6293          == ST_BRANCH_TO_THUMB)
    47756294        *map_type = MAP_THUMB;
    47766295      else
    … …  
    47826301}
    47836302
     6303/* Search the mapping symbol state for instruction at pc.  This is only
     6304   applicable for elf target.
     6305
     6306   There is an assumption Here, info->private_data contains the correct AND
     6307   up-to-date information about current scan process.  The information will be
     6308   used to speed this search process.
     6309
     6310   Return TRUE if the mapping state can be determined, and map_symbol
     6311   will be updated accordingly.  Otherwise, return FALSE.  */
     6312
     6313static bfd_boolean
     6314mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
     6315                         enum map_type *map_symbol)
     6316{
     6317  bfd_vma addr;
     6318  int n, start = 0;
     6319  bfd_boolean found = FALSE;
     6320  enum map_type type = MAP_ARM;
     6321  struct arm_private_data *private_data;
     6322
     6323  if (info->private_data == NULL || info->symtab_size == 0
     6324      || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
     6325    return FALSE;
     6326
     6327  private_data = info->private_data;
     6328  if (pc == 0)
     6329    start = 0;
     6330  else
     6331    start = private_data->last_mapping_sym;
     6332
     6333  start = (start == -1)? 0 : start;
     6334  addr = bfd_asymbol_value (info->symtab[start]);
     6335
     6336  if (pc >= addr)
     6337    {
     6338      if (get_map_sym_type (info, start, &type))
     6339      found = TRUE;
     6340    }
     6341  else
     6342    {
     6343      for (n = start - 1; n >= 0; n--)
     6344        {
     6345          if (get_map_sym_type (info, n, &type))
     6346            {
     6347              found = TRUE;
     6348              break;
     6349            }
     6350        }
     6351    }
     6352
     6353  /* No mapping symbols were found.  A leading $d may be
     6354     omitted for sections which start with data; but for
     6355     compatibility with legacy and stripped binaries, only
     6356     assume the leading $d if there is at least one mapping
     6357     symbol in the file.  */
     6358  if (!found && private_data->has_mapping_symbols == 1)
     6359    {
     6360      type = MAP_DATA;
     6361      found = TRUE;
     6362    }
     6363
     6364  *map_symbol = type;
     6365  return found;
     6366}
     6367
    47846368/* Given a bfd_mach_arm_XXX value, this function fills in the fields
    47856369   of the supplied arm_feature_set structure with bitmasks indicating
    … …  
    47936377                     arm_feature_set * features)
    47946378{
    4795 #undef  ARM_FEATURE
    4796 #define ARM_FEATURE(ARCH,CEXT) \
    4797   features->core = (ARCH); \
    4798   features->coproc = (CEXT) | FPU_FPA; \
    4799   return
     6379#undef ARM_SET_FEATURES
     6380#define ARM_SET_FEATURES(FSET) \
     6381  {                                                     \
     6382    const arm_feature_set fset = FSET;                  \
     6383    arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
     6384    ARM_MERGE_FEATURE_SETS (*features, tmp, fset);      \
     6385  }
    48006386
    48016387  switch (mach)
    48026388    {
    4803     case bfd_mach_arm_2:       ARM_ARCH_V2;
    4804     case bfd_mach_arm_2a:      ARM_ARCH_V2S;
    4805     case bfd_mach_arm_3:       ARM_ARCH_V3;
    4806     case bfd_mach_arm_3M:      ARM_ARCH_V3M;
    4807     case bfd_mach_arm_4:       ARM_ARCH_V4;
    4808     case bfd_mach_arm_4T:      ARM_ARCH_V4T;
    4809     case bfd_mach_arm_5:       ARM_ARCH_V5;
    4810     case bfd_mach_arm_5T:      ARM_ARCH_V5T;
    4811     case bfd_mach_arm_5TE:     ARM_ARCH_V5TE;
    4812     case bfd_mach_arm_XScale:  ARM_ARCH_XSCALE;
    4813     case bfd_mach_arm_ep9312:  ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK);
    4814     case bfd_mach_arm_iWMMXt:  ARM_ARCH_IWMMXT;
    4815     case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
     6389    case bfd_mach_arm_2:       ARM_SET_FEATURES (ARM_ARCH_V2); break;
     6390    case bfd_mach_arm_2a:      ARM_SET_FEATURES (ARM_ARCH_V2S); break;
     6391    case bfd_mach_arm_3:       ARM_SET_FEATURES (ARM_ARCH_V3); break;
     6392    case bfd_mach_arm_3M:      ARM_SET_FEATURES (ARM_ARCH_V3M); break;
     6393    case bfd_mach_arm_4:       ARM_SET_FEATURES (ARM_ARCH_V4); break;
     6394    case bfd_mach_arm_4T:      ARM_SET_FEATURES (ARM_ARCH_V4T); break;
     6395    case bfd_mach_arm_5:       ARM_SET_FEATURES (ARM_ARCH_V5); break;
     6396    case bfd_mach_arm_5T:      ARM_SET_FEATURES (ARM_ARCH_V5T); break;
     6397    case bfd_mach_arm_5TE:     ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
     6398    case bfd_mach_arm_XScale:  ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
     6399    case bfd_mach_arm_ep9312:
     6400      ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
     6401                                         ARM_CEXT_MAVERICK | FPU_MAVERICK));
     6402       break;
     6403    case bfd_mach_arm_iWMMXt:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
     6404    case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
    48166405      /* If the machine type is unknown allow all
    48176406         architecture types and all extensions.  */
    4818     case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL);
     6407    case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
    48196408    default:
    48206409      abort ();
    48216410    }
     6411
     6412#undef ARM_SET_FEATURES
    48226413}
    48236414
    … …  
    48566447        /* If the user did not use the -m command line switch then default to
    48576448           disassembling all types of ARM instruction.
    4858            
     6449
    48596450           The info->mach value has to be ignored as this will be based on
    48606451           the default archictecture for the target and/or hints in the notes
    … …  
    49066497      /* PR 14006.  When the address is 0 we are either at the start of the
    49076498         very first function, or else the first function in a new, unlinked
    4908          executable section (eg because uf -ffunction-sections).  Either way
     6499         executable section (eg because of -ffunction-sections).  Either way
    49096500         start scanning from the beginning of the symbol table, not where we
    49106501         left off last time.  */
    … …  
    50676658          type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
    50686659
    5069           is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
    5070                        == ST_BRANCH_TO_THUMB)
    5071                       || type == STT_ARM_16BIT);
     6660          is_thumb =
     6661            ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
     6662              == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
     6663        }
     6664      else if (bfd_asymbol_flavour (*info->symbols)
     6665               == bfd_target_mach_o_flavour)
     6666        {
     6667          bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
     6668
     6669          is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
    50726670        }
    50736671    }
Note: See TracChangeset for help on using the changeset viewer.