Changeset 1973 for binutils/trunk/ld/testsuite/ld-sh/arch/sh2a-nofpu.s
- Timestamp:
- Feb 6, 2017, 1:00:00 PM (8 years ago)
- Location:
- binutils/trunk
- Files:
-
- 2 edited
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- Unmodified
- Added
- Removed
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binutils/trunk ¶
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Property svn:mergeinfo
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/binutils/vendor/current merged eligible
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Property svn:mergeinfo
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TabularUnified binutils/trunk/ld/testsuite/ld-sh/arch/sh2a-nofpu.s ¶
r970 r1973 1 1 ! Generated file. DO NOT EDIT. 2 2 ! 3 ! This file was generated by gas/testsuite/gas/sh/arch/ arch.exp.3 ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . 4 4 ! This file should contain every instruction valid on 5 5 ! architecture sh2a-nofpu but no more. 6 ! If the tests are failing because the expected results 7 ! have changed then run 'make check' and copy the new file 8 ! from <objdir>/gas/testsuite/sh2a-nofpu.s 9 ! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu.s . 6 ! If the tests are failing because the expected results have changed then run 7 ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' 8 ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. 10 9 ! Make sure there are no unexpected or missing instructions. 11 10 … … 83 82 bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} 84 83 clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} 85 clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}86 84 clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} 87 85 cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} … … 166 164 or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} 167 165 or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} 168 pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh 4_nommu_nofpu_up}166 pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} 169 167 rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} 170 168 rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} … … 173 171 rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} 174 172 rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} 175 sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}176 173 sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} 177 174 shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
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