Changeset 1973 for binutils/trunk/gas/config/tc-arm.c

Timestamp:

Feb 6, 2017, 1:00:00 PM (8 years ago)

Author:

Silvan Scherrer

Message:

binutils: update trunk to version 2.27

Location:

binutils/trunk

Files:

• . (modified) (1 prop)
• gas/config/tc-arm.c (modified) (266 diffs)

binutils/trunk/gas/config/tc-arm.c ¶

@@ -1 +1 @@
 /* tc-arm.c -- Assemble for the ARM
-   Copyright (C) 1994-2014 Free Software Foundation, Inc.
+   Copyright (C) 1994-2016 Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
         Modified by David Taylor (dtaylor@armltd.co.uk)
@@ -156 +156 @@
 /* Constants for known architecture features.  */
 static const arm_feature_set fpu_default = FPU_DEFAULT;
-static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
+static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
-static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
-static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
+static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
+static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
+#ifdef OBJ_ELF
 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
+#endif
 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
 
@@ -169 +171 @@
 #endif
 
-static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
-static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
-static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
-static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
-static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
-static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
-static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
-static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
+static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
+static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
+static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
+static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
+static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
+static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
+static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
+static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
 static const arm_feature_set arm_ext_v4t_5 =
-  ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
-static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
-static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
-static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
-static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
-static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
-static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
-static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
-static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
-static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
-static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
-static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
-static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
-static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
-static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
-static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
-static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
-static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
-static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
+  ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
+static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
+static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
+static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
+static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
+static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
+static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
+static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
+static const arm_feature_set arm_ext_v6m = ARM_FEATURE_CORE_LOW (ARM_EXT_V6M);
+static const arm_feature_set arm_ext_v6_notm =
+  ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
+static const arm_feature_set arm_ext_v6_dsp =
+  ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
+static const arm_feature_set arm_ext_barrier =
+  ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
+static const arm_feature_set arm_ext_msr =
+  ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
+static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
+static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
+static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
+static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
+#ifdef OBJ_ELF
+static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
+#endif
+static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
 static const arm_feature_set arm_ext_m =
-  ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
-static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
-static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
-static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
-static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
-static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
+  ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M,
+                    ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
+static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
+static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
+static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
+static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
+static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
+static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
+static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
+static const arm_feature_set arm_ext_v8m_main =
+  ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
+/* Instructions in ARMv8-M only found in M profile architectures.  */
+static const arm_feature_set arm_ext_v8m_m_only =
+  ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
+static const arm_feature_set arm_ext_v6t2_v8m =
+  ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
+/* Instructions shared between ARMv8-A and ARMv8-M.  */
+static const arm_feature_set arm_ext_atomics =
+  ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
+#ifdef OBJ_ELF
+/* DSP instructions Tag_DSP_extension refers to.  */
+static const arm_feature_set arm_ext_dsp =
+  ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
+#endif
+static const arm_feature_set arm_ext_ras =
+  ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS);
+/* FP16 instructions.  */
+static const arm_feature_set arm_ext_fp16 =
+  ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
 
 static const arm_feature_set arm_arch_any = ARM_ANY;
-static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
+static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
+#ifdef OBJ_ELF
 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
+#endif
 
 static const arm_feature_set arm_cext_iwmmxt2 =
-  ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
+  ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
 static const arm_feature_set arm_cext_iwmmxt =
-  ARM_FEATURE (0, ARM_CEXT_IWMMXT);
+  ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
 static const arm_feature_set arm_cext_xscale =
-  ARM_FEATURE (0, ARM_CEXT_XSCALE);
+  ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
 static const arm_feature_set arm_cext_maverick =
-  ARM_FEATURE (0, ARM_CEXT_MAVERICK);
-static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
-static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
+  ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
+static const arm_feature_set fpu_fpa_ext_v1 =
+  ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
+static const arm_feature_set fpu_fpa_ext_v2 =
+  ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
 static const arm_feature_set fpu_vfp_ext_v1xd =
-  ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
-static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
-static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
-static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
-static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
+  ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
+static const arm_feature_set fpu_vfp_ext_v1 =
+  ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
+static const arm_feature_set fpu_vfp_ext_v2 =
+  ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
+static const arm_feature_set fpu_vfp_ext_v3xd =
+  ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
+static const arm_feature_set fpu_vfp_ext_v3 =
+  ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
 static const arm_feature_set fpu_vfp_ext_d32 =
-  ARM_FEATURE (0, FPU_VFP_EXT_D32);
-static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
+  ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
+static const arm_feature_set fpu_neon_ext_v1 =
+  ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
-  ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
-static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
-static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
-static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
+  ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
+#ifdef OBJ_ELF
+static const arm_feature_set fpu_vfp_fp16 =
+  ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
+static const arm_feature_set fpu_neon_ext_fma =
+  ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
+#endif
+static const arm_feature_set fpu_vfp_ext_fma =
+  ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
 static const arm_feature_set fpu_vfp_ext_armv8 =
-  ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
+  ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
+static const arm_feature_set fpu_vfp_ext_armv8xd =
+  ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
 static const arm_feature_set fpu_neon_ext_armv8 =
-  ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
+  ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
 static const arm_feature_set fpu_crypto_ext_armv8 =
-  ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
+  ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
 static const arm_feature_set crc_ext_armv8 =
-  ARM_FEATURE (0, CRC_EXT_ARMV8);
+  ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
+static const arm_feature_set fpu_neon_ext_v8_1 =
+  ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
 
 static int mfloat_abi_opt = -1;
@@ -248 +297 @@
 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
 /* Must be long enough to hold any of the names in arm_cpus.  */
-static char selected_cpu_name[16];
+static char selected_cpu_name[20];
 
 extern FLONUM_TYPE generic_floating_point_number;
@@ -256 +305 @@
 no_cpu_selected (void)
 {
-  return selected_cpu.core == arm_arch_none.core
-    && selected_cpu.coproc == arm_arch_none.coproc;
+  return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
 }
 
@@ -488 +536 @@
 struct reloc_entry
 {
-  char *                    name;
+  const char *                    name;
   bfd_reloc_code_real_type  reloc;
 };
@@ -756 +804 @@
 #define BAD_PC_WRITEBACK \
         _("cannot use writeback with PC-relative addressing")
-#define BAD_RANGE     _("branch out of range")
+#define BAD_RANGE       _("branch out of range")
+#define BAD_FP16        _("selected processor does not support fp16 instruction")
 #define UNPRED_REG(R)   _("using " R " results in unpredictable behaviour")
+#define THUMB1_RELOC_ONLY  _("relocation valid in thumb1 code only")
 
 static struct hash_control * arm_ops_hsh;
@@ -1047 +1097 @@
    ??? The format of 12 byte floats is uncertain according to gcc's arm.h.  */
 
-char *
+const char *
 md_atof (int type, char * litP, int * sizeP)
 {
@@ -1958 +2008 @@
   const char *const type_error = _("mismatched element/structure types in list");
   struct neon_typed_alias firsttype;
+  firsttype.defined = 0;
+  firsttype.eltype.type = NT_invtype;
+  firsttype.eltype.size = -1;
+  firsttype.index = -1;
 
   if (skip_past_char (&ptr, '{') == SUCCESS)
@@ -2150 +2204 @@
 
   name = xstrdup (str);
-  new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
+  new_reg = XNEW (struct reg_entry);
 
   new_reg->name = name;
@@ -2178 +2232 @@
   if (atype)
     {
-      reg->neon = (struct neon_typed_alias *)
-          xmalloc (sizeof (struct neon_typed_alias));
+      reg->neon = XNEW (struct neon_typed_alias);
       *reg->neon = *atype;
     }
@@ -2225 +2278 @@
 #endif
 
-  nbuf = (char *) alloca (nlen + 1);
-  memcpy (nbuf, newname, nlen);
-  nbuf[nlen] = '\0';
+  nbuf = xmemdup0 (newname, nlen);
 
   /* Create aliases under the new name as stated; an all-lowercase
@@ -2249 +2300 @@
              first .req.  */
           if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
-            return TRUE;
+            {
+              free (nbuf);
+              return TRUE;
+            }
         }
 
@@ -2259 +2313 @@
     }
 
+  free (nbuf);
   return TRUE;
 }
@@ -2386 +2441 @@
 #endif
 
-  namebuf = (char *) alloca (namelen + 1);
-  strncpy (namebuf, newname, namelen);
-  namebuf[namelen] = '\0';
+  namebuf = xmemdup0 (newname, namelen);
 
   insert_neon_reg_alias (namebuf, basereg->number, basetype,
@@ -2409 +2462 @@
                            typeinfo.defined != 0 ? &typeinfo : NULL);
 
+  free (namebuf);
   return TRUE;
 }
@@ -2631 +2685 @@
    emit some STATE bytes to the file.  */
 
+#define TRANSITION(from, to) (mapstate == (from) && state == (to))
 void
 mapping_state (enum mstate state)
 {
   enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
-
-#define TRANSITION(from, to) (mapstate == (from) && state == (to))
 
   if (mapstate == state)
@@ -2660 +2713 @@
 
   if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
-    /* This case will be evaluated later in the next else.  */
+    /* This case will be evaluated later.  */
     return;
-  else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
-          || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
-    {
-      /* Only add the symbol if the offset is > 0:
-         if we're at the first frag, check it's size > 0;
-         if we're not at the first frag, then for sure
-            the offset is > 0.  */
-      struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
-      const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
-
-      if (add_symbol)
-        make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
-    }
 
   mapping_state_2 (state, 0);
-#undef TRANSITION
 }
 
@@ -2696 +2735 @@
     return;
 
+  if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
+          || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
+    {
+      struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
+      const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
+
+      if (add_symbol)
+        make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
+    }
+
   seg_info (now_seg)->tc_segment_info_data.mapstate = state;
   make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
 }
+#undef TRANSITION
 #else
 #define mapping_state(x) ((void)0)
@@ -2728 +2778 @@
     return symbolP;
 
-  real_start = ACONCAT ((STUB_NAME, name, NULL));
+  real_start = concat (STUB_NAME, name, NULL);
   new_target = symbol_find (real_start);
+  free (real_start);
 
   if (new_target == NULL)
@@ -2855 +2906 @@
      This just grew, and could be parsed much more simply!
      Dean - in haste.  */
-  name      = input_line_pointer;
-  delim     = get_symbol_end ();
+  delim     = get_symbol_name (& name);
   end_name  = input_line_pointer;
-  *end_name = delim;
+  (void) restore_line_pointer (delim);
 
   if (*input_line_pointer != ',')
@@ -2938 +2988 @@
   char *name, delim;
 
-  name = input_line_pointer;
-  delim = get_symbol_end ();
+  delim = get_symbol_name (& name);
 
   if (!strcasecmp (name, "unified"))
@@ -2950 +2999 @@
       return;
     }
-  *input_line_pointer = delim;
+  (void) restore_line_pointer (delim);
   demand_empty_rest_of_line ();
 }
 
 /* Directives: sectioning and alignment.  */
-
-/* Same as s_align_ptwo but align 0 => align 2.  */
-
-static void
-s_align (int unused ATTRIBUTE_UNUSED)
-{
-  int temp;
-  bfd_boolean fill_p;
-  long temp_fill;
-  long max_alignment = 15;
-
-  temp = get_absolute_expression ();
-  if (temp > max_alignment)
-    as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
-  else if (temp < 0)
-    {
-      as_bad (_("alignment negative. 0 assumed."));
-      temp = 0;
-    }
-
-  if (*input_line_pointer == ',')
-    {
-      input_line_pointer++;
-      temp_fill = get_absolute_expression ();
-      fill_p = TRUE;
-    }
-  else
-    {
-      fill_p = FALSE;
-      temp_fill = 0;
-    }
-
-  if (!temp)
-    temp = 2;
-
-  /* Only make a frag if we HAVE to.  */
-  if (temp && !need_pass_2)
-    {
-      if (!fill_p && subseg_text_p (now_seg))
-        frag_align_code (temp, 0);
-      else
-        frag_align (temp, (int) temp_fill, 0);
-    }
-  demand_empty_rest_of_line ();
-
-  record_alignment (now_seg, temp);
-}
 
 static void
@@ -3155 +3157 @@
     {
       /* Create a new pool.  */
-      pool = (literal_pool *) xmalloc (sizeof (* pool));
+      pool = XNEW (literal_pool);
       if (! pool)
         return NULL;
@@ -3293 +3295 @@
 
               pool->literals[entry] = inst.reloc.exp;
+              pool->literals[entry].X_op = O_constant;
               pool->literals[entry].X_add_number = 0;
               pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
@@ -3347 +3350 @@
 
 bfd_boolean
-tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED, const char * rest)
+tc_start_label_without_colon (void)
 {
   bfd_boolean ret = TRUE;
@@ -3353 +3356 @@
   if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
     {
-      const char *label = rest;
+      const char *label = input_line_pointer;
 
       while (!is_end_of_line[(int) label[-1]])
@@ -3552 +3555 @@
                   char *p = input_line_pointer;
                   int offset;
-                  char *save_buf = (char *) alloca (input_line_pointer - base);
+                  char *save_buf = XNEWVEC (char, input_line_pointer - base);
+
                   memcpy (save_buf, base, input_line_pointer - base);
                   memmove (base + (input_line_pointer - before_reloc),
@@ -3566 +3570 @@
                   fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
                                size, &exp, 0, (enum bfd_reloc_code_real) reloc);
+                  free (save_buf);
                 }
             }
@@ -3914 +3919 @@
     as_bad (_("duplicate .personality directive"));
 
-  name = input_line_pointer;
-  c = get_symbol_end ();
+  c = get_symbol_name (& name);
   p = input_line_pointer;
+  if (c == '"')
+    ++ input_line_pointer;
   unwind.personality_routine = symbol_find_or_make (name);
   *p = c;
@@ -4678 +4684 @@
   { "unreq",       s_unreq,       0 },
   { "bss",         s_bss,         0 },
-  { "align",       s_align,       0 },
+  { "align",       s_align_ptwo,  2 },
   { "arm",         s_arm,         0 },
   { "thumb",       s_thumb,       0 },
@@ -4912 +4918 @@
       /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
          Ditto for 15.  */
-      if (gen_to_words (words, 5, (long) 15) == 0)
+#define X_PRECISION 5
+#define E_PRECISION 15L
+      if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
         {
           for (i = 0; i < NUM_FLOAT_VALS; i++)
@@ -4961 +4969 @@
 
   ++*in;
+
+  /* Accept #0x0 as a synonym for #0.  */
+  if (strncmp (*in, "0x", 2) == 0)
+    {
+      int val;
+      if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
+        return FALSE;
+      return TRUE;
+    }
+
   error_code = atof_generic (in, ".", EXP_CHARS,
                              &generic_floating_point_number);
@@ -5297 +5315 @@
       BFD_RELOC_ARM_LDR_SB_G2,          /* LDR */
       BFD_RELOC_ARM_LDRS_SB_G2,         /* LDRS */
-      BFD_RELOC_ARM_LDC_SB_G2 } };      /* LDC */
+      BFD_RELOC_ARM_LDC_SB_G2 },        /* LDC */
+    /* Absolute thumb alu relocations.  */
+    { "lower0_7",
+      BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU.  */
+      0,                                /* LDR.  */
+      0,                                /* LDRS.  */
+      0 },                              /* LDC.  */
+    { "lower8_15",
+      BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU.  */
+      0,                                /* LDR.  */
+      0,                                /* LDRS.  */
+      0 },                              /* LDC.  */
+    { "upper0_7",
+      BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU.  */
+      0,                                /* LDR.  */
+      0,                                /* LDRS.  */
+      0 },                              /* LDC.  */
+    { "upper8_15",
+      BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU.  */
+      0,                                /* LDR.  */
+      0,                                /* LDRS.  */
+      0 } };                            /* LDC.  */
 
 /* Given the address of a pointer pointing to the textual name of a group
@@ -5763 +5802 @@
      be TRUE, but we want to ignore it in this case as we are building for any
      CPU type, including non-m variants.  */
-  if (selected_cpu.core == arm_arch_any.core)
+  if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
     m_profile = FALSE;
 
@@ -6076 +6115 @@
 }
 
+/* Record a use of the given feature.  */
+static void
+record_feature_use (const arm_feature_set *feature)
+{
+  if (thumb_mode)
+    ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
+  else
+    ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
+}
+
 /* If the given feature available in the selected CPU, mark it as used.
    Returns TRUE iff feature is available.  */
@@ -6087 +6136 @@
   /* Add the appropriate architecture feature for the barrier option used.
      */
-  if (thumb_mode)
-    ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
-  else
-    ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
+  record_feature_use (feature);
 
   return TRUE;
@@ -7032 +7078 @@
           if (*str == '^')
             {
-              inst.operands[1].writeback = 1;
+              inst.operands[i].writeback = 1;
               str++;
             }
@@ -7248 +7294 @@
   do                                            \
     if (warn_on_deprecated && reg == REG_SP)    \
-       as_warn (_("use of r13 is deprecated")); \
+       as_tsktsk (_("use of r13 is deprecated"));       \
   while (0)
 
 /* Functions for operand encoding.  ARM, then Thumb.  */
 
-#define rotate_left(v, n) (v << n | v >> (32 - n))
+#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
+
+/* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
+
+   The only binary encoding difference is the Coprocessor number.  Coprocessor
+   9 is used for half-precision calculations or conversions.  The format of the
+   instruction is the same as the equivalent Coprocessor 10 instuction that
+   exists for Single-Precision operation.  */
+
+static void
+do_scalar_fp16_v82_encode (void)
+{
+  if (inst.cond != COND_ALWAYS)
+    as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
+               " the behaviour is UNPREDICTABLE"));
+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
+              _(BAD_FP16));
+
+  inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
+  mark_feature_used (&arm_ext_fp16);
+}
 
 /* If VAL can be encoded in the immediate field of an ARM instruction,
@@ -7263 +7329 @@
   unsigned int a, i;
 
-  for (i = 0; i < 32; i += 2)
+  if (val <= 0xff)
+    return val;
+
+  for (i = 2; i < 32; i += 2)
     if ((a = rotate_left (val, i)) <= 0xff)
       return a | (i << 7); /* 12-bit pack: [shift-cnt,const].  */
@@ -7480 +7549 @@
               && !is_load
               && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
-            as_warn (_("use of PC in this instruction is deprecated"));
+            as_tsktsk (_("use of PC in this instruction is deprecated"));
         }
 
@@ -7728 +7797 @@
 }
 
+#if defined BFD_HOST_64_BIT
+/* Returns TRUE if double precision value V may be cast
+   to single precision without loss of accuracy.  */
+
+static bfd_boolean
+is_double_a_single (bfd_int64_t v)
+{
+  int exp = (int)((v >> 52) & 0x7FF);
+  bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
+
+  return (exp == 0 || exp == 0x7FF
+          || (exp >= 1023 - 126 && exp <= 1023 + 127))
+    && (mantissa & 0x1FFFFFFFl) == 0;
+}
+
+/* Returns a double precision value casted to single precision
+   (ignoring the least significant bits in exponent and mantissa).  */
+
+static int
+double_to_single (bfd_int64_t v)
+{
+  int sign = (int) ((v >> 63) & 1l);
+  int exp = (int) ((v >> 52) & 0x7FF);
+  bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
+
+  if (exp == 0x7FF)
+    exp = 0xFF;
+  else
+    {
+      exp = exp - 1023 + 127;
+      if (exp >= 0xFF)
+        {
+          /* Infinity.  */
+          exp = 0x7F;
+          mantissa = 0;
+        }
+      else if (exp < 0)
+        {
+          /* No denormalized numbers.  */
+          exp = 0;
+          mantissa = 0;
+        }
+    }
+  mantissa >>= 29;
+  return (sign << 31) | (exp << 23) | mantissa;
+}
+#endif /* BFD_HOST_64_BIT */
+
 enum lit_type
 {
@@ -7734 +7851 @@
   CONST_VEC
 };
+
+static void do_vfp_nsyn_opcode (const char *);
 
 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
@@ -7750 +7869 @@
   bfd_boolean thumb_p = (t == CONST_THUMB);
   bfd_boolean arm_p   = (t == CONST_ARM);
-  bfd_boolean vec64_p = (t == CONST_VEC) && !inst.operands[i].issingle;
 
   if (thumb_p)
@@ -7762 +7880 @@
       return TRUE;
     }
+
   if (inst.reloc.exp.X_op != O_constant
       && inst.reloc.exp.X_op != O_symbol
@@ -7769 +7888 @@
       return TRUE;
     }
-  if ((inst.reloc.exp.X_op == O_constant
-       || inst.reloc.exp.X_op == O_big)
-      && !inst.operands[i].issingle)
-    {
-      if (thumb_p && inst.reloc.exp.X_op == O_constant)
-        {
-          if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
+
+  if (inst.reloc.exp.X_op == O_constant
+      || inst.reloc.exp.X_op == O_big)
+    {
+#if defined BFD_HOST_64_BIT
+      bfd_int64_t v;
+#else
+      offsetT v;
+#endif
+      if (inst.reloc.exp.X_op == O_big)
+        {
+          LITTLENUM_TYPE w[X_PRECISION];
+          LITTLENUM_TYPE * l;
+
+          if (inst.reloc.exp.X_add_number == -1)
             {
-              /* This can be done with a mov(1) instruction.  */
-              inst.instruction  = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
-              inst.instruction |= inst.reloc.exp.X_add_number;
+              gen_to_words (w, X_PRECISION, E_PRECISION);
+              l = w;
+              /* FIXME: Should we check words w[2..5] ?  */
+            }
+          else
+            l = generic_bignum;
+
+#if defined BFD_HOST_64_BIT
+          v =
+            ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
+                  << LITTLENUM_NUMBER_OF_BITS)
+                 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
+                << LITTLENUM_NUMBER_OF_BITS)
+               | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
+              << LITTLENUM_NUMBER_OF_BITS)
+             | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
+#else
+          v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
+            |  (l[0] & LITTLENUM_MASK);
+#endif
+        }
+      else
+        v = inst.reloc.exp.X_add_number;
+
+      if (!inst.operands[i].issingle)
+        {
+          if (thumb_p)
+            {
+              /* This can be encoded only for a low register.  */
+              if ((v & ~0xFF) == 0 && (inst.operands[i].reg < 8))
+                {
+                  /* This can be done with a mov(1) instruction.  */
+                  inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
+                  inst.instruction |= v;
+                  return TRUE;
+                }
+
+              if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
+                  || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
+                {
+                  /* Check if on thumb2 it can be done with a mov.w, mvn or
+                     movw instruction.  */
+                  unsigned int newimm;
+                  bfd_boolean isNegated;
+
+                  newimm = encode_thumb32_immediate (v);
+                  if (newimm != (unsigned int) FAIL)
+                    isNegated = FALSE;
+                  else
+                    {
+                      newimm = encode_thumb32_immediate (~v);
+                      if (newimm != (unsigned int) FAIL)
+                        isNegated = TRUE;
+                    }
+
+                  /* The number can be loaded with a mov.w or mvn
+                     instruction.  */
+                  if (newimm != (unsigned int) FAIL
+                      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
+                    {
+                      inst.instruction = (0xf04f0000  /*  MOV.W.  */
+                                          | (inst.operands[i].reg << 8));
+                      /* Change to MOVN.  */
+                      inst.instruction |= (isNegated ? 0x200000 : 0);
+                      inst.instruction |= (newimm & 0x800) << 15;
+                      inst.instruction |= (newimm & 0x700) << 4;
+                      inst.instruction |= (newimm & 0x0ff);
+                      return TRUE;
+                    }
+                  /* The number can be loaded with a movw instruction.  */
+                  else if ((v & ~0xFFFF) == 0
+                           && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
+                    {
+                      int imm = v & 0xFFFF;
+
+                      inst.instruction = 0xf2400000;  /* MOVW.  */
+                      inst.instruction |= (inst.operands[i].reg << 8);
+                      inst.instruction |= (imm & 0xf000) << 4;
+                      inst.instruction |= (imm & 0x0800) << 15;
+                      inst.instruction |= (imm & 0x0700) << 4;
+                      inst.instruction |= (imm & 0x00ff);
+                      return TRUE;
+                    }
+                }
+            }
+          else if (arm_p)
+            {
+              int value = encode_arm_immediate (v);
+
+              if (value != FAIL)
+                {
+                  /* This can be done with a mov instruction.  */
+                  inst.instruction &= LITERAL_MASK;
+                  inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
+                  inst.instruction |= value & 0xfff;
+                  return TRUE;
+                }
+
+              value = encode_arm_immediate (~ v);
+              if (value != FAIL)
+                {
+                  /* This can be done with a mvn instruction.  */
+                  inst.instruction &= LITERAL_MASK;
+                  inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
+                  inst.instruction |= value & 0xfff;
+                  return TRUE;
+                }
+            }
+          else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
+            {
+              int op = 0;
+              unsigned immbits = 0;
+              unsigned immlo = inst.operands[1].imm;
+              unsigned immhi = inst.operands[1].regisimm
+                ? inst.operands[1].reg
+                : inst.reloc.exp.X_unsigned
+                ? 0
+                : ((bfd_int64_t)((int) immlo)) >> 32;
+              int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
+                                                   &op, 64, NT_invtype);
+
+              if (cmode == FAIL)
+                {
+                  neon_invert_size (&immlo, &immhi, 64);
+                  op = !op;
+                  cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
+                                                   &op, 64, NT_invtype);
+                }
+
+              if (cmode != FAIL)
+                {
+                  inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
+                    | (1 << 23)
+                    | (cmode << 8)
+                    | (op << 5)
+                    | (1 << 4);
+
+                  /* Fill other bits in vmov encoding for both thumb and arm.  */
+                  if (thumb_mode)
+                    inst.instruction |= (0x7U << 29) | (0xF << 24);
+                  else
+                    inst.instruction |= (0xFU << 28) | (0x1 << 25);
+                  neon_write_immbits (immbits);
+                  return TRUE;
+                }
+            }
+        }
+
+      if (t == CONST_VEC)
+        {
+          /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant.  */
+          if (inst.operands[i].issingle
+              && is_quarter_float (inst.operands[1].imm)
+              && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
+            {
+              inst.operands[1].imm =
+                neon_qfloat_bits (v);
+              do_vfp_nsyn_opcode ("fconsts");
               return TRUE;
             }
-        }
-      else if (arm_p && inst.reloc.exp.X_op == O_constant)
-        {
-          int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
-          if (value != FAIL)
+
+          /* If our host does not support a 64-bit type then we cannot perform
+             the following optimization.  This mean that there will be a
+             discrepancy between the output produced by an assembler built for
+             a 32-bit-only host and the output produced from a 64-bit host, but
+             this cannot be helped.  */
+#if defined BFD_HOST_64_BIT
+          else if (!inst.operands[1].issingle
+                   && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
             {
-              /* This can be done with a mov instruction.  */
-              inst.instruction &= LITERAL_MASK;
-              inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
-              inst.instruction |= value & 0xfff;
-              return TRUE;
+              if (is_double_a_single (v)
+                  && is_quarter_float (double_to_single (v)))
+                {
+                  inst.operands[1].imm =
+                    neon_qfloat_bits (double_to_single (v));
+                  do_vfp_nsyn_opcode ("fconstd");
+                  return TRUE;
+                }
             }
-
-          value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
-          if (value != FAIL)
-            {
-              /* This can be done with a mvn instruction.  */
-              inst.instruction &= LITERAL_MASK;
-              inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
-              inst.instruction |= value & 0xfff;
-              return TRUE;
-            }
-        }
-      else if (vec64_p)
-        {
-          int op = 0;
-          unsigned immbits = 0;
-          unsigned immlo = inst.operands[1].imm;
-          unsigned immhi = inst.operands[1].regisimm
-                           ? inst.operands[1].reg
-                           : inst.reloc.exp.X_unsigned
-                             ? 0
-                             : ((bfd_int64_t)((int) immlo)) >> 32;
-          int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
-                                               &op, 64, NT_invtype);
-
-          if (cmode == FAIL)
-            {
-              neon_invert_size (&immlo, &immhi, 64);
-              op = !op;
-              cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
-                                               &op, 64, NT_invtype);
-            }
-          if (cmode != FAIL)
-            {
-              inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
-                                  | (1 << 23)
-                                  | (cmode << 8)
-                                  | (op << 5)
-                                  | (1 << 4);
-              /* Fill other bits in vmov encoding for both thumb and arm.  */
-              if (thumb_mode)
-                inst.instruction |= (0x7 << 29) | (0xF << 24);
-              else
-                inst.instruction |= (0xF << 28) | (0x1 << 25);
-              neon_write_immbits (immbits);
-              return TRUE;
-            }
+#endif
         }
     }
@@ -7872 +8116 @@
   if (!inst.operands[i].isreg)
     {
-      gas_assert (inst.operands[0].isvec);
+      /* PR 18256 */
+      if (! inst.operands[0].isvec)
+        {
+          inst.error = _("invalid co-processor operand");
+          return FAIL;
+        }
       if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
         return SUCCESS;
@@ -7947 +8196 @@
 
 static void
+do_rn (void)
+{
+  inst.instruction |= inst.operands[0].reg << 16;
+}
+
+static void
 do_rd_rm (void)
 {
@@ -7974 +8229 @@
 }
 
+static void
+do_tt (void)
+{
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 16;
+}
+
 static bfd_boolean
 check_obsolete (const arm_feature_set *feature, const char *msg)
@@ -7979 +8241 @@
   if (ARM_CPU_IS_ANY (cpu_variant))
     {
-      as_warn ("%s", msg);
+      as_tsktsk ("%s", msg);
       return TRUE;
     }
@@ -8007 +8269 @@
           && warn_on_deprecated
           && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
-        as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
+        as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
     }
 
@@ -8089 +8351 @@
 do_arit (void)
 {
+  constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
+              && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
+              THUMB1_RELOC_ONLY);
   if (!inst.operands[1].present)
     inst.operands[1].reg = inst.operands[0].reg;
@@ -8325 +8590 @@
 {
     {15, 0, 7, 10, 5,                                   /* CP15DMB.  */
-     ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
+     ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
      DEPR_ACCESS_V8, NULL},
     {15, 0, 7, 10, 4,                                   /* CP15DSB.  */
-     ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
+     ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
      DEPR_ACCESS_V8, NULL},
     {15, 0, 7,  5, 4,                                   /* CP15ISB.  */
-     ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
+     ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
      DEPR_ACCESS_V8, NULL},
     {14, 6, 1,  0, 0,                                   /* TEEHBR.  */
-     ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
+     ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
      DEPR_ACCESS_V8, NULL},
     {14, 6, 0,  0, 0,                                   /* TEECR.  */
-     ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
+     ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
      DEPR_ACCESS_V8, NULL},
 };
@@ -8384 +8649 @@
                 && warn_on_deprecated
                 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
-              as_warn ("%s", r->dep_msg);
+              as_tsktsk ("%s", r->dep_msg);
           }
       }
@@ -8746 +9011 @@
 do_mov (void)
 {
+  constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
+              && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
+              THUMB1_RELOC_ONLY);
   inst.instruction |= inst.operands[0].reg << 12;
   encode_arm_shifter_operand (1);
@@ -8771 +9039 @@
     }
 }
-
-static void do_vfp_nsyn_opcode (const char *);
 
 static int
@@ -9030 +9296 @@
 do_push_pop (void)
 {
+  constraint (inst.operands[0].writeback,
+              _("push/pop do not support {reglist}^"));
   inst.operands[1] = inst.operands[0];
   memset (&inst.operands[0], 0, sizeof inst.operands[0]);
@@ -9107 +9375 @@
   if (warn_on_deprecated
       && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
-      as_warn (_("setend use is deprecated for ARMv8"));
+      as_tsktsk (_("setend use is deprecated for ARMv8"));
 
   if (inst.operands[0].imm)
@@ -9153 +9421 @@
   inst.reloc.type = BFD_RELOC_ARM_SWI;
   inst.reloc.pc_rel = 0;
+}
+
+static void
+do_setpan (void)
+{
+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
+              _("selected processor does not support SETPAN instruction"));
+
+  inst.instruction |= ((inst.operands[0].imm & 1) << 9);
+}
+
+static void
+do_t_setpan (void)
+{
+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
+              _("selected processor does not support SETPAN instruction"));
+
+  inst.instruction |= (inst.operands[0].imm << 3);
 }
 
@@ -9753 +10039 @@
     {
       inst.instruction &= ~0x1a000ff;
-      inst.instruction |= (0xf << 28);
+      inst.instruction |= (0xfU << 28);
       if (inst.operands[1].preind)
         inst.instruction |= PRE_INDEX;
@@ -9832 +10118 @@
     /* Map 32 -> 0, etc.  */
     inst.operands[2].imm &= 0x1f;
-    inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
+    inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
   }
 }
@@ -10232 +10518 @@
                   inst.instruction = THUMB_OP16(opcode);
                   inst.instruction |= (Rd << 4) | Rs;
-                  inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
-                  if (inst.size_req != 2)
-                    inst.relax = opcode;
+                  if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
+                      || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
+                  {
+                    if (inst.size_req == 2)
+                      inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
+                    else
+                      inst.relax = opcode;
+                  }
                 }
               else
@@ -10242 +10533 @@
               || (inst.size_req != 2 && !opcode))
             {
+              constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
+                          && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
+                          THUMB1_RELOC_ONLY);
               if (Rd == REG_PC)
                 {
@@ -10710 +11004 @@
   int opcode;
   int cond;
-  int reloc;
+  bfd_reloc_code_real_type reloc;
 
   cond = inst.cond;
@@ -10740 +11034 @@
       else
         {
+          constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
+                      _("selected architecture does not support "
+                        "wide conditional branch instruction"));
+
           gas_assert (cond != 0xF);
           inst.instruction |= cond << 22;
@@ -11556 +11854 @@
                       && (Rm == REG_SP || Rm == REG_PC))
                     {
-                      as_warn (_("Use of r%u as a source register is "
+                      as_tsktsk (_("Use of r%u as a source register is "
                                  "deprecated when r%u is the destination "
                                  "register."), Rm, Rn);
@@ -11582 +11880 @@
               inst.instruction = THUMB_OP16 (opcode);
               inst.instruction |= Rn << 8;
-              if (inst.size_req == 2)
-                inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
-              else
-                inst.relax = opcode;
+              if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
+                  || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
+                {
+                  if (inst.size_req == 2)
+                    inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
+                  else
+                    inst.relax = opcode;
+                }
             }
           else
             {
+              constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
+                          && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
+                          THUMB1_RELOC_ONLY);
+
               inst.instruction = THUMB_OP32 (inst.instruction);
               inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
@@ -11918 +12224 @@
              If the user has specified -march=all, we want to ignore it as
              we are building for any CPU type, including non-m variants.  */
-          bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
+          bfd_boolean m_profile =
+            !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
           constraint ((flags != 0) && m_profile, _("selected processor does "
                                                    "not support requested special purpose register"));
@@ -11958 +12265 @@
          If the user has specified -march=all, we want to ignore it as
          we are building for any CPU type, including non-m variants.  */
-      bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
+      bfd_boolean m_profile =
+        !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
       constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
            && (bits & ~(PSR_s | PSR_f)) != 0)
@@ -12241 +12549 @@
     inst.instruction = THUMB_OP16 (inst.instruction) | mask;
   else if (inst.size_req != 4
-           && (mask & ~0xff) == (1 << (inst.instruction == T_MNEM_push
+           && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
                                        ? REG_LR : REG_PC)))
     {
@@ -12380 +12688 @@
   if (warn_on_deprecated
       && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
-      as_warn (_("setend use is deprecated for ARMv8"));
+      as_tsktsk (_("setend use is deprecated for ARMv8"));
 
   set_it_insn_type (OUTSIDE_IT_INSN);
@@ -12875 +13183 @@
   X(vqdmulh,    0x0000b00, N_INV,     0x0800c40),       \
   X(vqrdmulh,   0x1000b00, N_INV,     0x0800d40),       \
+  X(vqrdmlah,   0x3000b10, N_INV,     0x0800e40),       \
+  X(vqrdmlsh,   0x3000c10, N_INV,     0x0800f40),       \
   X(vshl,       0x0000400, N_INV,     0x0800510),       \
   X(vqshl,      0x0000410, N_INV,     0x0800710),       \
@@ -13028 +13338 @@
   X(2, (R, S), SINGLE),                 \
   X(2, (F, R), SINGLE),                 \
-  X(2, (R, F), SINGLE)
+  X(2, (R, F), SINGLE),                 \
+/* Half float shape supported so far.  */\
+  X (2, (H, D), MIXED),                 \
+  X (2, (D, H), MIXED),                 \
+  X (2, (H, F), MIXED),                 \
+  X (2, (F, H), MIXED),                 \
+  X (2, (H, H), HALF),                  \
+  X (2, (H, R), HALF),                  \
+  X (2, (R, H), HALF),                  \
+  X (2, (H, I), HALF),                  \
+  X (3, (H, H, H), HALF),               \
+  X (3, (H, F, I), MIXED),              \
+  X (3, (F, H, I), MIXED)
 
 #define S2(A,B)         NS_##A##B
@@ -13049 +13371 @@
 enum neon_shape_class
 {
+  SC_HALF,
   SC_SINGLE,
   SC_DOUBLE,
@@ -13066 +13389 @@
 enum neon_shape_el
 {
+  SE_H,
   SE_F,
   SE_D,
@@ -13078 +13402 @@
 static unsigned neon_shape_el_size[] =
 {
+  16,
   32,
   64,
@@ -13159 +13484 @@
 #define N_SU_32    (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
-#define N_SUF_32   (N_SU_32 | N_F32)
+#define N_S_32     (N_S8 | N_S16 | N_S32)
+#define N_F_16_32  (N_F16 | N_F32)
+#define N_SUF_32   (N_SU_32 | N_F_16_32)
 #define N_I_ALL    (N_I8 | N_I16 | N_I32 | N_I64)
-#define N_IF_32    (N_I8 | N_I16 | N_I32 | N_F32)
+#define N_IF_32    (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
+#define N_F_ALL    (N_F16 | N_F32 | N_F64)
 
 /* Pass this as the first type argument to neon_check_type to ignore types
@@ -13203 +13531 @@
           switch (neon_shape_tab[shape].el[j])
             {
+              /* If a  .f16,  .16,  .u16,  .s16 type specifier is given over
+                 a VFP single precision register operand, it's essentially
+                 means only half of the register is used.
+
+                 If the type specifier is given after the mnemonics, the
+                 information is stored in inst.vectype.  If the type specifier
+                 is given after register operand, the information is stored
+                 in inst.operands[].vectype.
+
+                 When there is only one type specifier, and all the register
+                 operands are the same type of hardware register, the type
+                 specifier applies to all register operands.
+
+                 If no type specifier is given, the shape is inferred from
+                 operand information.
+
+                 for example:
+                 vadd.f16 s0, s1, s2:           NS_HHH
+                 vabs.f16 s0, s1:               NS_HH
+                 vmov.f16 s0, r1:               NS_HR
+                 vmov.f16 r0, s1:               NS_RH
+                 vcvt.f16 r0, s1:               NS_RH
+                 vcvt.f16.s32   s2, s2, #29:    NS_HFI
+                 vcvt.f16.s32   s2, s2:         NS_HF
+              */
+            case SE_H:
+              if (!(inst.operands[j].isreg
+                    && inst.operands[j].isvec
+                    && inst.operands[j].issingle
+                    && !inst.operands[j].isquad
+                    && ((inst.vectype.elems == 1
+                         && inst.vectype.el[0].size == 16)
+                        || (inst.vectype.elems > 1
+                            && inst.vectype.el[j].size == 16)
+                        || (inst.vectype.elems == 0
+                            && inst.operands[j].vectype.type != NT_invtype
+                            && inst.operands[j].vectype.size == 16))))
+                matches = 0;
+              break;
+
             case SE_F:
               if (!(inst.operands[j].isreg
                     && inst.operands[j].isvec
                     && inst.operands[j].issingle
-                    && !inst.operands[j].isquad))
+                    && !inst.operands[j].isquad
+                    && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
+                        || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
+                        || (inst.vectype.elems == 0
+                            && (inst.operands[j].vectype.size == 32
+                                || inst.operands[j].vectype.type == NT_invtype)))))
                 matches = 0;
               break;
@@ -13423 +13796 @@
   else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
     *type = NT_poly;
-  else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
+  else if ((mask & (N_F_ALL)) != 0)
     *type = NT_float;
   else
@@ -13585 +13958 @@
                   k_size = g_size;
                   key_allowed = thisarg & ~N_KEY;
+
+                  /* Check architecture constraint on FP16 extension.  */
+                  if (k_size == 16
+                      && k_type == NT_float
+                      && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
+                    {
+                      inst.error = _(BAD_FP16);
+                      return badtype;
+                    }
                 }
             }
@@ -13610 +13992 @@
                   else
                     match = g_size;
+
+                  /* FP16 will use a single precision register.  */
+                  if (regwidth == 32 && match == 16)
+                    {
+                      if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
+                        match = regwidth;
+                      else
+                        {
+                          inst.error = _(BAD_FP16);
+                          return badtype;
+                        }
+                    }
 
                   if (regwidth != match)
@@ -13702 +14096 @@
   int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
 
-  if (rs == NS_FFF)
+  if (rs == NS_FFF || rs == NS_HHH)
     {
       if (is_add)
@@ -13708 +14102 @@
       else
         do_vfp_nsyn_opcode ("fsubs");
+
+      /* ARMv8.2 fp16 instruction.  */
+      if (rs == NS_HHH)
+        do_scalar_fp16_v82_encode ();
     }
   else
@@ -13730 +14128 @@
     {
     case 2:
-      rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
-      et = neon_check_type (2, rs,
-        N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+      rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
+      et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
       break;
 
     case 3:
-      rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
-      et = neon_check_type (3, rs,
-        N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+      rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
+      et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
+                            N_F_ALL | N_KEY | N_VFP);
       break;
 
@@ -13760 +14157 @@
   int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
 
-  if (rs == NS_FFF)
+  if (rs == NS_FFF || rs == NS_HHH)
     {
       if (is_mla)
@@ -13766 +14163 @@
       else
         do_vfp_nsyn_opcode ("fnmacs");
+
+      /* ARMv8.2 fp16 instruction.  */
+      if (rs == NS_HHH)
+        do_scalar_fp16_v82_encode ();
     }
   else
@@ -13781 +14182 @@
   int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
 
-  if (rs == NS_FFF)
+  if (rs == NS_FFF || rs == NS_HHH)
     {
       if (is_fma)
@@ -13787 +14188 @@
       else
         do_vfp_nsyn_opcode ("ffnmas");
+
+      /* ARMv8.2 fp16 instruction.  */
+      if (rs == NS_HHH)
+        do_scalar_fp16_v82_encode ();
     }
   else
@@ -13800 +14205 @@
 do_vfp_nsyn_mul (enum neon_shape rs)
 {
-  if (rs == NS_FFF)
-    do_vfp_nsyn_opcode ("fmuls");
+  if (rs == NS_FFF || rs == NS_HHH)
+    {
+      do_vfp_nsyn_opcode ("fmuls");
+
+      /* ARMv8.2 fp16 instruction.  */
+      if (rs == NS_HHH)
+        do_scalar_fp16_v82_encode ();
+    }
   else
     do_vfp_nsyn_opcode ("fmuld");
@@ -13810 +14221 @@
 {
   int is_neg = (inst.instruction & 0x80) != 0;
-  neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
-
-  if (rs == NS_FF)
+  neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
+
+  if (rs == NS_FF || rs == NS_HH)
     {
       if (is_neg)
@@ -13818 +14229 @@
       else
         do_vfp_nsyn_opcode ("fabss");
+
+      /* ARMv8.2 fp16 instruction.  */
+      if (rs == NS_HH)
+        do_scalar_fp16_v82_encode ();
     }
   else
@@ -13854 +14269 @@
 do_vfp_nsyn_sqrt (void)
 {
-  enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
-  neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
-
-  if (rs == NS_FF)
-    do_vfp_nsyn_opcode ("fsqrts");
+  enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
+  neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
+
+  if (rs == NS_FF || rs == NS_HH)
+    {
+      do_vfp_nsyn_opcode ("fsqrts");
+
+      /* ARMv8.2 fp16 instruction.  */
+      if (rs == NS_HH)
+        do_scalar_fp16_v82_encode ();
+    }
   else
     do_vfp_nsyn_opcode ("fsqrtd");
@@ -13866 +14287 @@
 do_vfp_nsyn_div (void)
 {
-  enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
+  enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
   neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
-    N_F32 | N_F64 | N_KEY | N_VFP);
-
-  if (rs == NS_FFF)
-    do_vfp_nsyn_opcode ("fdivs");
+                   N_F_ALL | N_KEY | N_VFP);
+
+  if (rs == NS_FFF || rs == NS_HHH)
+    {
+      do_vfp_nsyn_opcode ("fdivs");
+
+      /* ARMv8.2 fp16 instruction.  */
+      if (rs == NS_HHH)
+        do_scalar_fp16_v82_encode ();
+    }
   else
     do_vfp_nsyn_opcode ("fdivd");
@@ -13879 +14306 @@
 do_vfp_nsyn_nmul (void)
 {
-  enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
+  enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
   neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
-    N_F32 | N_F64 | N_KEY | N_VFP);
-
-  if (rs == NS_FFF)
+                   N_F_ALL | N_KEY | N_VFP);
+
+  if (rs == NS_FFF || rs == NS_HHH)
     {
       NEON_ENCODE (SINGLE, inst);
       do_vfp_sp_dyadic ();
+
+      /* ARMv8.2 fp16 instruction.  */
+      if (rs == NS_HHH)
+        do_scalar_fp16_v82_encode ();
     }
   else
@@ -13894 +14325 @@
     }
   do_vfp_cond_or_thumb ();
+
 }
 
@@ -13899 +14331 @@
 do_vfp_nsyn_cmp (void)
 {
+  enum neon_shape rs;
   if (inst.operands[1].isreg)
     {
-      enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
-      neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
-
-      if (rs == NS_FF)
+      rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
+      neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
+
+      if (rs == NS_FF || rs == NS_HH)
         {
           NEON_ENCODE (SINGLE, inst);
@@ -13917 +14350 @@
   else
     {
-      enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
-      neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
+      rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
+      neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
 
       switch (inst.instruction & 0x0fffffff)
@@ -13932 +14365 @@
         }
 
-      if (rs == NS_FI)
+      if (rs == NS_FI || rs == NS_HI)
         {
           NEON_ENCODE (SINGLE, inst);
@@ -13944 +14377 @@
     }
   do_vfp_cond_or_thumb ();
+
+  /* ARMv8.2 fp16 instruction.  */
+  if (rs == NS_HI || rs == NS_HH)
+    do_scalar_fp16_v82_encode ();
 }
 
@@ -14108 +14545 @@
       enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
       struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
+      int imm = inst.operands[2].imm;
+
+      constraint (imm < 0 || (unsigned)imm >= et.size,
+                  _("immediate out of range for shift"));
       NEON_ENCODE (IMMED, inst);
-      neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
+      neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
     }
   else
@@ -14140 +14581 @@
       enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
       struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
-
+      int imm = inst.operands[2].imm;
+
+      constraint (imm < 0 || (unsigned)imm >= et.size,
+                  _("immediate out of range for shift"));
       NEON_ENCODE (IMMED, inst);
-      neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
-                      inst.operands[2].imm);
+      neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
     }
   else
@@ -14335 +14778 @@
     {
       NEON_ENCODE (FLOAT, inst);
-      neon_three_same (neon_quad (rs), 0, -1);
+      neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
     }
   else
@@ -14450 +14893 @@
 neon_exchange_operands (void)
 {
-  void *scratch = alloca (sizeof (inst.operands[0]));
   if (inst.operands[1].present)
     {
+      void *scratch = xmalloc (sizeof (inst.operands[0]));
+
       /* Swap operands[1] and operands[2].  */
       memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
       inst.operands[1] = inst.operands[2];
       memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
+      free (scratch);
     }
   else
@@ -14496 +14941 @@
 do_neon_cmp (void)
 {
-  neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
+  neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
 }
 
@@ -14502 +14947 @@
 do_neon_cmp_inv (void)
 {
-  neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
+  neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
 }
 
@@ -14581 +15026 @@
       enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
       struct neon_type_el et = neon_check_type (3, rs,
-        N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
+        N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
       NEON_ENCODE (SCALAR, inst);
       neon_mul_mac (et, neon_quad (rs));
@@ -14630 +15075 @@
     do_neon_mac_maybe_scalar ();
   else
-    neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
+    neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
 }
 
@@ -14656 +15101 @@
 
 static void
+do_neon_qrdmlah (void)
+{
+  /* Check we're on the correct architecture.  */
+  if (!mark_feature_used (&fpu_neon_ext_armv8))
+    inst.error =
+      _("instruction form not available on this architecture.");
+  else if (!mark_feature_used (&fpu_neon_ext_v8_1))
+    {
+      as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
+      record_feature_use (&fpu_neon_ext_v8_1);
+    }
+
+  if (inst.operands[2].isscalar)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
+      NEON_ENCODE (SCALAR, inst);
+      neon_mul_mac (et, neon_quad (rs));
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
+      NEON_ENCODE (INTEGER, inst);
+      /* The U bit (rounding) comes from bit mask.  */
+      neon_three_same (neon_quad (rs), 0, et.size);
+    }
+}
+
+static void
 do_neon_fcmp_absolute (void)
 {
   enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
-  neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
+  struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
+                                            N_F_16_32 | N_KEY);
   /* Size field comes from bit mask.  */
-  neon_three_same (neon_quad (rs), 1, -1);
+  neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
 }
 
@@ -14675 +15153 @@
 {
   enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
-  neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
-  neon_three_same (neon_quad (rs), 0, -1);
+  struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
+                                            N_F_16_32 | N_KEY);
+  neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
 }
 
@@ -14692 +15171 @@
 
   rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
-  et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
+  et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
 
   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
@@ -14901 +15380 @@
   CVT_VAR (f32_u32, N_F32, N_U32, whole_reg,   "fultos", "fuitos", NULL)      \
   /* Half-precision conversions.  */                                          \
+  CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL)        \
+  CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL)        \
+  CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL)        \
+  CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL)        \
   CVT_VAR (f32_f16, N_F32, N_F16, whole_reg,   NULL,     NULL,     NULL)      \
   CVT_VAR (f16_f32, N_F16, N_F32, whole_reg,   NULL,     NULL,     NULL)      \
+  /* New VCVT instructions introduced by ARMv8.2 fp16 extension.              \
+     Compared with single/double precision variants, only the co-processor    \
+     field is different, so the encoding flow is reused here.  */             \
+  CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL)    \
+  CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL)    \
+  CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
+  CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
   /* VFP instructions.  */                                                    \
   CVT_VAR (f32_f64, N_F32, N_F64, N_VFP,       NULL,     "fcvtsd", NULL)      \
@@ -14977 +15467 @@
   const char *opname = 0;
 
-  if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
+  if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
+      || rs == NS_FHI || rs == NS_HFI)
     {
       /* Conversions with immediate bitshift.  */
@@ -15014 +15505 @@
   if (opname)
     do_vfp_nsyn_opcode (opname);
+
+  /* ARMv8.2 fp16 VCVT instruction.  */
+  if (flavour == neon_cvt_flavour_s32_f16
+      || flavour == neon_cvt_flavour_u32_f16
+      || flavour == neon_cvt_flavour_f16_u32
+      || flavour == neon_cvt_flavour_f16_s32)
+    do_scalar_fp16_v82_encode ();
 }
 
@@ -15019 +15517 @@
 do_vfp_nsyn_cvtz (void)
 {
-  enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
+  enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
   enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
   const char *enc[] =
@@ -15040 +15538 @@
   int rm;
 
+  /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
+     D register operands.  */
+  if (flavour == neon_cvt_flavour_s32_f64
+      || flavour == neon_cvt_flavour_u32_f64)
+    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
+                _(BAD_FPU));
+
+  if (flavour == neon_cvt_flavour_s32_f16
+      || flavour == neon_cvt_flavour_u32_f16)
+    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
+                _(BAD_FP16));
+
   set_it_insn_type (OUTSIDE_IT_INSN);
 
@@ -15049 +15559 @@
       break;
     case neon_cvt_flavour_s32_f32:
+      sz = 0;
+      op = 1;
+      break;
+    case neon_cvt_flavour_s32_f16:
       sz = 0;
       op = 1;
@@ -15060 +15574 @@
       op = 0;
       break;
+    case neon_cvt_flavour_u32_f16:
+      sz = 0;
+      op = 0;
+      break;
     default:
       first_error (_("invalid instruction shape"));
@@ -15078 +15596 @@
   encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
   inst.instruction |= sz << 8;
+
+  /* ARMv8.2 fp16 VCVT instruction.  */
+  if (flavour == neon_cvt_flavour_s32_f16
+      ||flavour == neon_cvt_flavour_u32_f16)
+    do_scalar_fp16_v82_encode ();
   inst.instruction |= op << 7;
   inst.instruction |= rm << 16;
@@ -15088 +15611 @@
 {
   enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
-    NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
+                                          NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
+                                          NS_FH, NS_HF, NS_FHI, NS_HFI,
+                                          NS_NULL);
   enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
+
+  if (flavour == neon_cvt_flavour_invalid)
+    return;
 
   /* PR11109: Handle round-to-zero for VCVT conversions.  */
   if (mode == neon_cvt_mode_z
       && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
-      && (flavour == neon_cvt_flavour_s32_f32
+      && (flavour == neon_cvt_flavour_s16_f16
+          || flavour == neon_cvt_flavour_u16_f16
+          || flavour == neon_cvt_flavour_s32_f32
           || flavour == neon_cvt_flavour_u32_f32
           || flavour == neon_cvt_flavour_s32_f64
@@ -15104 +15634 @@
     }
 
+  /* ARMv8.2 fp16 VCVT conversions.  */
+  if (mode == neon_cvt_mode_z
+      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
+      && (flavour == neon_cvt_flavour_s32_f16
+          || flavour == neon_cvt_flavour_u32_f16)
+      && (rs == NS_FH))
+    {
+      do_vfp_nsyn_cvtz ();
+      do_scalar_fp16_v82_encode ();
+      return;
+    }
+
   /* VFP rather than Neon conversions.  */
   if (flavour >= neon_cvt_flavour_first_fp)
@@ -15121 +15663 @@
       {
         unsigned immbits;
-        unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
+        unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
+                             0x0000100, 0x1000100, 0x0, 0x1000000};
 
         if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
@@ -15130 +15673 @@
         if (inst.operands[2].present && inst.operands[2].imm == 0)
           goto int_encode;
-       immbits = 32 - inst.operands[2].imm;
         NEON_ENCODE (IMMED, inst);
         if (flavour != neon_cvt_flavour_invalid)
@@ -15140 +15682 @@
         inst.instruction |= neon_quad (rs) << 6;
         inst.instruction |= 1 << 21;
-        inst.instruction |= immbits << 16;
+        if (flavour < neon_cvt_flavour_s16_f16)
+          {
+            inst.instruction |= 1 << 21;
+            immbits = 32 - inst.operands[2].imm;
+            inst.instruction |= immbits << 16;
+          }
+        else
+          {
+            inst.instruction |= 3 << 20;
+            immbits = 16 - inst.operands[2].imm;
+            inst.instruction |= immbits << 16;
+            inst.instruction &= ~(1 << 9);
+          }
 
         neon_dp_fixup (&inst);
@@ -15161 +15715 @@
           inst.instruction |= HI1 (inst.operands[1].reg) << 5;
           inst.instruction |= neon_quad (rs) << 6;
-          inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
+          inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
+                               || flavour == neon_cvt_flavour_u32_f32) << 7;
           inst.instruction |= mode << 8;
+          if (flavour == neon_cvt_flavour_u16_f16
+              || flavour == neon_cvt_flavour_s16_f16)
+            /* Mask off the original size bits and reencode them.  */
+            inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
+
           if (thumb_mode)
             inst.instruction |= 0xfc000000;
@@ -15172 +15732 @@
     int_encode:
           {
-            unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
+            unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
+                                  0x100, 0x180, 0x0, 0x080};
 
             NEON_ENCODE (INTEGER, inst);
@@ -15187 +15748 @@
             inst.instruction |= HI1 (inst.operands[1].reg) << 5;
             inst.instruction |= neon_quad (rs) << 6;
-            inst.instruction |= 2 << 18;
+            if (flavour >= neon_cvt_flavour_s16_f16
+                && flavour <= neon_cvt_flavour_f16_u16)
+              /* Half precision.  */
+              inst.instruction |= 1 << 18;
+            else
+              inst.instruction |= 2 << 18;
 
             neon_dp_fixup (&inst);
@@ -15288 +15854 @@
 do_neon_cvttb_1 (bfd_boolean t)
 {
-  enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
+  enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
+                                          NS_DF, NS_DH, NS_NULL);
 
   if (rs == NS_NULL)
@@ -15304 +15871 @@
   else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
     {
+      /* The VCVTB and VCVTT instructions with D-register operands
+         don't work for SP only targets.  */
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
+                  _(BAD_FPU));
+
       inst.error = NULL;
       do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
@@ -15309 +15881 @@
   else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
     {
+      /* The VCVTB and VCVTT instructions with D-register operands
+         don't work for SP only targets.  */
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
+                  _(BAD_FPU));
+
       inst.error = NULL;
       do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
@@ -15658 +16235 @@
 {
   enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
-    NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
-    NS_NULL);
+                                          NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR,
+                                          NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
+                                          NS_HR, NS_RH, NS_HI, NS_NULL);
   struct neon_type_el et;
   const char *ldconst = 0;
@@ -15837 +16415 @@
       break;
 
+    case NS_HI:
     case NS_FI:  /* case 10 (fconsts).  */
       ldconst = "fconsts";
@@ -15844 +16423 @@
           inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
           do_vfp_nsyn_opcode (ldconst);
+
+          /* ARMv8.2 fp16 vmov.f16 instruction.  */
+          if (rs == NS_HI)
+            do_scalar_fp16_v82_encode ();
         }
       else
@@ -15849 +16432 @@
       break;
 
+    case NS_RH:
     case NS_RF:  /* case 12 (fmrs).  */
       do_vfp_nsyn_opcode ("fmrs");
+      /* ARMv8.2 fp16 vmov.f16 instruction.  */
+      if (rs == NS_RH)
+        do_scalar_fp16_v82_encode ();
       break;
 
+    case NS_HR:
     case NS_FR:  /* case 13 (fmsr).  */
       do_vfp_nsyn_opcode ("fmsr");
+      /* ARMv8.2 fp16 vmov.f16 instruction.  */
+      if (rs == NS_HR)
+        do_scalar_fp16_v82_encode ();
       break;
 
@@ -15911 +16502 @@
 
 static void
+do_neon_movhf (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
+  constraint (rs != NS_HH, _("invalid suffix"));
+
+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
+              _(BAD_FPU));
+
+  do_vfp_sp_monadic ();
+
+  inst.is_neon = 1;
+  inst.instruction |= 0xf0000000;
+}
+
+static void
 do_neon_movl (void)
 {
@@ -15970 +16576 @@
   enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
   struct neon_type_el et = neon_check_type (2, rs,
-    N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
+    N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
   inst.instruction |= (et.type == NT_float) << 8;
   neon_two_same (neon_quad (rs), 1, et.size);
@@ -16077 +16683 @@
         inst.error = _("Use of PC here is UNPREDICTABLE");
       else if (warn_on_deprecated)
-        as_warn (_("Use of PC here is deprecated"));
+        as_tsktsk (_("Use of PC here is deprecated"));
     }
 
@@ -16086 +16692 @@
       else
         do_vfp_nsyn_opcode ("fsts");
+
+      /* ARMv8.2 vldr.16/vstr.16 instruction.  */
+      if (inst.vectype.el[0].size == 16)
+        do_scalar_fp16_v82_encode ();
     }
   else
@@ -16171 +16781 @@
 
 static int
-neon_alignment_bit (int size, int align, int *do_align, ...)
+neon_alignment_bit (int size, int align, int *do_alignment, ...)
 {
   va_list ap;
@@ -16178 +16788 @@
   if (!inst.operands[1].immisalign)
     {
-      *do_align = 0;
+      *do_alignment = 0;
       return SUCCESS;
     }
 
-  va_start (ap, do_align);
+  va_start (ap, do_alignment);
 
   do
@@ -16199 +16809 @@
 
   if (result == SUCCESS)
-    *do_align = 1;
+    *do_alignment = 1;
   else
     first_error (_("unsupported alignment for instruction"));
@@ -16210 +16820 @@
 {
   struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
-  int align_good, do_align = 0;
+  int align_good, do_alignment = 0;
   int logsize = neon_logbits (et.size);
   int align = inst.operands[1].imm >> 8;
@@ -16230 +16840 @@
     {
     case 0:  /* VLD1 / VST1.  */
-      align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
+      align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
                                        32, 32, -1);
       if (align_good == FAIL)
         return;
-      if (do_align)
+      if (do_alignment)
         {
           unsigned alignbits = 0;
@@ -16248 +16858 @@
 
     case 1:  /* VLD2 / VST2.  */
-      align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
-                                       32, 64, -1);
+      align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
+                      16, 32, 32, 64, -1);
       if (align_good == FAIL)
         return;
-      if (do_align)
+      if (do_alignment)
         inst.instruction |= 1 << 4;
       break;
@@ -16262 +16872 @@
 
     case 3:  /* VLD4 / VST4.  */
-      align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
+      align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
                                        16, 64, 32, 64, 32, 128, -1);
       if (align_good == FAIL)
         return;
-      if (do_align)
+      if (do_alignment)
         {
           unsigned alignbits = 0;
@@ -16297 +16907 @@
 {
   struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
-  int align_good, do_align = 0;
+  int align_good, do_alignment = 0;
 
   if (et.type == NT_invtype)
@@ -16307 +16917 @@
       gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
       align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
-                                       &do_align, 16, 16, 32, 32, -1);
+                                       &do_alignment, 16, 16, 32, 32, -1);
       if (align_good == FAIL)
         return;
@@ -16321 +16931 @@
     case 1:  /* VLD2.  */
       align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
-                                       &do_align, 8, 16, 16, 32, 32, 64, -1);
+                                       &do_alignment, 8, 16, 16, 32, 32, 64,
+                                       -1);
       if (align_good == FAIL)
         return;
@@ -16344 +16955 @@
       {
         int align = inst.operands[1].imm >> 8;
-        align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
+        align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
                                          16, 64, 32, 64, 32, 128, -1);
         if (align_good == FAIL)
@@ -16362 +16973 @@
     }
 
-  inst.instruction |= do_align << 4;
+  inst.instruction |= do_alignment << 4;
 }
 
@@ -16435 +17046 @@
 do_vfp_nsyn_fpv8 (enum neon_shape rs)
 {
+  /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
+     D register operands.  */
+  if (neon_shape_class[rs] == SC_DOUBLE)
+    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
+                _(BAD_FPU));
+
   NEON_ENCODE (FPV8, inst);
 
-  if (rs == NS_FFF)
-    do_vfp_sp_dyadic ();
+  if (rs == NS_FFF || rs == NS_HHH)
+    {
+      do_vfp_sp_dyadic ();
+
+      /* ARMv8.2 fp16 instruction.  */
+      if (rs == NS_HHH)
+        do_scalar_fp16_v82_encode ();
+    }
   else
     do_vfp_dp_rd_rn_rm ();
@@ -16468 +17091 @@
     return;
 
-  neon_dyadic_misc (NT_untyped, N_F32, 0);
+  neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
 }
 
@@ -16474 +17097 @@
 do_vrint_1 (enum neon_cvt_mode mode)
 {
-  enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
+  enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
   struct neon_type_el et;
 
@@ -16480 +17103 @@
     return;
 
-  et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+  /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
+     D register operands.  */
+  if (neon_shape_class[rs] == SC_DOUBLE)
+    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
+                _(BAD_FPU));
+
+  et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
+                        | N_VFP);
   if (et.type != NT_invtype)
     {
@@ -16489 +17119 @@
 
       NEON_ENCODE (FPV8, inst);
-      if (rs == NS_FF)
+      if (rs == NS_FF || rs == NS_HH)
         do_vfp_sp_monadic ();
       else
@@ -16508 +17138 @@
       inst.instruction |= (rs == NS_DD) << 8;
       do_vfp_cond_or_thumb ();
+
+      /* ARMv8.2 fp16 vrint instruction.  */
+      if (rs == NS_HH)
+      do_scalar_fp16_v82_encode ();
     }
   else
@@ -16513 +17147 @@
       /* Neon encodings (or something broken...).  */
       inst.error = NULL;
-      et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
+      et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
 
       if (et.type == NT_invtype)
@@ -16529 +17163 @@
       inst.instruction |= HI1 (inst.operands[1].reg) << 5;
       inst.instruction |= neon_quad (rs) << 6;
+      /* Mask off the original size bits and reencode them.  */
+      inst.instruction = ((inst.instruction & 0xfff3ffff)
+                          | neon_logbits (et.size) << 18);
+
       switch (mode)
         {
@@ -17093 +17731 @@
 
       if (warn_on_deprecated && unified_syntax)
-        as_warn (_("conditional infixes are deprecated in unified syntax"));
+        as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
       affix = base + (opcode->tag - OT_odd_infix_0);
       cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
@@ -17179 +17817 @@
           && (opcode->tag == OT_cinfix3
               || opcode->tag == OT_cinfix3_deprecated))
-        as_warn (_("conditional infixes are deprecated in unified syntax"));
+        as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
 
       inst.cond = cond->value;
@@ -17336 +17974 @@
             {
               if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
-                  && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
+                  && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
                 {
                   /* Automatically generate the IT instruction.  */
@@ -17509 +18147 @@
       if (inst.instruction >= 0x10000)
         {
-          as_warn (_("IT blocks containing 32-bit Thumb instructions are "
+          as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
                      "deprecated in ARMv8"));
           now_it.warn_deprecated = TRUE;
@@ -17521 +18159 @@
               if ((inst.instruction & p->mask) == p->pattern)
                 {
-                  as_warn (_("IT blocks containing 16-bit Thumb instructions "
+                  as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
                              "of the following class are deprecated in ARMv8: "
                              "%s"), p->description);
@@ -17534 +18172 @@
       if (now_it.block_length > 1)
         {
-          as_warn (_("IT blocks containing more than one conditional "
+          as_tsktsk (_("IT blocks containing more than one conditional "
                      "instruction are deprecated in ARMv8"));
           now_it.warn_deprecated = TRUE;
@@ -17566 +18204 @@
 
   return now_it.state != OUTSIDE_IT_BLOCK;
+}
+
+/* Whether OPCODE only has T32 encoding.  Since this function is only used by
+   t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
+   here, hence the "known" in the function name.  */
+
+static bfd_boolean
+known_t32_only_insn (const struct asm_opcode *opcode)
+{
+  /* Original Thumb-1 wide instruction.  */
+  if (opcode->tencode == do_t_blx
+      || opcode->tencode == do_t_branch23
+      || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
+      || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
+    return TRUE;
+
+  /* Wide-only instruction added to ARMv8-M Baseline.  */
+  if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
+      || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
+      || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
+      || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
+    return TRUE;
+
+  return FALSE;
+}
+
+/* Whether wide instruction variant can be used if available for a valid OPCODE
+   in ARCH.  */
+
+static bfd_boolean
+t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
+{
+  if (known_t32_only_insn (opcode))
+    return TRUE;
+
+  /* Instruction with narrow and wide encoding added to ARMv8-M.  Availability
+     of variant T3 of B.W is checked in do_t_branch.  */
+  if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
+      && opcode->tencode == do_t_branch)
+    return TRUE;
+
+  /* Wide instruction variants of all instructions with narrow *and* wide
+     variants become available with ARMv6t2.  Other opcodes are either
+     narrow-only or wide-only and are thus available if OPCODE is valid.  */
+  if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
+    return TRUE;
+
+  /* OPCODE with narrow only instruction variant or wide variant not
+     available.  */
+  return FALSE;
 }
 
@@ -17598 +18286 @@
 
   if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
-    as_warn (_("s suffix on comparison instruction is deprecated"));
+    as_tsktsk (_("s suffix on comparison instruction is deprecated"));
 
   /* The value which unconditional instructions should have in place of the
@@ -17617 +18305 @@
               && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
         {
-          as_bad (_("selected processor does not support Thumb mode `%s'"), str);
+          as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
           return;
         }
@@ -17627 +18315 @@
         }
 
-      if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
-        {
-          if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
-              && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
-                   || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
+      /* Two things are addressed here:
+         1) Implicit require narrow instructions on Thumb-1.
+            This avoids relaxation accidentally introducing Thumb-2
+            instructions.
+         2) Reject wide instructions in non Thumb-2 cores.
+
+         Only instructions with narrow and wide variants need to be handled
+         but selecting all non wide-only instructions is easier.  */
+      if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
+          && !t32_insn_ok (variant, opcode))
+        {
+          if (inst.size_req == 0)
+            inst.size_req = 2;
+          else if (inst.size_req == 4)
             {
-              /* Two things are addressed here.
-                 1) Implicit require narrow instructions on Thumb-1.
-                    This avoids relaxation accidentally introducing Thumb-2
-                     instructions.
-                 2) Reject wide instructions in non Thumb-2 cores.  */
-              if (inst.size_req == 0)
-                inst.size_req = 2;
-              else if (inst.size_req == 4)
-                {
-                  as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
-                  return;
-                }
+              if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
+                as_bad (_("selected processor does not support 32bit wide "
+                          "variant of instruction `%s'"), str);
+              else
+                as_bad (_("selected processor does not support `%s' in "
+                          "Thumb-2 mode"), str);
+              return;
             }
         }
@@ -17679 +18371 @@
                               *opcode->tvariant);
       /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
-         set those bits when Thumb-2 32-bit instructions are seen.  ie.
-         anything other than bl/blx and v6-M instructions.
-         This is overly pessimistic for relaxable instructions.  */
-      if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
-           || inst.relax)
-          && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
-               || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
+         set those bits when Thumb-2 32-bit instructions are seen.  The impact
+         of relaxable instructions will be considered later after we finish all
+         relaxation.  */
+      if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
+        variant = arm_arch_none;
+      else
+        variant = cpu_variant;
+      if (inst.size == 4 && !t32_insn_ok (variant, opcode))
         ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
                                 arm_ext_v6t2);
@@ -17708 +18401 @@
                ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
         {
-          as_bad (_("selected processor does not support ARM mode `%s'"), str);
+          as_bad (_("selected processor does not support `%s' in ARM mode"), str);
           return;
         }
@@ -17719 +18412 @@
       inst.instruction = opcode->avalue;
       if (opcode->tag == OT_unconditionalF)
-        inst.instruction |= 0xF << 28;
+        inst.instruction |= 0xFU << 28;
       else
         inst.instruction |= inst.cond << 28;
@@ -18105 +18798 @@
   {"epsr",        6 }, {"EPSR",         6 },
   {"iepsr",       7 }, {"IEPSR",        7 },
-  {"msp",         8 }, {"MSP",          8 },
-  {"psp",         9 }, {"PSP",          9 },
+  {"msp",         8 }, {"MSP",          8 }, {"msp_s",     8 }, {"MSP_S",     8 },
+  {"psp",         9 }, {"PSP",          9 }, {"psp_s",     9 }, {"PSP_S",     9 },
   {"primask",     16}, {"PRIMASK",      16},
   {"basepri",     17}, {"BASEPRI",      17},
@@ -18112 +18805 @@
   {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility.  */
   {"faultmask",   19}, {"FAULTMASK",    19},
-  {"control",     20}, {"CONTROL",      20}
+  {"control",     20}, {"CONTROL",      20},
+  {"msp_ns",    0x88}, {"MSP_NS",     0x88},
+  {"psp_ns",    0x89}, {"PSP_NS",     0x89}
 };
 
@@ -18172 +18867 @@
 
 #define UL_BARRIER(L,U,CODE,FEAT) \
-  { L, CODE, ARM_FEATURE (FEAT, 0) }, \
-  { U, CODE, ARM_FEATURE (FEAT, 0) }
+  { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
+  { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
 
 static struct asm_barrier_opt barrier_opt_names[] =
@@ -18409 +19104 @@
 
  tCE("mov",     1a00000, _mov,     2, (RR, SH),      mov,  t_mov_cmp),
- tC3("movs",    1b00000, _movs,    2, (RR, SH),      mov,  t_mov_cmp),
+ tC3("movs",    1b00000, _movs,    2, (RR, SHG),     mov,  t_mov_cmp),
  tCE("mvn",     1e00000, _mvn,     2, (RR, SH),      mov,  t_mvn_tst),
  tC3("mvns",    1f00000, _mvns,    2, (RR, SH),      mov,  t_mvn_tst),
@@ -18653 +19348 @@
 
 #undef  THUMB_VARIANT
-#define THUMB_VARIANT  & arm_ext_v6t2
+#define THUMB_VARIANT  & arm_ext_v6t2_v8m
 
  TCE("ldrex",   1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR),        ldrex, t_ldrex),
  TCE("strex",   1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
                                       strex,  t_strex),
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT  & arm_ext_v6t2
+
  TUF("mcrr2",   c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
  TUF("mrrc2",   c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
@@ -18685 +19383 @@
  TUF("srsdb",   9400500, e800c000, 2, (oRRw, I31w),                srs,  srs),
  TUF("srsfd",   9400500, e800c000, 2, (oRRw, I31w),                srs,  srs),
+ TUF("cps",     1020000, f3af8100, 1, (I31b),                     imm0, t_cps),
 
 /*  ARM V6 not included in V7M (eg. integer SIMD).  */
 #undef  THUMB_VARIANT
 #define THUMB_VARIANT  & arm_ext_v6_dsp
- TUF("cps",     1020000, f3af8100, 1, (I31b),                     imm0, t_cps),
  TCE("pkhbt",   6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll),   pkhbt, t_pkhbt),
  TCE("pkhtb",   6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar),   pkhtb, t_pkhtb),
@@ -18803 +19501 @@
 
 #undef  THUMB_VARIANT
-#define THUMB_VARIANT  & arm_ext_v6t2
+#define THUMB_VARIANT  & arm_ext_v6t2_v8m
  TCE("ldrexb",  1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
      rd_rn,  rd_rn),
@@ -18829 +19527 @@
  TCE("eret",    160006e, f3de8f00, 0, (), noargs, noargs),
 
+#undef  ARM_VARIANT
+#define ARM_VARIANT    & arm_ext_pan
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT  & arm_ext_pan
+
+ TUF("setpan",  1100000, b610, 1, (I7), setpan, t_setpan),
+
 #undef  ARM_VARIANT
 #define ARM_VARIANT    & arm_ext_v6t2
@@ -18840 +19545 @@
 
  TCE("mls",     0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
- TCE("movw",    3000000, f2400000, 2, (RRnpc, HALF),                mov16, t_mov16),
- TCE("movt",    3400000, f2c00000, 2, (RRnpc, HALF),                mov16, t_mov16),
  TCE("rbit",    6ff0f30, fa90f0a0, 2, (RR, RR),                     rd_rm, t_rbit),
 
@@ -18848 +19551 @@
  TC3("ldrsbt",  03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
  TC3("strht",   02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
+
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT  & arm_ext_v6t2_v8m
+ TCE("movw",    3000000, f2400000, 2, (RRnpc, HALF),                mov16, t_mov16),
+ TCE("movt",    3400000, f2c00000, 2, (RRnpc, HALF),                mov16, t_mov16),
 
  /* Thumb-only instructions.  */
@@ -18860 +19568 @@
 #undef  ARM_VARIANT
 #define ARM_VARIANT  & arm_ext_v1
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT  & arm_ext_v6t2
 
  TUE("it",        bf08,        bf08,     1, (COND),   it,    t_it),
@@ -18929 +19639 @@
 #undef  ARM_VARIANT
 #define ARM_VARIANT   & arm_ext_v8
+
+/* Instructions shared between armv8-a and armv8-m.  */
 #undef  THUMB_VARIANT
-#define THUMB_VARIANT & arm_ext_v8
-
- tCE("sevl",    320f005, _sevl,    0, (),               noargs, t_hint),
- TUE("hlt",     1000070, ba80,     1, (oIffffb),        bkpt,   t_hlt),
- TCE("ldaex",   1900e9f, e8d00fef, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
- TCE("ldaexd",  1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
-                                                        ldrexd, t_ldrexd),
- TCE("ldaexb",  1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb),   rd_rn,  rd_rn),
- TCE("ldaexh",  1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
- TCE("stlex",   1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
-                                                        stlex,  t_stlex),
- TCE("stlexd",  1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
-                                                        strexd, t_strexd),
- TCE("stlexb",  1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
-                                                        stlex, t_stlex),
- TCE("stlexh",  1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
-                                                        stlex, t_stlex),
+#define THUMB_VARIANT & arm_ext_atomics
+
  TCE("lda",     1900c9f, e8d00faf, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
  TCE("ldab",    1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
@@ -18953 +19650 @@
  TCE("stlb",    1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
  TCE("stlh",    1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb),  rm_rn,  rd_rn),
-
+ TCE("ldaex",   1900e9f, e8d00fef, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
+ TCE("ldaexb",  1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb),   rd_rn,  rd_rn),
+ TCE("ldaexh",  1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb),  rd_rn,  rd_rn),
+ TCE("stlex",   1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
+                                                        stlex,  t_stlex),
+ TCE("stlexb",  1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
+                                                        stlex, t_stlex),
+ TCE("stlexh",  1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
+                                                        stlex, t_stlex),
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8
+
+ tCE("sevl",    320f005, _sevl,    0, (),               noargs, t_hint),
+ TUE("hlt",     1000070, ba80,     1, (oIffffb),        bkpt,   t_hlt),
+ TCE("ldaexd",  1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
+                                                        ldrexd, t_ldrexd),
+ TCE("stlexd",  1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
+                                                        strexd, t_strexd),
  /* ARMv8 T32 only.  */
 #undef  ARM_VARIANT
@@ -18963 +19677 @@
   /* FP for ARMv8.  */
 #undef  ARM_VARIANT
-#define ARM_VARIANT   & fpu_vfp_ext_armv8
+#define ARM_VARIANT   & fpu_vfp_ext_armv8xd
 #undef  THUMB_VARIANT
-#define THUMB_VARIANT & fpu_vfp_ext_armv8
+#define THUMB_VARIANT & fpu_vfp_ext_armv8xd
 
   nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD),           vsel),
@@ -19016 +19730 @@
   TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
   TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
+
+ /* ARMv8.2 RAS extension.  */
+#undef  ARM_VARIANT
+#define ARM_VARIANT   & arm_ext_ras
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_ras
+ TUE ("esb", 320f010, f3af8010, 0, (), noargs,  noargs),
 
 #undef  ARM_VARIANT
@@ -19632 +20353 @@
  NCE(vmov,      0,       1, (VMOV), neon_mov),
  NCE(vmovq,     0,       1, (VMOV), neon_mov),
+
+#undef  ARM_VARIANT
+#define ARM_VARIANT    & arm_ext_fp16
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT  & arm_ext_fp16
+ /* New instructions added from v8.2, allowing the extraction and insertion of
+    the upper 16 bits of a 32-bit vector register.  */
+ NCE (vmovx,     eb00a40,       2, (RVS, RVS), neon_movhf),
+ NCE (vins,      eb00ac0,       2, (RVS, RVS), neon_movhf),
 
 #undef  THUMB_VARIANT
@@ -19682 +20412 @@
  NUF(vbif,      1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
  NUF(vbifq,     1300110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
-  /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32.  */
+  /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32.  */
  nUF(vabd,      _vabd,    3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
  nUF(vabdq,     _vabd,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
@@ -19734 +20464 @@
  NUF(vrsqrts,   0200f10,  3, (RNDQ, oRNDQ, RNDQ), neon_step),
  NUF(vrsqrtsq,  0200f10,  3, (RNQ,  oRNQ,  RNQ),  neon_step),
+ /* ARM v8.1 extension.  */
+ nUF (vqrdmlah,  _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
+ nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qrdmlah),
+ nUF (vqrdmlsh,  _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
+ nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qrdmlah),
 
   /* Two address, int/float. Types S8 S16 S32 F32.  */
@@ -19840 +20575 @@
  NUF(vpaddl,    1b00200, 2, (RNDQ, RNDQ),     neon_pair_long),
  NUF(vpaddlq,   1b00200, 2, (RNQ,  RNQ),      neon_pair_long),
-  /* Reciprocal estimates. Types U32 F32.  */
+  /* Reciprocal estimates.  Types U32 F16 F32.  */
  NUF(vrecpe,    1b30400, 2, (RNDQ, RNDQ),     neon_recip_est),
  NUF(vrecpeq,   1b30400, 2, (RNQ,  RNQ),      neon_recip_est),
@@ -20246 +20981 @@
  cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
  cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
+
+ /* ARMv8-M instructions.  */
+#undef  ARM_VARIANT
+#define ARM_VARIANT NULL
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8m
+ TUE("sg", 0, e97fe97f, 0, (), 0, noargs),
+ TUE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx),
+ TUE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx),
+ TUE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt),
+ TUE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt),
+ TUE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt),
+ TUE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt),
+
+ /* FP for ARMv8-M Mainline.  Enabled for ARMv8-M Mainline because the
+    instructions behave as nop if no VFP is present.  */
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8m_main
+ TUEc("vlldm",  0,       ec300a00, 1, (RRnpc),  rn),
+ TUEc("vlstm",  0,       ec200a00, 1, (RRnpc),  rn),
 };
 #undef ARM_VARIANT
@@ -20519 +21274 @@
   fixp->fx_line = fragp->fr_line;
   fragp->fr_fix += fragp->fr_var;
+
+  /* Set whether we use thumb-2 ISA based on final relaxation results.  */
+  if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
+      && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
+    ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
 }
 
@@ -20796 +21556 @@
 
       align = bfd_get_section_alignment (stdoutput, segment);
-      size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
+      size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
     }
 #endif
@@ -20809 +21569 @@
 arm_handle_align (fragS * fragP)
 {
-  static char const arm_noop[2][2][4] =
+  static unsigned char const arm_noop[2][2][4] =
     {
       {  /* ARMv1 */
@@ -20820 +21580 @@
       },
     };
-  static char const thumb_noop[2][2][2] =
+  static unsigned char const thumb_noop[2][2][2] =
     {
       {  /* Thumb-1 */
@@ -20831 +21591 @@
       }
     };
-  static char const wide_thumb_noop[2][4] =
+  static unsigned char const wide_thumb_noop[2][4] =
     {  /* Wide Thumb-2 */
       {0xaf, 0xf3, 0x00, 0x80},  /* LE */
@@ -20839 +21599 @@
   unsigned bytes, fix, noop_size;
   char * p;
-  const char * noop;
-  const char *narrow_noop = NULL;
+  const unsigned char * noop;
+  const unsigned char *narrow_noop = NULL;
 #ifdef OBJ_ELF
   enum mstate state;
@@ -20971 +21731 @@
 arm_init_frag (fragS * fragP, int max_chars)
 {
+  int frag_thumb_mode;
+
   /* If the current ARM vs THUMB mode has not already
      been recorded into this frag then do so now.  */
   if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
-    {
-      fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
-
-      /* Record a mapping symbol for alignment frags.  We will delete this
-         later if the alignment ends up empty.  */
-      switch (fragP->fr_type)
-        {
-          case rs_align:
-          case rs_align_test:
-          case rs_fill:
-            mapping_state_2 (MAP_DATA, max_chars);
-            break;
-          case rs_align_code:
-            mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
-            break;
-          default:
-            break;
-        }
+    fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
+
+  frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
+
+  /* Record a mapping symbol for alignment frags.  We will delete this
+     later if the alignment ends up empty.  */
+  switch (fragP->fr_type)
+    {
+    case rs_align:
+    case rs_align_test:
+    case rs_fill:
+      mapping_state_2 (MAP_DATA, max_chars);
+      break;
+    case rs_align_code:
+      mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
+      break;
+    default:
+      break;
     }
 }
@@ -21050 +21812 @@
       unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
       if (unwind.opcodes)
-        unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
-                                                     unwind.opcode_alloc);
+        unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
+                                     unwind.opcode_alloc);
       else
-        unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
+        unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
     }
   while (length > 0)
@@ -21157 +21919 @@
   const char * prefix_once;
   const char * group_name;
-  size_t prefix_len;
-  size_t text_len;
   char * sec_name;
-  size_t sec_name_len;
   int type;
   int flags;
@@ -21189 +21948 @@
     }
 
-  prefix_len = strlen (prefix);
-  text_len = strlen (text_name);
-  sec_name_len = prefix_len + text_len;
-  sec_name = (char *) xmalloc (sec_name_len + 1);
-  memcpy (sec_name, prefix, prefix_len);
-  memcpy (sec_name + prefix_len, text_name, text_len);
-  sec_name[prefix_len + text_len] = '\0';
+  sec_name = concat (prefix, text_name, (char *) NULL);
 
   flags = SHF_ALLOC;
@@ -21565 +22318 @@
       return base;
     }
+}
+
+static bfd_boolean flag_warn_syms = TRUE;
+
+bfd_boolean
+arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
+{
+  /* PR 18347 - Warn if the user attempts to create a symbol with the same
+     name as an ARM instruction.  Whilst strictly speaking it is allowed, it
+     does mean that the resulting code might be very confusing to the reader.
+     Also this warning can be triggered if the user omits an operand before
+     an immediate address, eg:
+
+       LDR =foo
+
+     GAS treats this as an assignment of the value of the symbol foo to a
+     symbol LDR, and so (without this code) it will not issue any kind of
+     warning or error message.
+
+     Note - ARM instructions are case-insensitive but the strings in the hash
+     table are all stored in lower case, so we must first ensure that name is
+     lower case too.  */
+  if (flag_warn_syms && arm_ops_hsh)
+    {
+      char * nbuf = strdup (name);
+      char * p;
+
+      for (p = nbuf; *p; p++)
+        *p = TOLOWER (*p);
+      if (hash_find (arm_ops_hsh, nbuf) != NULL)
+        {
+          static struct hash_control * already_warned = NULL;
+
+          if (already_warned == NULL)
+            already_warned = hash_new ();
+          /* Only warn about the symbol once.  To keep the code
+             simple we let hash_insert do the lookup for us.  */
+          if (hash_insert (already_warned, name, NULL) == NULL)
+            as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
+        }
+      else
+        free (nbuf);
+    }
+
+  return FALSE;
 }
 
@@ -22592 +23390 @@
       if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
         {
-          if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
+          if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
             as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
           else if ((value & ~0x1ffffff)
@@ -22691 +23489 @@
     case BFD_RELOC_ARM_CP_OFF_IMM:
     case BFD_RELOC_ARM_T32_CP_OFF_IMM:
-      if (value < -1023 || value > 1023 || (value & 3))
+      if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
+        newval = md_chars_to_number (buf, INSN_SIZE);
+      else
+        newval = get_thumb32_insn (buf);
+      if ((newval & 0x0f200f00) == 0x0d000900)
+        {
+          /* This is a fp16 vstr/vldr.  The immediate offset in the mnemonic
+             has permitted values that are multiples of 2, in the range 0
+             to 510.  */
+          if (value < -510 || value > 510 || (value & 1))
+            as_bad_where (fixP->fx_file, fixP->fx_line,
+                          _("co-processor offset out of range"));
+        }
+      else if (value < -1023 || value > 1023 || (value & 3))
         as_bad_where (fixP->fx_file, fixP->fx_line,
                       _("co-processor offset out of range"));
@@ -22708 +23519 @@
         {
           newval &= 0xff7fff00;
+          if ((newval & 0x0f200f00) == 0x0d000900)
+            {
+              /* This is a fp16 vstr/vldr.
+
+                 It requires the immediate offset in the instruction is shifted
+                 left by 1 to be a half-word offset.
+
+                 Here, left shift by 1 first, and later right shift by 2
+                 should get the right offset.  */
+              value <<= 1;
+            }
           newval |= (value >> 2) | (sign ? INDEX_UP : 0);
         }
@@ -22833 +23655 @@
         if (rd == REG_SP)
           {
-            if (value & ~0x1fc)
+            if (value & ~0x1fc)
               as_bad_where (fixP->fx_file, fixP->fx_line,
                             _("invalid immediate for stack address calculation"));
@@ -22841 +23663 @@
         else if (rs == REG_PC || rs == REG_SP)
           {
+            /* PR gas/18541.  If the addition is for a defined symbol
+               within range of an ADR instruction then accept it.  */
+            if (subtract
+                && value == 4
+                && fixP->fx_addsy != NULL)
+              {
+                subtract = 0;
+
+                if (! S_IS_DEFINED (fixP->fx_addsy)
+                    || S_GET_SEGMENT (fixP->fx_addsy) != seg
+                    || S_IS_WEAK (fixP->fx_addsy))
+                  {
+                    as_bad_where (fixP->fx_file, fixP->fx_line,
+                                  _("address calculation needs a strongly defined nearby symbol"));
+                  }
+                else
+                  {
+                    offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
+
+                    /* Round up to the next 4-byte boundary.  */
+                    if (v & 3)
+                      v = (v + 3) & ~ 3;
+                    else
+                      v += 4;
+                    v = S_GET_VALUE (fixP->fx_addsy) - v;
+
+                    if (v & ~0x3fc)
+                      {
+                        as_bad_where (fixP->fx_file, fixP->fx_line,
+                                      _("symbol too far away"));
+                      }
+                    else
+                      {
+                        fixP->fx_done = 1;
+                        value = v;
+                      }
+                  }
+              }
+
             if (subtract || value & ~0x3fc)
               as_bad_where (fixP->fx_file, fixP->fx_line,
                             _("invalid immediate for address calculation (value = 0x%08lX)"),
-                            (unsigned long) value);
+                            (unsigned long) (subtract ? - value : value));
             newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
             newval |= rd << 8;
@@ -22942 +23803 @@
       return;
 
+   case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
+   case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
+   case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
+   case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
+      gas_assert (!fixP->fx_done);
+      {
+        bfd_vma insn;
+        bfd_boolean is_mov;
+        bfd_vma encoded_addend = value;
+
+        /* Check that addend can be encoded in instruction.  */
+        if (!seg->use_rela_p && (value < 0 || value > 255))
+          as_bad_where (fixP->fx_file, fixP->fx_line,
+                        _("the offset 0x%08lX is not representable"),
+                        (unsigned long) encoded_addend);
+
+        /* Extract the instruction.  */
+        insn = md_chars_to_number (buf, THUMB_SIZE);
+        is_mov = (insn & 0xf800) == 0x2000;
+
+        /* Encode insn.  */
+        if (is_mov)
+          {
+            if (!seg->use_rela_p)
+              insn |= encoded_addend;
+          }
+        else
+          {
+            int rd, rs;
+
+            /* Extract the instruction.  */
+             /* Encoding is the following
+                0x8000  SUB
+                0x00F0  Rd
+                0x000F  Rs
+             */
+             /* The following conditions must be true :
+                - ADD
+                - Rd == Rs
+                - Rd <= 7
+             */
+            rd = (insn >> 4) & 0xf;
+            rs = insn & 0xf;
+            if ((insn & 0x8000) || (rd != rs) || rd > 7)
+              as_bad_where (fixP->fx_file, fixP->fx_line,
+                        _("Unable to process relocation for thumb opcode: %lx"),
+                        (unsigned long) insn);
+
+            /* Encode as ADD immediate8 thumb 1 code.  */
+            insn = 0x3000 | (rd << 8);
+
+            /* Place the encoded addend into the first 8 bits of the
+               instruction.  */
+            if (!seg->use_rela_p)
+              insn |= encoded_addend;
+          }
+
+        /* Update the instruction.  */
+        md_number_to_chars (buf, insn, THUMB_SIZE);
+      }
+      break;
+
    case BFD_RELOC_ARM_ALU_PC_G0_NC:
    case BFD_RELOC_ARM_ALU_PC_G0:
@@ -23132 +24055 @@
   bfd_reloc_code_real_type code;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
-
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc = XNEW (arelent);
+
+  reloc->sym_ptr_ptr = XNEW (asymbol *);
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
@@ -23247 +24170 @@
     case BFD_RELOC_ARM_PREL31:
     case BFD_RELOC_ARM_TARGET2:
-    case BFD_RELOC_ARM_TLS_LE32:
     case BFD_RELOC_ARM_TLS_LDO32:
     case BFD_RELOC_ARM_PCREL_CALL:
@@ -23280 +24202 @@
     case BFD_RELOC_ARM_LDC_SB_G2:
     case BFD_RELOC_ARM_V4BX:
+    case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
+    case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
+    case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
+    case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
       code = fixp->fx_r_type;
       break;
@@ -23285 +24211 @@
     case BFD_RELOC_ARM_TLS_GOTDESC:
     case BFD_RELOC_ARM_TLS_GD32:
+    case BFD_RELOC_ARM_TLS_LE32:
     case BFD_RELOC_ARM_TLS_IE32:
     case BFD_RELOC_ARM_TLS_LDM32:
@@ -23328 +24255 @@
     default:
       {
-        char * type;
+        const char * type;
 
         switch (fixp->fx_r_type)
@@ -23581 +24508 @@
     return FALSE;
 
+  /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
+     offsets, so keep these symbols.  */
+  if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
+      && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
+    return FALSE;
+
   return TRUE;
 }
@@ -23586 +24519 @@
 
 #ifdef OBJ_ELF
-
 const char *
 elf32_arm_target_format (void)
@@ -23772 +24704 @@
                  otherwise tag label as .code 16.  */
               if (THUMB_IS_FUNC (sym))
-                elf_sym->internal_elf_sym.st_target_internal
-                  = ST_BRANCH_TO_THUMB;
+                ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
+                                         ST_BRANCH_TO_THUMB);
               else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
                 elf_sym->internal_elf_sym.st_info =
@@ -23911 +24843 @@
       selected_cpu = cpu_default;
     }
+  else if (no_cpu_selected ())
+    selected_cpu = cpu_default;
 #else
   if (mcpu_cpu_opt)
@@ -24058 +24992 @@
 
               -m[no-]warn-deprecated     Warn about deprecated features
+              -m[no-]warn-syms           Warn when symbols match instructions
 
       For now we will also provide support for:
@@ -24126 +25061 @@
 };
 
+
 size_t md_longopts_size = sizeof (md_longopts);
 
 struct arm_option_table
 {
-  char *option;         /* Option name to match.  */
-  char *help;           /* Help information.  */
+  const char *option;           /* Option name to match.  */
+  const char *help;             /* Help information.  */
   int  *var;            /* Variable to change.  */
   int   value;          /* What to change it to.  */
-  char *deprecated;     /* If non-null, print this message.  */
+  const char *deprecated;       /* If non-null, print this message.  */
 };
 
@@ -24160 +25096 @@
   {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
    &warn_on_deprecated, 0, NULL},
+  {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
+  {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
   {NULL, NULL, NULL, 0, NULL}
 };
@@ -24165 +25103 @@
 struct arm_legacy_option_table
 {
-  char *option;                         /* Option name to match.  */
+  const char *option;                           /* Option name to match.  */
   const arm_feature_set **var;          /* Variable to change.  */
   const arm_feature_set value;          /* What to change it to.  */
-  char *deprecated;                     /* If non-null, print this message.  */
+  const char *deprecated;                       /* If non-null, print this message.  */
 };
 
@@ -24286 +25224 @@
 struct arm_cpu_option_table
 {
-  char *name;
+  const char *name;
   size_t name_len;
   const arm_feature_set value;
@@ -24386 +25324 @@
   ARM_CPU_OPT ("arm1156t2-s",   ARM_ARCH_V6T2,   FPU_NONE,        NULL),
   ARM_CPU_OPT ("arm1156t2f-s",  ARM_ARCH_V6T2,   FPU_ARCH_VFP_V2, NULL),
-  ARM_CPU_OPT ("arm1176jz-s",   ARM_ARCH_V6ZK,   FPU_NONE,        NULL),
-  ARM_CPU_OPT ("arm1176jzf-s",  ARM_ARCH_V6ZK,   FPU_ARCH_VFP_V2, NULL),
+  ARM_CPU_OPT ("arm1176jz-s",   ARM_ARCH_V6KZ,   FPU_NONE,        NULL),
+  ARM_CPU_OPT ("arm1176jzf-s",  ARM_ARCH_V6KZ,   FPU_ARCH_VFP_V2, NULL),
   ARM_CPU_OPT ("cortex-a5",     ARM_ARCH_V7A_MP_SEC,
                                                  FPU_NONE,        "Cortex-A5"),
@@ -24393 +25331 @@
                                                                   "Cortex-A7"),
   ARM_CPU_OPT ("cortex-a8",     ARM_ARCH_V7A_SEC,
-                                                 ARM_FEATURE (0, FPU_VFP_V3
+                                                 ARM_FEATURE_COPROC (FPU_VFP_V3
                                                         | FPU_NEON_EXT_V1),
                                                                   "Cortex-A8"),
   ARM_CPU_OPT ("cortex-a9",     ARM_ARCH_V7A_MP_SEC,
-                                                 ARM_FEATURE (0, FPU_VFP_V3
+                                                 ARM_FEATURE_COPROC (FPU_VFP_V3
                                                         | FPU_NEON_EXT_V1),
                                                                   "Cortex-A9"),
@@ -24406 +25344 @@
   ARM_CPU_OPT ("cortex-a17",    ARM_ARCH_V7VE,   FPU_ARCH_NEON_VFP_V4,
                                                                   "Cortex-A17"),
+  ARM_CPU_OPT ("cortex-a32",    ARM_ARCH_V8A,    FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+                                                                  "Cortex-A32"),
+  ARM_CPU_OPT ("cortex-a35",    ARM_ARCH_V8A,    FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+                                                                  "Cortex-A35"),
   ARM_CPU_OPT ("cortex-a53",    ARM_ARCH_V8A,    FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
                                                                   "Cortex-A53"),
   ARM_CPU_OPT ("cortex-a57",    ARM_ARCH_V8A,    FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
                                                                   "Cortex-A57"),
+  ARM_CPU_OPT ("cortex-a72",    ARM_ARCH_V8A,    FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+                                                                  "Cortex-A72"),
+  ARM_CPU_OPT ("cortex-a73",    ARM_ARCH_V8A,    FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+                                                                  "Cortex-A73"),
   ARM_CPU_OPT ("cortex-r4",     ARM_ARCH_V7R,    FPU_NONE,        "Cortex-R4"),
   ARM_CPU_OPT ("cortex-r4f",    ARM_ARCH_V7R,    FPU_ARCH_VFP_V3D16,
@@ -24418 +25364 @@
                                                  FPU_ARCH_VFP_V3D16,
                                                                   "Cortex-R7"),
+  ARM_CPU_OPT ("cortex-r8",     ARM_ARCH_V7R_IDIV,
+                                                 FPU_ARCH_VFP_V3D16,
+                                                                  "Cortex-R8"),
+  ARM_CPU_OPT ("cortex-m7",     ARM_ARCH_V7EM,   FPU_NONE,        "Cortex-M7"),
   ARM_CPU_OPT ("cortex-m4",     ARM_ARCH_V7EM,   FPU_NONE,        "Cortex-M4"),
   ARM_CPU_OPT ("cortex-m3",     ARM_ARCH_V7M,    FPU_NONE,        "Cortex-M3"),
@@ -24423 +25373 @@
   ARM_CPU_OPT ("cortex-m0",     ARM_ARCH_V6SM,   FPU_NONE,        "Cortex-M0"),
   ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM,   FPU_NONE,        "Cortex-M0+"),
+  ARM_CPU_OPT ("exynos-m1",     ARM_ARCH_V8A,    FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+                                                                  "Samsung " \
+                                                                  "Exynos M1"),
+  ARM_CPU_OPT ("qdf24xx",       ARM_ARCH_V8A,    FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+                                                                  "Qualcomm "
+                                                                  "QDF24XX"),
+
   /* ??? XSCALE is really an architecture.  */
   ARM_CPU_OPT ("xscale",        ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
@@ -24430 +25387 @@
   ARM_CPU_OPT ("i80200",        ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
   /* Maverick */
-  ARM_CPU_OPT ("ep9312",        ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
+  ARM_CPU_OPT ("ep9312",        ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
                                                  FPU_ARCH_MAVERICK, "ARM920T"),
   /* Marvell processors.  */
-  ARM_CPU_OPT ("marvell-pj4",   ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0),
+  ARM_CPU_OPT ("marvell-pj4",   ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP
+                                                  | ARM_EXT_SEC,
+                                                  ARM_EXT2_V6T2_V8M),
                                                 FPU_ARCH_VFP_V3D16, NULL),
+  ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP
+                                                    | ARM_EXT_SEC,
+                                                    ARM_EXT2_V6T2_V8M),
+                                               FPU_ARCH_NEON_VFP_V4, NULL),
+  /* APM X-Gene family.  */
+  ARM_CPU_OPT ("xgene1",        ARM_ARCH_V8A,    FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+                                                                  "APM X-Gene 1"),
+  ARM_CPU_OPT ("xgene2",        ARM_ARCH_V8A,    FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+                                                                  "APM X-Gene 2"),
 
   { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
@@ -24442 +25410 @@
 struct arm_arch_option_table
 {
-  char *name;
+  const char *name;
   size_t name_len;
   const arm_feature_set value;
@@ -24474 +25442 @@
   ARM_ARCH_OPT ("armv6k",       ARM_ARCH_V6K,    FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv6z",       ARM_ARCH_V6Z,    FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6zk",      ARM_ARCH_V6ZK,   FPU_ARCH_VFP),
+  /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
+     kept to preserve existing behaviour.  */
+  ARM_ARCH_OPT ("armv6kz",      ARM_ARCH_V6KZ,   FPU_ARCH_VFP),
+  ARM_ARCH_OPT ("armv6zk",      ARM_ARCH_V6KZ,   FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv6t2",      ARM_ARCH_V6T2,   FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv6kt2",     ARM_ARCH_V6KT2,  FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv6zt2",     ARM_ARCH_V6ZT2,  FPU_ARCH_VFP),
-  ARM_ARCH_OPT ("armv6zkt2",    ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
+  /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
+     kept to preserve existing behaviour.  */
+  ARM_ARCH_OPT ("armv6kzt2",    ARM_ARCH_V6KZT2, FPU_ARCH_VFP),
+  ARM_ARCH_OPT ("armv6zkt2",    ARM_ARCH_V6KZT2, FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv6-m",      ARM_ARCH_V6M,    FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv6s-m",     ARM_ARCH_V6SM,   FPU_ARCH_VFP),
@@ -24492 +25466 @@
   ARM_ARCH_OPT ("armv7-m",      ARM_ARCH_V7M,    FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv7e-m",     ARM_ARCH_V7EM,   FPU_ARCH_VFP),
+  ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
+  ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv8-a",      ARM_ARCH_V8A,    FPU_ARCH_VFP),
+  ARM_ARCH_OPT ("armv8.1-a",    ARM_ARCH_V8_1A,  FPU_ARCH_VFP),
+  ARM_ARCH_OPT ("armv8.2-a",    ARM_ARCH_V8_2A,  FPU_ARCH_VFP),
   ARM_ARCH_OPT ("xscale",       ARM_ARCH_XSCALE, FPU_ARCH_VFP),
   ARM_ARCH_OPT ("iwmmxt",       ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
@@ -24503 +25481 @@
 struct arm_option_extension_value_table
 {
-  char *name;
+  const char *name;
   size_t name_len;
-  const arm_feature_set value;
-  const arm_feature_set allowed_archs;
+  const arm_feature_set merge_value;
+  const arm_feature_set clear_value;
+  /* List of architectures for which an extension is available.  ARM_ARCH_NONE
+     indicates that an extension is available for all architectures while
+     ARM_ANY marks an empty entry.  */
+  const arm_feature_set allowed_archs[2];
 };
 
 /* The following table must be in alphabetical order with a NULL last entry.
    */
-#define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
+#define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
+#define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
 static const struct arm_option_extension_value_table arm_extensions[] =
 {
-  ARM_EXT_OPT ("crc",  ARCH_CRC_ARMV8, ARM_FEATURE (ARM_EXT_V8, 0)),
+  ARM_EXT_OPT ("crc",  ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+                         ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
   ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
-                                   ARM_FEATURE (ARM_EXT_V8, 0)),
-  ARM_EXT_OPT ("fp",     FPU_ARCH_VFP_ARMV8,
-                                   ARM_FEATURE (ARM_EXT_V8, 0)),
-  ARM_EXT_OPT ("idiv",  ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
-                                   ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
-  ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT),       ARM_ANY),
-  ARM_EXT_OPT ("iwmmxt2",
-                        ARM_FEATURE (0, ARM_CEXT_IWMMXT2),      ARM_ANY),
-  ARM_EXT_OPT ("maverick",
-                        ARM_FEATURE (0, ARM_CEXT_MAVERICK),     ARM_ANY),
-  ARM_EXT_OPT ("mp",    ARM_FEATURE (ARM_EXT_MP, 0),
-                                   ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
-  ARM_EXT_OPT ("simd",   FPU_ARCH_NEON_VFP_ARMV8,
-                                   ARM_FEATURE (ARM_EXT_V8, 0)),
-  ARM_EXT_OPT ("os",    ARM_FEATURE (ARM_EXT_OS, 0),
-                                   ARM_FEATURE (ARM_EXT_V6M, 0)),
-  ARM_EXT_OPT ("sec",   ARM_FEATURE (ARM_EXT_SEC, 0),
-                                   ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
-  ARM_EXT_OPT ("virt",  ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
-                                     | ARM_EXT_DIV, 0),
-                                   ARM_FEATURE (ARM_EXT_V7A, 0)),
-  ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE),       ARM_ANY),
-  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+                         ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
+                                   ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
+  ARM_EXT_OPT ("dsp",   ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
+                        ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
+  ARM_EXT_OPT ("fp",     FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
+                                   ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
+  ARM_EXT_OPT ("fp16",  ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+                        ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+                        ARM_ARCH_V8_2A),
+  ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
+  ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
+                        ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
+  ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
+                        ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
+  ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+                        ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
+  ARM_EXT_OPT2 ("mp",   ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
+  ARM_EXT_OPT ("os",    ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
+                                   ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
+  ARM_EXT_OPT ("pan",   ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
+                        ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
+  ARM_EXT_OPT ("ras",   ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
+                        ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
+  ARM_EXT_OPT ("rdma",  FPU_ARCH_NEON_VFP_ARMV8_1,
+                        ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
+  ARM_EXT_OPT2 ("sec",  ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
+  ARM_EXT_OPT ("simd",  FPU_ARCH_NEON_VFP_ARMV8,
+                        ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
+  ARM_EXT_OPT ("virt",  ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
+                                     | ARM_EXT_DIV),
+                        ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
+                                   ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
+  ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+                        ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
 };
 #undef ARM_EXT_OPT
@@ -24545 +25556 @@
 struct arm_option_fpu_value_table
 {
-  char *name;
+  const char *name;
   const arm_feature_set value;
 };
@@ -24586 +25597 @@
   {"vfpv4-d16",         FPU_ARCH_VFP_V4D16},
   {"fpv4-sp-d16",       FPU_ARCH_VFP_V4_SP_D16},
+  {"fpv5-d16",          FPU_ARCH_VFP_V5D16},
+  {"fpv5-sp-d16",       FPU_ARCH_VFP_V5_SP_D16},
   {"neon-vfpv4",        FPU_ARCH_NEON_VFP_V4},
   {"fp-armv8",          FPU_ARCH_VFP_ARMV8},
@@ -24591 +25604 @@
   {"crypto-neon-fp-armv8",
                         FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
+  {"neon-fp-armv8.1",   FPU_ARCH_NEON_VFP_ARMV8_1},
+  {"crypto-neon-fp-armv8.1",
+                        FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
   {NULL,                ARM_ARCH_NONE}
 };
@@ -24596 +25612 @@
 struct arm_option_value_table
 {
-  char *name;
+  const char *name;
   long value;
 };
@@ -24621 +25637 @@
 struct arm_long_option_table
 {
-  char * option;                /* Substring to match.  */
-  char * help;                  /* Help information.  */
-  int (* func) (char * subopt); /* Function to decode sub-option.  */
-  char * deprecated;            /* If non-null, print this message.  */
+  const char * option;          /* Substring to match.  */
+  const char * help;                    /* Help information.  */
+  int (* func) (const char * subopt);   /* Function to decode sub-option.  */
+  const char * deprecated;              /* If non-null, print this message.  */
 };
 
 static bfd_boolean
-arm_parse_extension (char *str, const arm_feature_set **opt_p)
-{
-  arm_feature_set *ext_set = (arm_feature_set *)
-      xmalloc (sizeof (arm_feature_set));
+arm_parse_extension (const char *str, const arm_feature_set **opt_p)
+{
+  arm_feature_set *ext_set = XNEW (arm_feature_set);
 
   /* We insist on extensions being specified in alphabetical order, and with
@@ -24640 +25655 @@
      -1 -> 1 -> 0.  */
   const struct arm_option_extension_value_table * opt = NULL;
+  const arm_feature_set arm_any = ARM_ANY;
   int adding_value = -1;
 
@@ -24648 +25664 @@
   while (str != NULL && *str != 0)
     {
-      char *ext;
+      const char *ext;
       size_t len;
 
@@ -24704 +25720 @@
         if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
           {
+            int i, nb_allowed_archs =
+              sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
             /* Check we can apply the extension to this architecture.  */
-            if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
+            for (i = 0; i < nb_allowed_archs; i++)
+              {
+                /* Empty entry.  */
+                if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
+                  continue;
+                if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *ext_set))
+                  break;
+              }
+            if (i == nb_allowed_archs)
               {
                 as_bad (_("extension does not apply to the base architecture"));
@@ -24713 +25739 @@
             /* Add or remove the extension.  */
             if (adding_value)
-              ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
+              ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
             else
-              ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
+              ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
 
             break;
@@ -24751 +25777 @@
 
 static bfd_boolean
-arm_parse_cpu (char *str)
+arm_parse_cpu (const char *str)
 {
   const struct arm_cpu_option_table *opt;
-  char *ext = strchr (str, '+');
+  const char *ext = strchr (str, '+');
   size_t len;
 
@@ -24774 +25800 @@
         mcpu_fpu_opt = &opt->default_fpu;
         if (opt->canonical_name)
-          strcpy (selected_cpu_name, opt->canonical_name);
+          {
+            gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
+            strcpy (selected_cpu_name, opt->canonical_name);
+          }
         else
           {
             size_t i;
+
+            if (len >= sizeof selected_cpu_name)
+              len = (sizeof selected_cpu_name) - 1;
 
             for (i = 0; i < len; i++)
@@ -24795 +25827 @@
 
 static bfd_boolean
-arm_parse_arch (char *str)
+arm_parse_arch (const char *str)
 {
   const struct arm_arch_option_table *opt;
-  char *ext = strchr (str, '+');
+  const char *ext = strchr (str, '+');
   size_t len;
 
@@ -24830 +25862 @@
 
 static bfd_boolean
-arm_parse_fpu (char * str)
+arm_parse_fpu (const char * str)
 {
   const struct arm_option_fpu_value_table * opt;
@@ -24846 +25878 @@
 
 static bfd_boolean
-arm_parse_float_abi (char * str)
+arm_parse_float_abi (const char * str)
 {
   const struct arm_option_value_table * opt;
@@ -24863 +25895 @@
 #ifdef OBJ_ELF
 static bfd_boolean
-arm_parse_eabi (char * str)
+arm_parse_eabi (const char * str)
 {
   const struct arm_option_value_table *opt;
@@ -24879 +25911 @@
 
 static bfd_boolean
-arm_parse_it_mode (char * str)
+arm_parse_it_mode (const char * str)
 {
   bfd_boolean ret = TRUE;
@@ -24902 +25934 @@
 
 static bfd_boolean
-arm_ccs_mode (char * unused ATTRIBUTE_UNUSED)
+arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
 {
   codecomposer_syntax = TRUE;
@@ -24932 +25964 @@
 
 int
-md_parse_option (int c, char * arg)
+md_parse_option (int c, const char * arg)
 {
   struct arm_option_table *opt;
@@ -25060 +26092 @@
 } cpu_arch_ver_table;
 
-/* Mapping from CPU features to EABI CPU arch values.  Table must be sorted
-   least features first.  */
+/* Mapping from CPU features to EABI CPU arch values.  As a general rule, table
+   must be sorted least features first but some reordering is needed, eg. for
+   Thumb-2 instructions to be detected as coming from ARMv6T2.  */
 static const cpu_arch_ver_table cpu_arch_ver[] =
 {
@@ -25080 +26113 @@
     {10, ARM_ARCH_V7M},
     {14, ARM_ARCH_V8A},
+    {16, ARM_ARCH_V8M_BASE},
+    {17, ARM_ARCH_V8M_MAIN},
     {0, ARM_ARCH_NONE}
 };
@@ -25103 +26138 @@
 
 /* Set the public EABI object attributes.  */
-static void
+void
 aeabi_set_public_attributes (void)
 {
@@ -25110 +26145 @@
   int virt_sec = 0;
   int fp16_optional = 0;
+  arm_feature_set arm_arch = ARM_ARCH_NONE;
   arm_feature_set flags;
   arm_feature_set tmp;
+  arm_feature_set arm_arch_v8m_base = ARM_ARCH_V8M_BASE;
   const cpu_arch_ver_table *p;
 
@@ -25148 +26185 @@
         {
           arch = p->val;
+          arm_arch = p->flags;
           ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
         }
@@ -25160 +26198 @@
      and implicit cases.  Avoid taking this path for -march=all by
      checking for contradictory v7-A / v7-M features.  */
-  if (arch == 10
+  if (arch == TAG_CPU_ARCH_V7
       && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
       && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
       && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
-    arch = 13;
+    {
+      arch = TAG_CPU_ARCH_V7E_M;
+      arm_arch = (arm_feature_set) ARM_ARCH_V7EM;
+    }
+
+  ARM_CLEAR_FEATURE (tmp, flags, arm_arch_v8m_base);
+  if (arch == TAG_CPU_ARCH_V8M_BASE && ARM_CPU_HAS_FEATURE (tmp, arm_arch_any))
+    {
+      arch = TAG_CPU_ARCH_V8M_MAIN;
+      arm_arch = (arm_feature_set) ARM_ARCH_V8M_MAIN;
+    }
+
+  /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
+     coming from ARMv8-A.  However, since ARMv8-A has more instructions than
+     ARMv8-M, -march=all must be detected as ARMv8-A.  */
+  if (arch == TAG_CPU_ARCH_V8M_MAIN
+      && ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
+    {
+      arch = TAG_CPU_ARCH_V8;
+      arm_arch = (arm_feature_set) ARM_ARCH_V8A;
+    }
 
   /* Tag_CPU_name.  */
@@ -25187 +26245 @@
 
   /* Tag_CPU_arch_profile.  */
-  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
+  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
+      || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
+      || (ARM_CPU_HAS_FEATURE (flags, arm_ext_atomics)
+          && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only)))
     profile = 'A';
   else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
@@ -25199 +26260 @@
     aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
 
+  /* Tag_DSP_extension.  */
+  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_dsp))
+    {
+      arm_feature_set ext;
+
+      /* DSP instructions not in architecture.  */
+      ARM_CLEAR_FEATURE (ext, flags, arm_arch);
+      if (ARM_CPU_HAS_FEATURE (ext, arm_ext_dsp))
+        aeabi_set_attribute_int (Tag_DSP_extension, 1);
+    }
+
   /* Tag_ARM_ISA_use.  */
   if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
@@ -25207 +26279 @@
   if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
       || arch == 0)
-    aeabi_set_attribute_int (Tag_THUMB_ISA_use,
-        ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
+    {
+      int thumb_isa_use;
+
+      if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
+          && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
+        thumb_isa_use = 3;
+      else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
+        thumb_isa_use = 2;
+      else
+        thumb_isa_use = 1;
+      aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
+    }
 
   /* Tag_VFP_arch.  */
-  if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
-    aeabi_set_attribute_int (Tag_VFP_arch, 7);
+  if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
+    aeabi_set_attribute_int (Tag_VFP_arch,
+                             ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
+                             ? 7 : 8);
   else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
     aeabi_set_attribute_int (Tag_VFP_arch,
@@ -25245 +26329 @@
 
   /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch).  */
-  if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
+  if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
+    aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
+  else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
     aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
   else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
@@ -25270 +26356 @@
      but we have no architecture profile set, nor have we any ARM instructions.
 
-     For ARMv8 we set the tag to 0 as integer divide is implied by the base
-     architecture.
+     For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
+     by the base architecture.
 
      For new architectures we will have to check these tests.  */
-  gas_assert (arch <= TAG_CPU_ARCH_V8);
-  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
+  gas_assert (arch <= TAG_CPU_ARCH_V8
+              || (arch >= TAG_CPU_ARCH_V8M_BASE
+                  && arch <= TAG_CPU_ARCH_V8M_MAIN));
+  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
+      || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
     aeabi_set_attribute_int (Tag_DIV_use, 0);
   else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
@@ -25420 +26509 @@
 {
   const struct arm_option_extension_value_table *opt;
+  const arm_feature_set arm_any = ARM_ANY;
   char saved_char;
   char *name;
@@ -25440 +26530 @@
     if (streq (opt->name, name))
       {
-        if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
+        int i, nb_allowed_archs =
+          sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
+        for (i = 0; i < nb_allowed_archs; i++)
+          {
+            /* Empty entry.  */
+            if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
+              continue;
+            if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *mcpu_cpu_opt))
+              break;
+          }
+
+        if (i == nb_allowed_archs)
           {
             as_bad (_("architectural extension `%s' is not allowed for the "
@@ -25448 +26549 @@
 
         if (adding_value)
-          ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
+          ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu,
+                                  opt->merge_value);
         else
-          ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
+          ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->clear_value);
 
         mcpu_cpu_opt = &selected_cpu;
@@ -25564 +26666 @@
       T (Tag_T2EE_use),
       T (Tag_Virtualization_use),
+      T (Tag_DSP_extension),
       /* We deliberately do not include Tag_MPextension_use_legacy.  */
 #undef T
@@ -25580 +26683 @@
 
 
-/* Apply sym value for relocations only in the case that
-   they are for local symbols and you have the respective
-   architectural feature for blx and simple switches.  */
+/* Apply sym value for relocations only in the case that they are for
+   local symbols in the same segment as the fixup and you have the
+   respective architectural feature for blx and simple switches.  */
 int
-arm_apply_sym_value (struct fix * fixP)
+arm_apply_sym_value (struct fix * fixP, segT this_seg)
 {
   if (fixP->fx_addsy
       && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
+      /* PR 17444: If the local symbol is in a different section then a reloc
+         will always be generated for it, so applying the symbol value now
+         will result in a double offset being stored in the relocation.  */
+      && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
       && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
     {
@@ -25601 +26708 @@
         case BFD_RELOC_THUMB_PCREL_BLX:
           if (THUMB_IS_FUNC (fixP->fx_addsy))
-              return 1;
+            return 1;
           break;