- Timestamp:
- Jun 15, 2017, 9:08:49 AM (8 years ago)
- Location:
- binutils/trunk/gas/doc
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
TabularUnified binutils/trunk/gas/doc/as.1 ¶
r2201 r2202 1 .\" Automatically generated by Pod::Man 2.27 (Pod::Simple 3.28) 2 .\" 3 .\" Standard preamble: 4 .\" ======================================================================== 5 .de Sp \" Vertical space (when we can't use .PP) 6 .if t .sp .5v 7 .if n .sp 8 .. 9 .de Vb \" Begin verbatim text 10 .ft CW 11 .nf 12 .ne \\$1 13 .. 14 .de Ve \" End verbatim text 15 .ft R 16 .fi 17 .. 18 .\" Set up some character translations and predefined strings. \*(-- will 19 .\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left 20 .\" double quote, and \*(R" will give a right double quote. \*(C+ will 21 .\" give a nicer C++. Capital omega is used to do unbreakable dashes and 22 .\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, 23 .\" nothing in troff, for use with C<>. 24 .tr \(*W- 25 .ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' 26 .ie n \{\ 27 . ds -- \(*W- 28 . ds PI pi 29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch 30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch 31 . ds L" "" 32 . ds R" "" 33 . ds C` "" 34 . ds C' "" 35 'br\} 36 .el\{\ 37 . ds -- \|\(em\| 38 . ds PI \(*p 39 . ds L" `` 40 . ds R" '' 41 . ds C` 42 . ds C' 43 'br\} 44 .\" 45 .\" Escape single quotes in literal strings from groff's Unicode transform. 46 .ie \n(.g .ds Aq \(aq 47 .el .ds Aq ' 48 .\" 49 .\" If the F register is turned on, we'll generate index entries on stderr for 50 .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index 51 .\" entries marked with X<> in POD. Of course, you'll have to process the 52 .\" output yourself in some meaningful fashion. 53 .\" 54 .\" Avoid warning from groff about undefined register 'F'. 55 .de IX 56 .. 57 .nr rF 0 58 .if \n(.g .if rF .nr rF 1 59 .if (\n(rF:(\n(.g==0)) \{ 60 . if \nF \{ 61 . de IX 62 . tm Index:\\$1\t\\n%\t"\\$2" 63 .. 64 . if !\nF==2 \{ 65 . nr % 0 66 . nr F 2 67 . \} 68 . \} 69 .\} 70 .rr rF 71 .\" 72 .\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). 73 .\" Fear. Run. Save yourself. No user-serviceable parts. 74 . \" fudge factors for nroff and troff 75 .if n \{\ 76 . ds #H 0 77 . ds #V .8m 78 . ds #F .3m 79 . ds #[ \f1 80 . ds #] \fP 81 .\} 82 .if t \{\ 83 . ds #H ((1u-(\\\\n(.fu%2u))*.13m) 84 . ds #V .6m 85 . ds #F 0 86 . ds #[ \& 87 . ds #] \& 88 .\} 89 . \" simple accents for nroff and troff 90 .if n \{\ 91 . ds ' \& 92 . ds ` \& 93 . ds ^ \& 94 . ds , \& 95 . ds ~ ~ 96 . ds / 97 .\} 98 .if t \{\ 99 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" 100 . ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' 101 . ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' 102 . ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' 103 . ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' 104 . ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' 105 .\} 106 . \" troff and (daisy-wheel) nroff accents 107 .ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' 108 .ds 8 \h'\*(#H'\(*b\h'-\*(#H' 109 .ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] 110 .ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' 111 .ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' 112 .ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] 113 .ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] 114 .ds ae a\h'-(\w'a'u*4/10)'e 115 .ds Ae A\h'-(\w'A'u*4/10)'E 116 . \" corrections for vroff 117 .if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' 118 .if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' 119 . \" for low resolution devices (crt and lpr) 120 .if \n(.H>23 .if \n(.V>19 \ 121 \{\ 122 . ds : e 123 . ds 8 ss 124 . ds o a 125 . ds d- d\h'-1'\(ga 126 . ds D- D\h'-1'\(hy 127 . ds th \o'bp' 128 . ds Th \o'LP' 129 . ds ae ae 130 . ds Ae AE 131 .\} 132 .rm #[ #] #H #V #F C 133 .\" ======================================================================== 134 .\" 135 .IX Title "AS 1" 136 .TH AS 1 "2016-08-03" "binutils-2.27" "GNU Development Tools" 137 .\" For nroff, turn off justification. Always turn off hyphenation; it makes 138 .\" way too many mistakes in technical documents. 139 .if n .ad l 140 .nh 141 .SH "NAME" 142 AS \- the portable GNU assembler. 143 .SH "SYNOPSIS" 144 .IX Header "SYNOPSIS" 145 as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR] 146 [\fB\-\-compress\-debug\-sections\fR] [\fB\-\-nocompress\-debug\-sections\fR] 147 [\fB\-\-debug\-prefix\-map\fR \fIold\fR=\fInew\fR] 148 [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR] 149 [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-gdwarf\-sections\fR] 150 [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR] 151 [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR] 152 [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR] 153 [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR] 154 [\fB\-\-no\-pad\-sections\fR] 155 [\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR] 156 [\fB\-\-hash\-size\fR=\fI\s-1NUM\s0\fR] [\fB\-\-reduce\-memory\-overheads\fR] 157 [\fB\-\-statistics\fR] 158 [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR] 159 [\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR] 160 [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR] 161 [\fB\-\-sectname\-subst\fR] [\fB\-\-size\-check=[error|warning]\fR] 162 [\fB\-\-elf\-stt\-common=[no|yes]\fR] 163 [\fB\-\-target\-help\fR] [\fItarget-options\fR] 164 [\fB\-\-\fR|\fIfiles\fR ...] 165 .SH "TARGET" 166 .IX Header "TARGET" 167 \&\fITarget AArch64 options:\fR 168 [\fB\-EB\fR|\fB\-EL\fR] 169 [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] 170 .PP 171 \&\fITarget Alpha options:\fR 172 [\fB\-m\fR\fIcpu\fR] 173 [\fB\-mdebug\fR | \fB\-no\-mdebug\fR] 174 [\fB\-replace\fR | \fB\-noreplace\fR] 175 [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR] 176 [\fB\-F\fR] [\fB\-32addr\fR] 177 .PP 178 \&\fITarget \s-1ARC\s0 options:\fR 179 [\fB\-mcpu=\fR\fIcpu\fR] 180 [\fB\-mA6\fR|\fB\-mARC600\fR|\fB\-mARC601\fR|\fB\-mA7\fR|\fB\-mARC700\fR|\fB\-mEM\fR|\fB\-mHS\fR] 181 [\fB\-mcode\-density\fR] 182 [\fB\-mrelax\fR] 183 [\fB\-EB\fR|\fB\-EL\fR] 184 .PP 185 \&\fITarget \s-1ARM\s0 options:\fR 186 [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]] 187 [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]] 188 [\fB\-mfpu\fR=\fIfloating-point-format\fR] 189 [\fB\-mfloat\-abi\fR=\fIabi\fR] 190 [\fB\-meabi\fR=\fIver\fR] 191 [\fB\-mthumb\fR] 192 [\fB\-EB\fR|\fB\-EL\fR] 193 [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR| 194 \fB\-mapcs\-reentrant\fR] 195 [\fB\-mthumb\-interwork\fR] [\fB\-k\fR] 196 .PP 197 \&\fITarget Blackfin options:\fR 198 [\fB\-mcpu\fR=\fIprocessor\fR[\-\fIsirevision\fR]] 199 [\fB\-mfdpic\fR] 200 [\fB\-mno\-fdpic\fR] 201 [\fB\-mnopic\fR] 202 .PP 203 \&\fITarget \s-1CRIS\s0 options:\fR 204 [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR] 205 [\fB\-\-pic\fR] [\fB\-N\fR] 206 [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR] 207 [\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR] 208 .PP 209 \&\fITarget D10V options:\fR 210 [\fB\-O\fR] 211 .PP 212 \&\fITarget D30V options:\fR 213 [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR] 214 .PP 215 \&\fITarget \s-1EPIPHANY\s0 options:\fR 216 [\fB\-mepiphany\fR|\fB\-mepiphany16\fR] 217 .PP 218 \&\fITarget H8/300 options:\fR 219 [\-h\-tick\-hex] 220 .PP 221 \&\fITarget i386 options:\fR 222 [\fB\-\-32\fR|\fB\-\-x32\fR|\fB\-\-64\fR] [\fB\-n\fR] 223 [\fB\-march\fR=\fI\s-1CPU\s0\fR[+\fI\s-1EXTENSION\s0\fR...]] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] 224 .PP 225 \&\fITarget i960 options:\fR 226 [\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR| 227 \fB\-AKC\fR|\fB\-AMC\fR] 228 [\fB\-b\fR] [\fB\-no\-relax\fR] 229 .PP 230 \&\fITarget \s-1IA\-64\s0 options:\fR 231 [\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR] 232 [\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR] 233 [\fB\-mle\fR|\fBmbe\fR] 234 [\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR] 235 [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR] 236 [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR] 237 [\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR] 238 .PP 239 \&\fITarget \s-1IP2K\s0 options:\fR 240 [\fB\-mip2022\fR|\fB\-mip2022ext\fR] 241 .PP 242 \&\fITarget M32C options:\fR 243 [\fB\-m32c\fR|\fB\-m16c\fR] [\-relax] [\-h\-tick\-hex] 244 .PP 245 \&\fITarget M32R options:\fR 246 [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR| 247 \fB\-\-W[n]p\fR] 248 .PP 249 \&\fITarget M680X0 options:\fR 250 [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...] 251 .PP 252 \&\fITarget M68HC11 options:\fR 253 [\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR|\fB\-mm9s12x\fR|\fB\-mm9s12xg\fR] 254 [\fB\-mshort\fR|\fB\-mlong\fR] 255 [\fB\-mshort\-double\fR|\fB\-mlong\-double\fR] 256 [\fB\-\-force\-long\-branches\fR] [\fB\-\-short\-branches\fR] 257 [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR] 258 [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR] 259 .PP 260 \&\fITarget \s-1MCORE\s0 options:\fR 261 [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR] 262 [\fB\-mcpu=[210|340]\fR] 263 .PP 264 \&\fITarget Meta options:\fR 265 [\fB\-mcpu=\fR\fIcpu\fR] [\fB\-mfpu=\fR\fIcpu\fR] [\fB\-mdsp=\fR\fIcpu\fR] 266 \&\fITarget \s-1MICROBLAZE\s0 options:\fR 267 .PP 268 \&\fITarget \s-1MIPS\s0 options:\fR 269 [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]] 270 [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR] 271 [\fB\-non_shared\fR] [\fB\-xgot\fR [\fB\-mvxworks\-pic\fR] 272 [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR] 273 [\fB\-mfp64\fR] [\fB\-mgp64\fR] [\fB\-mfpxx\fR] 274 [\fB\-modd\-spreg\fR] [\fB\-mno\-odd\-spreg\fR] 275 [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR] 276 [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR] 277 [\fB\-mips32r3\fR] [\fB\-mips32r5\fR] [\fB\-mips32r6\fR] [\fB\-mips64\fR] [\fB\-mips64r2\fR] 278 [\fB\-mips64r3\fR] [\fB\-mips64r5\fR] [\fB\-mips64r6\fR] 279 [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR] 280 [\fB\-mnan=\fR\fIencoding\fR] 281 [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR] 282 [\fB\-mips16\fR] [\fB\-no\-mips16\fR] 283 [\fB\-mmicromips\fR] [\fB\-mno\-micromips\fR] 284 [\fB\-msmartmips\fR] [\fB\-mno\-smartmips\fR] 285 [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR] 286 [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR] 287 [\fB\-mdsp\fR] [\fB\-mno\-dsp\fR] 288 [\fB\-mdspr2\fR] [\fB\-mno\-dspr2\fR] 289 [\fB\-mdspr3\fR] [\fB\-mno\-dspr3\fR] 290 [\fB\-mmsa\fR] [\fB\-mno\-msa\fR] 291 [\fB\-mxpa\fR] [\fB\-mno\-xpa\fR] 292 [\fB\-mmt\fR] [\fB\-mno\-mt\fR] 293 [\fB\-mmcu\fR] [\fB\-mno\-mcu\fR] 294 [\fB\-minsn32\fR] [\fB\-mno\-insn32\fR] 295 [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR] 296 [\fB\-mfix\-rm7000\fR] [\fB\-mno\-fix\-rm7000\fR] 297 [\fB\-mfix\-vr4120\fR] [\fB\-mno\-fix\-vr4120\fR] 298 [\fB\-mfix\-vr4130\fR] [\fB\-mno\-fix\-vr4130\fR] 299 [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR] 300 [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR] 301 .PP 302 \&\fITarget \s-1MMIX\s0 options:\fR 303 [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR] 304 [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR] 305 [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR] 306 [\fB\-\-linker\-allocated\-gregs\fR] 307 .PP 308 \&\fITarget Nios \s-1II\s0 options:\fR 309 [\fB\-relax\-all\fR] [\fB\-relax\-section\fR] [\fB\-no\-relax\fR] 310 [\fB\-EB\fR] [\fB\-EL\fR] 311 .PP 312 \&\fITarget \s-1NDS32\s0 options:\fR 313 [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR] [\fB\-Os\fR] [\fB\-mcpu=\fR\fIcpu\fR] 314 [\fB\-misa=\fR\fIisa\fR] [\fB\-mabi=\fR\fIabi\fR] [\fB\-mall\-ext\fR] 315 [\fB\-m[no\-]16\-bit\fR] [\fB\-m[no\-]perf\-ext\fR] [\fB\-m[no\-]perf2\-ext\fR] 316 [\fB\-m[no\-]string\-ext\fR] [\fB\-m[no\-]dsp\-ext\fR] [\fB\-m[no\-]mac\fR] [\fB\-m[no\-]div\fR] 317 [\fB\-m[no\-]audio\-isa\-ext\fR] [\fB\-m[no\-]fpu\-sp\-ext\fR] [\fB\-m[no\-]fpu\-dp\-ext\fR] 318 [\fB\-m[no\-]fpu\-fma\fR] [\fB\-mfpu\-freg=\fR\fI\s-1FREG\s0\fR] [\fB\-mreduced\-regs\fR] 319 [\fB\-mfull\-regs\fR] [\fB\-m[no\-]dx\-regs\fR] [\fB\-mpic\fR] [\fB\-mno\-relax\fR] 320 [\fB\-mb2bb\fR] 321 .PP 322 \&\fITarget \s-1PDP11\s0 options:\fR 323 [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR] 324 [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR] 325 [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR] 326 .PP 327 \&\fITarget picoJava options:\fR 328 [\fB\-mb\fR|\fB\-me\fR] 329 .PP 330 \&\fITarget PowerPC options:\fR 331 [\fB\-a32\fR|\fB\-a64\fR] 332 [\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|\fB\-m403\fR|\fB\-m405\fR| 333 \fB\-m440\fR|\fB\-m464\fR|\fB\-m476\fR|\fB\-m7400\fR|\fB\-m7410\fR|\fB\-m7450\fR|\fB\-m7455\fR|\fB\-m750cl\fR|\fB\-mppc64\fR| 334 \fB\-m620\fR|\fB\-me500\fR|\fB\-e500x2\fR|\fB\-me500mc\fR|\fB\-me500mc64\fR|\fB\-me5500\fR|\fB\-me6500\fR|\fB\-mppc64bridge\fR| 335 \fB\-mbooke\fR|\fB\-mpower4\fR|\fB\-mpwr4\fR|\fB\-mpower5\fR|\fB\-mpwr5\fR|\fB\-mpwr5x\fR|\fB\-mpower6\fR|\fB\-mpwr6\fR| 336 \fB\-mpower7\fR|\fB\-mpwr7\fR|\fB\-mpower8\fR|\fB\-mpwr8\fR|\fB\-mpower9\fR|\fB\-mpwr9\fR\fB\-ma2\fR| 337 \fB\-mcell\fR|\fB\-mspe\fR|\fB\-mtitan\fR|\fB\-me300\fR|\fB\-mcom\fR] 338 [\fB\-many\fR] [\fB\-maltivec\fR|\fB\-mvsx\fR|\fB\-mhtm\fR|\fB\-mvle\fR] 339 [\fB\-mregnames\fR|\fB\-mno\-regnames\fR] 340 [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR|\fB\-K \s-1PIC\s0\fR] [\fB\-memb\fR] 341 [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-le\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR|\fB\-be\fR] 342 [\fB\-msolaris\fR|\fB\-mno\-solaris\fR] 343 [\fB\-nops=\fR\fIcount\fR] 344 .PP 345 \&\fITarget \s-1RL78\s0 options:\fR 346 [\fB\-mg10\fR] 347 [\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR] 348 .PP 349 \&\fITarget \s-1RX\s0 options:\fR 350 [\fB\-mlittle\-endian\fR|\fB\-mbig\-endian\fR] 351 [\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR] 352 [\fB\-muse\-conventional\-section\-names\fR] 353 [\fB\-msmall\-data\-limit\fR] 354 [\fB\-mpid\fR] 355 [\fB\-mrelax\fR] 356 [\fB\-mint\-register=\fR\fInumber\fR] 357 [\fB\-mgcc\-abi\fR|\fB\-mrx\-abi\fR] 358 .PP 359 \&\fITarget s390 options:\fR 360 [\fB\-m31\fR|\fB\-m64\fR] [\fB\-mesa\fR|\fB\-mzarch\fR] [\fB\-march\fR=\fI\s-1CPU\s0\fR] 361 [\fB\-mregnames\fR|\fB\-mno\-regnames\fR] 362 [\fB\-mwarn\-areg\-zero\fR] 363 .PP 364 \&\fITarget \s-1SCORE\s0 options:\fR 365 [\fB\-EB\fR][\fB\-EL\fR][\fB\-FIXDD\fR][\fB\-NWARN\fR] 366 [\fB\-SCORE5\fR][\fB\-SCORE5U\fR][\fB\-SCORE7\fR][\fB\-SCORE3\fR] 367 [\fB\-march=score7\fR][\fB\-march=score3\fR] 368 [\fB\-USE_R1\fR][\fB\-KPIC\fR][\fB\-O0\fR][\fB\-G\fR \fInum\fR][\fB\-V\fR] 369 .PP 370 \&\fITarget \s-1SPARC\s0 options:\fR 371 [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR 372 \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR] 373 [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR] 374 [\fB\-32\fR|\fB\-64\fR] 375 .PP 376 \&\fITarget \s-1TIC54X\s0 options:\fR 377 [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR] 378 [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR] 379 .PP 380 \&\fITarget \s-1TIC6X\s0 options:\fR 381 [\fB\-march=\fR\fIarch\fR] [\fB\-mbig\-endian\fR|\fB\-mlittle\-endian\fR] 382 [\fB\-mdsbt\fR|\fB\-mno\-dsbt\fR] [\fB\-mpid=no\fR|\fB\-mpid=near\fR|\fB\-mpid=far\fR] 383 [\fB\-mpic\fR|\fB\-mno\-pic\fR] 384 .PP 385 \&\fITarget TILE-Gx options:\fR 386 [\fB\-m32\fR|\fB\-m64\fR][\fB\-EB\fR][\fB\-EL\fR] 387 .PP 388 \&\fITarget Visium options:\fR 389 [\fB\-mtune=\fR\fIarch\fR] 390 .PP 391 \&\fITarget Xtensa options:\fR 392 [\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]auto\-litpools\fR] 393 [\fB\-\-[no\-]absolute\-literals\fR] 394 [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR] 395 [\fB\-\-[no\-]transform\fR] 396 [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR] 397 [\fB\-\-[no\-]trampolines\fR] 398 .PP 399 \&\fITarget Z80 options:\fR 400 [\fB\-z80\fR] [\fB\-r800\fR] 401 [ \fB\-ignore\-undocumented\-instructions\fR] [\fB\-Wnud\fR] 402 [ \fB\-ignore\-unportable\-instructions\fR] [\fB\-Wnup\fR] 403 [ \fB\-warn\-undocumented\-instructions\fR] [\fB\-Wud\fR] 404 [ \fB\-warn\-unportable\-instructions\fR] [\fB\-Wup\fR] 405 [ \fB\-forbid\-undocumented\-instructions\fR] [\fB\-Fud\fR] 406 [ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR] 407 .SH "DESCRIPTION" 408 .IX Header "DESCRIPTION" 409 \&\s-1GNU \s0\fBas\fR is really a family of assemblers. 410 If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you 411 should find a fairly similar environment when you use it on another 412 architecture. Each version has much in common with the others, 413 including object file formats, most assembler directives (often called 414 \&\fIpseudo-ops\fR) and assembler syntax. 415 .PP 416 \&\fBas\fR is primarily intended to assemble the output of the 417 \&\s-1GNU C\s0 compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker 418 \&\f(CW\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR 419 assemble correctly everything that other assemblers for the same 420 machine would assemble. 421 Any exceptions are documented explicitly. 422 This doesn't mean \fBas\fR always uses the same syntax as another 423 assembler for the same architecture; for example, we know of several 424 incompatible versions of 680x0 assembly language syntax. 425 .PP 426 Each time you run \fBas\fR it assembles exactly one source 427 program. The source program is made up of one or more files. 428 (The standard input is also a file.) 429 .PP 430 You give \fBas\fR a command line that has zero or more input file 431 names. The input files are read (from left file name to right). A 432 command line argument (in any position) that has no special meaning 433 is taken to be an input file name. 434 .PP 435 If you give \fBas\fR no file names it attempts to read one input file 436 from the \fBas\fR standard input, which is normally your terminal. You 437 may have to type \fBctl-D\fR to tell \fBas\fR there is no more program 438 to assemble. 439 .PP 440 Use \fB\-\-\fR if you need to explicitly name the standard input file 441 in your command line. 442 .PP 443 If the source is empty, \fBas\fR produces a small, empty object 444 file. 445 .PP 446 \&\fBas\fR may write warnings and error messages to the standard error 447 file (usually your terminal). This should not happen when a compiler 448 runs \fBas\fR automatically. Warnings report an assumption made so 449 that \fBas\fR could keep assembling a flawed program; errors report a 450 grave problem that stops the assembly. 451 .PP 452 If you are invoking \fBas\fR via the \s-1GNU C\s0 compiler, 453 you can use the \fB\-Wa\fR option to pass arguments through to the assembler. 454 The assembler arguments must be separated from each other (and the \fB\-Wa\fR) 455 by commas. For example: 456 .PP 457 .Vb 1 458 \& gcc \-c \-g \-O \-Wa,\-alh,\-L file.c 459 .Ve 460 .PP 461 This passes two options to the assembler: \fB\-alh\fR (emit a listing to 462 standard output with high-level and assembly source) and \fB\-L\fR (retain 463 local symbols in the symbol table). 464 .PP 465 Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler 466 command-line options are automatically passed to the assembler by the compiler. 467 (You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see 468 precisely what options it passes to each compilation pass, including the 469 assembler.) 470 .SH "OPTIONS" 471 .IX Header "OPTIONS" 472 .IP "\fB@\fR\fIfile\fR" 4 473 .IX Item "@file" 474 Read command-line options from \fIfile\fR. The options read are 475 inserted in place of the original @\fIfile\fR option. If \fIfile\fR 476 does not exist, or cannot be read, then the option will be treated 477 literally, and not removed. 478 .Sp 479 Options in \fIfile\fR are separated by whitespace. A whitespace 480 character may be included in an option by surrounding the entire 481 option in either single or double quotes. Any character (including a 482 backslash) may be included by prefixing the character to be included 483 with a backslash. The \fIfile\fR may itself contain additional 484 @\fIfile\fR options; any such options will be processed recursively. 485 .IP "\fB\-a[cdghlmns]\fR" 4 486 .IX Item "-a[cdghlmns]" 487 Turn on listings, in any of a variety of ways: 488 .RS 4 489 .IP "\fB\-ac\fR" 4 490 .IX Item "-ac" 491 omit false conditionals 492 .IP "\fB\-ad\fR" 4 493 .IX Item "-ad" 494 omit debugging directives 495 .IP "\fB\-ag\fR" 4 496 .IX Item "-ag" 497 include general information, like as version and options passed 498 .IP "\fB\-ah\fR" 4 499 .IX Item "-ah" 500 include high-level source 501 .IP "\fB\-al\fR" 4 502 .IX Item "-al" 503 include assembly 504 .IP "\fB\-am\fR" 4 505 .IX Item "-am" 506 include macro expansions 507 .IP "\fB\-an\fR" 4 508 .IX Item "-an" 509 omit forms processing 510 .IP "\fB\-as\fR" 4 511 .IX Item "-as" 512 include symbols 513 .IP "\fB=file\fR" 4 514 .IX Item "=file" 515 set the name of the listing file 516 .RE 517 .RS 4 518 .Sp 519 You may combine these options; for example, use \fB\-aln\fR for assembly 520 listing without forms processing. The \fB=file\fR option, if used, must be 521 the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR. 522 .RE 523 .IP "\fB\-\-alternate\fR" 4 524 .IX Item "--alternate" 525 Begin in alternate macro mode. 526 .IP "\fB\-\-compress\-debug\-sections\fR" 4 527 .IX Item "--compress-debug-sections" 528 Compress \s-1DWARF\s0 debug sections using zlib with \s-1SHF_COMPRESSED\s0 from the 529 \&\s-1ELF ABI. \s0 The resulting object file may not be compatible with older 530 linkers and object file utilities. Note if compression would make a 531 given section \fIlarger\fR then it is not compressed. 532 .IP "\fB\-\-compress\-debug\-sections=none\fR" 4 533 .IX Item "--compress-debug-sections=none" 534 .PD 0 535 .IP "\fB\-\-compress\-debug\-sections=zlib\fR" 4 536 .IX Item "--compress-debug-sections=zlib" 537 .IP "\fB\-\-compress\-debug\-sections=zlib\-gnu\fR" 4 538 .IX Item "--compress-debug-sections=zlib-gnu" 539 .IP "\fB\-\-compress\-debug\-sections=zlib\-gabi\fR" 4 540 .IX Item "--compress-debug-sections=zlib-gabi" 541 .PD 542 These options control how \s-1DWARF\s0 debug sections are compressed. 543 \&\fB\-\-compress\-debug\-sections=none\fR is equivalent to 544 \&\fB\-\-nocompress\-debug\-sections\fR. 545 \&\fB\-\-compress\-debug\-sections=zlib\fR and 546 \&\fB\-\-compress\-debug\-sections=zlib\-gabi\fR are equivalent to 547 \&\fB\-\-compress\-debug\-sections\fR. 548 \&\fB\-\-compress\-debug\-sections=zlib\-gnu\fR compresses \s-1DWARF\s0 debug 549 sections using zlib. The debug sections are renamed to begin with 550 \&\fB.zdebug\fR. Note if compression would make a given section 551 \&\fIlarger\fR then it is not compressed nor renamed. 552 .IP "\fB\-\-nocompress\-debug\-sections\fR" 4 553 .IX Item "--nocompress-debug-sections" 554 Do not compress \s-1DWARF\s0 debug sections. This is usually the default for all 555 targets except the x86/x86_64, but a configure time option can be used to 556 override this. 557 .IP "\fB\-D\fR" 4 558 .IX Item "-D" 559 Ignored. This option is accepted for script compatibility with calls to 560 other assemblers. 561 .IP "\fB\-\-debug\-prefix\-map\fR \fIold\fR\fB=\fR\fInew\fR" 4 562 .IX Item "--debug-prefix-map old=new" 563 When assembling files in directory \fI\fIold\fI\fR, record debugging 564 information describing them as in \fI\fInew\fI\fR instead. 565 .IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4 566 .IX Item "--defsym sym=value" 567 Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file. 568 \&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR 569 indicates a hexadecimal value, and a leading \fB0\fR indicates an octal 570 value. The value of the symbol can be overridden inside a source file via the 571 use of a \f(CW\*(C`.set\*(C'\fR pseudo-op. 572 .IP "\fB\-f\fR" 4 573 .IX Item "-f" 574 \&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is 575 compiler output). 576 .IP "\fB\-g\fR" 4 577 .IX Item "-g" 578 .PD 0 579 .IP "\fB\-\-gen\-debug\fR" 4 580 .IX Item "--gen-debug" 581 .PD 582 Generate debugging information for each assembler source line using whichever 583 debug format is preferred by the target. This currently means either \s-1STABS, 584 ECOFF\s0 or \s-1DWARF2.\s0 585 .IP "\fB\-\-gstabs\fR" 4 586 .IX Item "--gstabs" 587 Generate stabs debugging information for each assembler line. This 588 may help debugging assembler code, if the debugger can handle it. 589 .IP "\fB\-\-gstabs+\fR" 4 590 .IX Item "--gstabs+" 591 Generate stabs debugging information for each assembler line, with \s-1GNU\s0 592 extensions that probably only gdb can handle, and that could make other 593 debuggers crash or refuse to read your program. This 594 may help debugging assembler code. Currently the only \s-1GNU\s0 extension is 595 the location of the current working directory at assembling time. 596 .IP "\fB\-\-gdwarf\-2\fR" 4 597 .IX Item "--gdwarf-2" 598 Generate \s-1DWARF2\s0 debugging information for each assembler line. This 599 may help debugging assembler code, if the debugger can handle it. Note\-\-\-this 600 option is only supported by some targets, not all of them. 601 .IP "\fB\-\-gdwarf\-sections\fR" 4 602 .IX Item "--gdwarf-sections" 603 Instead of creating a .debug_line section, create a series of 604 \&.debug_line.\fIfoo\fR sections where \fIfoo\fR is the name of the 605 corresponding code section. For example a code section called \fI.text.func\fR 606 will have its dwarf line number information placed into a section called 607 \&\fI.debug_line.text.func\fR. If the code section is just called \fI.text\fR 608 then debug line section will still be called just \fI.debug_line\fR without any 609 suffix. 610 .IP "\fB\-\-size\-check=error\fR" 4 611 .IX Item "--size-check=error" 612 .PD 0 613 .IP "\fB\-\-size\-check=warning\fR" 4 614 .IX Item "--size-check=warning" 615 .PD 616 Issue an error or warning for invalid \s-1ELF \s0.size directive. 617 .IP "\fB\-\-elf\-stt\-common=no\fR" 4 618 .IX Item "--elf-stt-common=no" 619 .PD 0 620 .IP "\fB\-\-elf\-stt\-common=yes\fR" 4 621 .IX Item "--elf-stt-common=yes" 622 .PD 623 These options control whether the \s-1ELF\s0 assembler should generate common 624 symbols with the \f(CW\*(C`STT_COMMON\*(C'\fR type. The default can be controlled 625 by a configure option \fB\-\-enable\-elf\-stt\-common\fR. 626 .IP "\fB\-\-help\fR" 4 627 .IX Item "--help" 628 Print a summary of the command line options and exit. 629 .IP "\fB\-\-target\-help\fR" 4 630 .IX Item "--target-help" 631 Print a summary of all target specific options and exit. 632 .IP "\fB\-I\fR \fIdir\fR" 4 633 .IX Item "-I dir" 634 Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives. 635 .IP "\fB\-J\fR" 4 636 .IX Item "-J" 637 Don't warn about signed overflow. 638 .IP "\fB\-K\fR" 4 639 .IX Item "-K" 640 Issue warnings when difference tables altered for long displacements. 641 .IP "\fB\-L\fR" 4 642 .IX Item "-L" 643 .PD 0 644 .IP "\fB\-\-keep\-locals\fR" 4 645 .IX Item "--keep-locals" 646 .PD 647 Keep (in the symbol table) local symbols. These symbols start with 648 system-specific local label prefixes, typically \fB.L\fR for \s-1ELF\s0 systems 649 or \fBL\fR for traditional a.out systems. 650 .IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4 651 .IX Item "--listing-lhs-width=number" 652 Set the maximum width, in words, of the output data column for an assembler 653 listing to \fInumber\fR. 654 .IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4 655 .IX Item "--listing-lhs-width2=number" 656 Set the maximum width, in words, of the output data column for continuation 657 lines in an assembler listing to \fInumber\fR. 658 .IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4 659 .IX Item "--listing-rhs-width=number" 660 Set the maximum width of an input source line, as displayed in a listing, to 661 \&\fInumber\fR bytes. 662 .IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4 663 .IX Item "--listing-cont-lines=number" 664 Set the maximum number of lines printed in a listing for a single line of input 665 to \fInumber\fR + 1. 666 .IP "\fB\-\-no\-pad\-sections\fR" 4 667 .IX Item "--no-pad-sections" 668 Stop the assembler for padding the ends of output sections to the alignment 669 of that section. The default is to pad the sections, but this can waste space 670 which might be needed on targets which have tight memory constraints. 671 .IP "\fB\-o\fR \fIobjfile\fR" 4 672 .IX Item "-o objfile" 673 Name the object-file output from \fBas\fR \fIobjfile\fR. 674 .IP "\fB\-R\fR" 4 675 .IX Item "-R" 676 Fold the data section into the text section. 677 .IP "\fB\-\-hash\-size=\fR\fInumber\fR" 4 678 .IX Item "--hash-size=number" 679 Set the default size of \s-1GAS\s0's hash tables to a prime number close to 680 \&\fInumber\fR. Increasing this value can reduce the length of time it takes the 681 assembler to perform its tasks, at the expense of increasing the assembler's 682 memory requirements. Similarly reducing this value can reduce the memory 683 requirements at the expense of speed. 684 .IP "\fB\-\-reduce\-memory\-overheads\fR" 4 685 .IX Item "--reduce-memory-overheads" 686 This option reduces \s-1GAS\s0's memory requirements, at the expense of making the 687 assembly processes slower. Currently this switch is a synonym for 688 \&\fB\-\-hash\-size=4051\fR, but in the future it may have other effects as well. 689 .IP "\fB\-\-sectname\-subst\fR" 4 690 .IX Item "--sectname-subst" 691 Honor substitution sequences in section names. 692 .IP "\fB\-\-statistics\fR" 4 693 .IX Item "--statistics" 694 Print the maximum space (in bytes) and total time (in seconds) used by 695 assembly. 696 .IP "\fB\-\-strip\-local\-absolute\fR" 4 697 .IX Item "--strip-local-absolute" 698 Remove local absolute symbols from the outgoing symbol table. 699 .IP "\fB\-v\fR" 4 700 .IX Item "-v" 701 .PD 0 702 .IP "\fB\-version\fR" 4 703 .IX Item "-version" 704 .PD 705 Print the \fBas\fR version. 706 .IP "\fB\-\-version\fR" 4 707 .IX Item "--version" 708 Print the \fBas\fR version and exit. 709 .IP "\fB\-W\fR" 4 710 .IX Item "-W" 711 .PD 0 712 .IP "\fB\-\-no\-warn\fR" 4 713 .IX Item "--no-warn" 714 .PD 715 Suppress warning messages. 716 .IP "\fB\-\-fatal\-warnings\fR" 4 717 .IX Item "--fatal-warnings" 718 Treat warnings as errors. 719 .IP "\fB\-\-warn\fR" 4 720 .IX Item "--warn" 721 Don't suppress warning messages or treat them as errors. 722 .IP "\fB\-w\fR" 4 723 .IX Item "-w" 724 Ignored. 725 .IP "\fB\-x\fR" 4 726 .IX Item "-x" 727 Ignored. 728 .IP "\fB\-Z\fR" 4 729 .IX Item "-Z" 730 Generate an object file even after errors. 731 .IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4 732 .IX Item "-- | files ..." 733 Standard input, or source files to assemble. 734 .PP 735 The following options are available when as is configured for the 736 64\-bit mode of the \s-1ARM\s0 Architecture (AArch64). 737 .IP "\fB\-EB\fR" 4 738 .IX Item "-EB" 739 This option specifies that the output generated by the assembler should 740 be marked as being encoded for a big-endian processor. 741 .IP "\fB\-EL\fR" 4 742 .IX Item "-EL" 743 This option specifies that the output generated by the assembler should 744 be marked as being encoded for a little-endian processor. 745 .IP "\fB\-mabi=\fR\fIabi\fR" 4 746 .IX Item "-mabi=abi" 747 Specify which \s-1ABI\s0 the source code uses. The recognized arguments 748 are: \f(CW\*(C`ilp32\*(C'\fR and \f(CW\*(C`lp64\*(C'\fR, which decides the generated object 749 file in \s-1ELF32\s0 and \s-1ELF64\s0 format respectively. The default is \f(CW\*(C`lp64\*(C'\fR. 750 .IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 751 .IX Item "-mcpu=processor[+extension...]" 752 This option specifies the target processor. The assembler will issue an error 753 message if an attempt is made to assemble an instruction which will not execute 754 on the target processor. The following processor names are recognized: 755 \&\f(CW\*(C`cortex\-a35\*(C'\fR, 756 \&\f(CW\*(C`cortex\-a53\*(C'\fR, 757 \&\f(CW\*(C`cortex\-a57\*(C'\fR, 758 \&\f(CW\*(C`cortex\-a72\*(C'\fR, 759 \&\f(CW\*(C`cortex\-a73\*(C'\fR, 760 \&\f(CW\*(C`exynos\-m1\*(C'\fR, 761 \&\f(CW\*(C`qdf24xx\*(C'\fR, 762 \&\f(CW\*(C`thunderx\*(C'\fR, 763 \&\f(CW\*(C`vulcan\*(C'\fR, 764 \&\f(CW\*(C`xgene1\*(C'\fR 765 and 766 \&\f(CW\*(C`xgene2\*(C'\fR. 767 The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept 768 instructions valid for any supported processor, including all optional 769 extensions. 770 .Sp 771 In addition to the basic instruction set, the assembler can be told to 772 accept, or restrict, various extension mnemonics that extend the 773 processor. 774 .Sp 775 If some implementations of a particular processor can have an 776 extension, then then those extensions are automatically enabled. 777 Consequently, you will not normally have to specify any additional 778 extensions. 779 .IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 780 .IX Item "-march=architecture[+extension...]" 781 This option specifies the target architecture. The assembler will 782 issue an error message if an attempt is made to assemble an 783 instruction which will not execute on the target architecture. The 784 following architecture names are recognized: \f(CW\*(C`armv8\-a\*(C'\fR, 785 \&\f(CW\*(C`armv8.1\-a\*(C'\fR and \f(CW\*(C`armv8.2\-a\*(C'\fR. 786 .Sp 787 If both \fB\-mcpu\fR and \fB\-march\fR are specified, the 788 assembler will use the setting for \fB\-mcpu\fR. If neither are 789 specified, the assembler will default to \fB\-mcpu=all\fR. 790 .Sp 791 The architecture option can be extended with the same instruction set 792 extension options as the \fB\-mcpu\fR option. Unlike 793 \&\fB\-mcpu\fR, extensions are not always enabled by default, 794 .IP "\fB\-mverbose\-error\fR" 4 795 .IX Item "-mverbose-error" 796 This option enables verbose error messages for AArch64 gas. This option 797 is enabled by default. 798 .IP "\fB\-mno\-verbose\-error\fR" 4 799 .IX Item "-mno-verbose-error" 800 This option disables verbose error messages in AArch64 gas. 801 .PP 802 The following options are available when as is configured for an Alpha 803 processor. 804 .IP "\fB\-m\fR\fIcpu\fR" 4 805 .IX Item "-mcpu" 806 This option specifies the target processor. If an attempt is made to 807 assemble an instruction which will not execute on the target processor, 808 the assembler may either expand the instruction as a macro or issue an 809 error message. This option is equivalent to the \f(CW\*(C`.arch\*(C'\fR directive. 810 .Sp 811 The following processor names are recognized: 812 \&\f(CW21064\fR, 813 \&\f(CW\*(C`21064a\*(C'\fR, 814 \&\f(CW21066\fR, 815 \&\f(CW21068\fR, 816 \&\f(CW21164\fR, 817 \&\f(CW\*(C`21164a\*(C'\fR, 818 \&\f(CW\*(C`21164pc\*(C'\fR, 819 \&\f(CW21264\fR, 820 \&\f(CW\*(C`21264a\*(C'\fR, 821 \&\f(CW\*(C`21264b\*(C'\fR, 822 \&\f(CW\*(C`ev4\*(C'\fR, 823 \&\f(CW\*(C`ev5\*(C'\fR, 824 \&\f(CW\*(C`lca45\*(C'\fR, 825 \&\f(CW\*(C`ev5\*(C'\fR, 826 \&\f(CW\*(C`ev56\*(C'\fR, 827 \&\f(CW\*(C`pca56\*(C'\fR, 828 \&\f(CW\*(C`ev6\*(C'\fR, 829 \&\f(CW\*(C`ev67\*(C'\fR, 830 \&\f(CW\*(C`ev68\*(C'\fR. 831 The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept 832 instructions valid for any Alpha processor. 833 .Sp 834 In order to support existing practice in \s-1OSF/1\s0 with respect to \f(CW\*(C`.arch\*(C'\fR, 835 and existing practice within \fB\s-1MILO\s0\fR (the Linux \s-1ARC\s0 bootloader), the 836 numbered processor names (e.g. 21064) enable the processor-specific PALcode 837 instructions, while the \*(L"electro-vlasic\*(R" names (e.g. \f(CW\*(C`ev4\*(C'\fR) do not. 838 .IP "\fB\-mdebug\fR" 4 839 .IX Item "-mdebug" 840 .PD 0 841 .IP "\fB\-no\-mdebug\fR" 4 842 .IX Item "-no-mdebug" 843 .PD 844 Enables or disables the generation of \f(CW\*(C`.mdebug\*(C'\fR encapsulation for 845 stabs directives and procedure descriptors. The default is to automatically 846 enable \f(CW\*(C`.mdebug\*(C'\fR when the first stabs directive is seen. 847 .IP "\fB\-relax\fR" 4 848 .IX Item "-relax" 849 This option forces all relocations to be put into the object file, instead 850 of saving space and resolving some relocations at assembly time. Note that 851 this option does not propagate all symbol arithmetic into the object file, 852 because not all symbol arithmetic can be represented. However, the option 853 can still be useful in specific applications. 854 .IP "\fB\-replace\fR" 4 855 .IX Item "-replace" 856 .PD 0 857 .IP "\fB\-noreplace\fR" 4 858 .IX Item "-noreplace" 859 .PD 860 Enables or disables the optimization of procedure calls, both at assemblage 861 and at link time. These options are only available for \s-1VMS\s0 targets and 862 \&\f(CW\*(C`\-replace\*(C'\fR is the default. See section 1.4.1 of the OpenVMS Linker 863 Utility Manual. 864 .IP "\fB\-g\fR" 4 865 .IX Item "-g" 866 This option is used when the compiler generates debug information. When 867 \&\fBgcc\fR is using \fBmips-tfile\fR to generate debug 868 information for \s-1ECOFF,\s0 local labels must be passed through to the object 869 file. Otherwise this option has no effect. 870 .IP "\fB\-G\fR\fIsize\fR" 4 871 .IX Item "-Gsize" 872 A local common symbol larger than \fIsize\fR is placed in \f(CW\*(C`.bss\*(C'\fR, 873 while smaller symbols are placed in \f(CW\*(C`.sbss\*(C'\fR. 874 .IP "\fB\-F\fR" 4 875 .IX Item "-F" 876 .PD 0 877 .IP "\fB\-32addr\fR" 4 878 .IX Item "-32addr" 879 .PD 880 These options are ignored for backward compatibility. 881 .PP 882 The following options are available when as is configured for an \s-1ARC\s0 883 processor. 884 .IP "\fB\-mcpu=\fR\fIcpu\fR" 4 885 .IX Item "-mcpu=cpu" 886 This option selects the core processor variant. 887 .IP "\fB\-EB | \-EL\fR" 4 888 .IX Item "-EB | -EL" 889 Select either big-endian (\-EB) or little-endian (\-EL) output. 890 .IP "\fB\-mcode\-density\fR" 4 891 .IX Item "-mcode-density" 892 Enable Code Density extenssion instructions. 893 .PP 894 The following options are available when as is configured for the \s-1ARM\s0 895 processor family. 896 .IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 897 .IX Item "-mcpu=processor[+extension...]" 898 Specify which \s-1ARM\s0 processor variant is the target. 899 .IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 900 .IX Item "-march=architecture[+extension...]" 901 Specify which \s-1ARM\s0 architecture variant is used by the target. 902 .IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4 903 .IX Item "-mfpu=floating-point-format" 904 Select which Floating Point architecture is the target. 905 .IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4 906 .IX Item "-mfloat-abi=abi" 907 Select which floating point \s-1ABI\s0 is in use. 908 .IP "\fB\-mthumb\fR" 4 909 .IX Item "-mthumb" 910 Enable Thumb only instruction decoding. 911 .IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4 912 .IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant" 913 Select which procedure calling convention is in use. 914 .IP "\fB\-EB | \-EL\fR" 4 915 .IX Item "-EB | -EL" 916 Select either big-endian (\-EB) or little-endian (\-EL) output. 917 .IP "\fB\-mthumb\-interwork\fR" 4 918 .IX Item "-mthumb-interwork" 919 Specify that the code has been generated with interworking between Thumb and 920 \&\s-1ARM\s0 code in mind. 921 .IP "\fB\-mccs\fR" 4 922 .IX Item "-mccs" 923 Turns on CodeComposer Studio assembly syntax compatibility mode. 924 .IP "\fB\-k\fR" 4 925 .IX Item "-k" 926 Specify that \s-1PIC\s0 code has been generated. 927 .PP 928 The following options are available when as is configured for 929 the Blackfin processor family. 930 .IP "\fB\-mcpu=\fR\fIprocessor\fR[\fB\-\fR\fIsirevision\fR]" 4 931 .IX Item "-mcpu=processor[-sirevision]" 932 This option specifies the target processor. The optional \fIsirevision\fR 933 is not used in assembler. It's here such that \s-1GCC\s0 can easily pass down its 934 \&\f(CW\*(C`\-mcpu=\*(C'\fR option. The assembler will issue an 935 error message if an attempt is made to assemble an instruction which 936 will not execute on the target processor. The following processor names are 937 recognized: 938 \&\f(CW\*(C`bf504\*(C'\fR, 939 \&\f(CW\*(C`bf506\*(C'\fR, 940 \&\f(CW\*(C`bf512\*(C'\fR, 941 \&\f(CW\*(C`bf514\*(C'\fR, 942 \&\f(CW\*(C`bf516\*(C'\fR, 943 \&\f(CW\*(C`bf518\*(C'\fR, 944 \&\f(CW\*(C`bf522\*(C'\fR, 945 \&\f(CW\*(C`bf523\*(C'\fR, 946 \&\f(CW\*(C`bf524\*(C'\fR, 947 \&\f(CW\*(C`bf525\*(C'\fR, 948 \&\f(CW\*(C`bf526\*(C'\fR, 949 \&\f(CW\*(C`bf527\*(C'\fR, 950 \&\f(CW\*(C`bf531\*(C'\fR, 951 \&\f(CW\*(C`bf532\*(C'\fR, 952 \&\f(CW\*(C`bf533\*(C'\fR, 953 \&\f(CW\*(C`bf534\*(C'\fR, 954 \&\f(CW\*(C`bf535\*(C'\fR (not implemented yet), 955 \&\f(CW\*(C`bf536\*(C'\fR, 956 \&\f(CW\*(C`bf537\*(C'\fR, 957 \&\f(CW\*(C`bf538\*(C'\fR, 958 \&\f(CW\*(C`bf539\*(C'\fR, 959 \&\f(CW\*(C`bf542\*(C'\fR, 960 \&\f(CW\*(C`bf542m\*(C'\fR, 961 \&\f(CW\*(C`bf544\*(C'\fR, 962 \&\f(CW\*(C`bf544m\*(C'\fR, 963 \&\f(CW\*(C`bf547\*(C'\fR, 964 \&\f(CW\*(C`bf547m\*(C'\fR, 965 \&\f(CW\*(C`bf548\*(C'\fR, 966 \&\f(CW\*(C`bf548m\*(C'\fR, 967 \&\f(CW\*(C`bf549\*(C'\fR, 968 \&\f(CW\*(C`bf549m\*(C'\fR, 969 \&\f(CW\*(C`bf561\*(C'\fR, 970 and 971 \&\f(CW\*(C`bf592\*(C'\fR. 972 .IP "\fB\-mfdpic\fR" 4 973 .IX Item "-mfdpic" 974 Assemble for the \s-1FDPIC ABI.\s0 975 .IP "\fB\-mno\-fdpic\fR" 4 976 .IX Item "-mno-fdpic" 977 .PD 0 978 .IP "\fB\-mnopic\fR" 4 979 .IX Item "-mnopic" 980 .PD 981 Disable \-mfdpic. 982 .PP 983 See the info pages for documentation of the CRIS-specific options. 984 .PP 985 The following options are available when as is configured for 986 a D10V processor. 987 .IP "\fB\-O\fR" 4 988 .IX Item "-O" 989 Optimize output by parallelizing instructions. 990 .PP 991 The following options are available when as is configured for a D30V 992 processor. 993 .IP "\fB\-O\fR" 4 994 .IX Item "-O" 995 Optimize output by parallelizing instructions. 996 .IP "\fB\-n\fR" 4 997 .IX Item "-n" 998 Warn when nops are generated. 999 .IP "\fB\-N\fR" 4 1000 .IX Item "-N" 1001 Warn when a nop after a 32\-bit multiply instruction is generated. 1002 .PP 1003 The following options are available when as is configured for 1004 an Epiphany processor. 1005 .IP "\fB\-mepiphany\fR" 4 1006 .IX Item "-mepiphany" 1007 Specifies that the both 32 and 16 bit instructions are allowed. This is the 1008 default behavior. 1009 .IP "\fB\-mepiphany16\fR" 4 1010 .IX Item "-mepiphany16" 1011 Restricts the permitted instructions to just the 16 bit set. 1012 .PP 1013 The following options are available when as is configured for an H8/300 1014 processor. 1015 \&\f(CW@chapter\fR H8/300 Dependent Features 1016 .SS "Options" 1017 .IX Subsection "Options" 1018 The Renesas H8/300 version of \f(CW\*(C`as\*(C'\fR has one 1019 machine-dependent option: 1020 .IP "\fB\-h\-tick\-hex\fR" 4 1021 .IX Item "-h-tick-hex" 1022 Support H'00 style hex constants in addition to 0x00 style. 1023 .IP "\fB\-mach=\fR\fIname\fR" 4 1024 .IX Item "-mach=name" 1025 Sets the H8300 machine variant. The following machine names 1026 are recognised: 1027 \&\f(CW\*(C`h8300h\*(C'\fR, 1028 \&\f(CW\*(C`h8300hn\*(C'\fR, 1029 \&\f(CW\*(C`h8300s\*(C'\fR, 1030 \&\f(CW\*(C`h8300sn\*(C'\fR, 1031 \&\f(CW\*(C`h8300sx\*(C'\fR and 1032 \&\f(CW\*(C`h8300sxn\*(C'\fR. 1033 .PP 1034 The following options are available when as is configured for 1035 an i386 processor. 1036 .IP "\fB\-\-32 | \-\-x32 | \-\-64\fR" 4 1037 .IX Item "--32 | --x32 | --64" 1038 Select the word size, either 32 bits or 64 bits. \fB\-\-32\fR 1039 implies Intel i386 architecture, while \fB\-\-x32\fR and \fB\-\-64\fR 1040 imply \s-1AMD\s0 x86\-64 architecture with 32\-bit or 64\-bit word-size 1041 respectively. 1042 .Sp 1043 These options are only available with the \s-1ELF\s0 object file format, and 1044 require that the necessary \s-1BFD\s0 support has been included (on a 32\-bit 1045 platform you have to add \-\-enable\-64\-bit\-bfd to configure enable 64\-bit 1046 usage and use x86\-64 as target platform). 1047 .IP "\fB\-n\fR" 4 1048 .IX Item "-n" 1049 By default, x86 \s-1GAS\s0 replaces multiple nop instructions used for 1050 alignment within code sections with multi-byte nop instructions such 1051 as leal 0(%esi,1),%esi. This switch disables the optimization. 1052 .IP "\fB\-\-divide\fR" 4 1053 .IX Item "--divide" 1054 On SVR4\-derived platforms, the character \fB/\fR is treated as a comment 1055 character, which means that it cannot be used in expressions. The 1056 \&\fB\-\-divide\fR option turns \fB/\fR into a normal character. This does 1057 not disable \fB/\fR at the beginning of a line starting a comment, or 1058 affect using \fB#\fR for starting a comment. 1059 .IP "\fB\-march=\fR\fI\s-1CPU\s0\fR\fB[+\fR\fI\s-1EXTENSION\s0\fR\fB...]\fR" 4 1060 .IX Item "-march=CPU[+EXTENSION...]" 1061 This option specifies the target processor. The assembler will 1062 issue an error message if an attempt is made to assemble an instruction 1063 which will not execute on the target processor. The following 1064 processor names are recognized: 1065 \&\f(CW\*(C`i8086\*(C'\fR, 1066 \&\f(CW\*(C`i186\*(C'\fR, 1067 \&\f(CW\*(C`i286\*(C'\fR, 1068 \&\f(CW\*(C`i386\*(C'\fR, 1069 \&\f(CW\*(C`i486\*(C'\fR, 1070 \&\f(CW\*(C`i586\*(C'\fR, 1071 \&\f(CW\*(C`i686\*(C'\fR, 1072 \&\f(CW\*(C`pentium\*(C'\fR, 1073 \&\f(CW\*(C`pentiumpro\*(C'\fR, 1074 \&\f(CW\*(C`pentiumii\*(C'\fR, 1075 \&\f(CW\*(C`pentiumiii\*(C'\fR, 1076 \&\f(CW\*(C`pentium4\*(C'\fR, 1077 \&\f(CW\*(C`prescott\*(C'\fR, 1078 \&\f(CW\*(C`nocona\*(C'\fR, 1079 \&\f(CW\*(C`core\*(C'\fR, 1080 \&\f(CW\*(C`core2\*(C'\fR, 1081 \&\f(CW\*(C`corei7\*(C'\fR, 1082 \&\f(CW\*(C`l1om\*(C'\fR, 1083 \&\f(CW\*(C`k1om\*(C'\fR, 1084 \&\f(CW\*(C`iamcu\*(C'\fR, 1085 \&\f(CW\*(C`k6\*(C'\fR, 1086 \&\f(CW\*(C`k6_2\*(C'\fR, 1087 \&\f(CW\*(C`athlon\*(C'\fR, 1088 \&\f(CW\*(C`opteron\*(C'\fR, 1089 \&\f(CW\*(C`k8\*(C'\fR, 1090 \&\f(CW\*(C`amdfam10\*(C'\fR, 1091 \&\f(CW\*(C`bdver1\*(C'\fR, 1092 \&\f(CW\*(C`bdver2\*(C'\fR, 1093 \&\f(CW\*(C`bdver3\*(C'\fR, 1094 \&\f(CW\*(C`bdver4\*(C'\fR, 1095 \&\f(CW\*(C`znver1\*(C'\fR, 1096 \&\f(CW\*(C`btver1\*(C'\fR, 1097 \&\f(CW\*(C`btver2\*(C'\fR, 1098 \&\f(CW\*(C`generic32\*(C'\fR and 1099 \&\f(CW\*(C`generic64\*(C'\fR. 1100 .Sp 1101 In addition to the basic instruction set, the assembler can be told to 1102 accept various extension mnemonics. For example, 1103 \&\f(CW\*(C`\-march=i686+sse4+vmx\*(C'\fR extends \fIi686\fR with \fIsse4\fR and 1104 \&\fIvmx\fR. The following extensions are currently supported: 1105 \&\f(CW8087\fR, 1106 \&\f(CW287\fR, 1107 \&\f(CW387\fR, 1108 \&\f(CW687\fR, 1109 \&\f(CW\*(C`no87\*(C'\fR, 1110 \&\f(CW\*(C`no287\*(C'\fR, 1111 \&\f(CW\*(C`no387\*(C'\fR, 1112 \&\f(CW\*(C`no687\*(C'\fR, 1113 \&\f(CW\*(C`mmx\*(C'\fR, 1114 \&\f(CW\*(C`nommx\*(C'\fR, 1115 \&\f(CW\*(C`sse\*(C'\fR, 1116 \&\f(CW\*(C`sse2\*(C'\fR, 1117 \&\f(CW\*(C`sse3\*(C'\fR, 1118 \&\f(CW\*(C`ssse3\*(C'\fR, 1119 \&\f(CW\*(C`sse4.1\*(C'\fR, 1120 \&\f(CW\*(C`sse4.2\*(C'\fR, 1121 \&\f(CW\*(C`sse4\*(C'\fR, 1122 \&\f(CW\*(C`nosse\*(C'\fR, 1123 \&\f(CW\*(C`nosse2\*(C'\fR, 1124 \&\f(CW\*(C`nosse3\*(C'\fR, 1125 \&\f(CW\*(C`nossse3\*(C'\fR, 1126 \&\f(CW\*(C`nosse4.1\*(C'\fR, 1127 \&\f(CW\*(C`nosse4.2\*(C'\fR, 1128 \&\f(CW\*(C`nosse4\*(C'\fR, 1129 \&\f(CW\*(C`avx\*(C'\fR, 1130 \&\f(CW\*(C`avx2\*(C'\fR, 1131 \&\f(CW\*(C`noavx\*(C'\fR, 1132 \&\f(CW\*(C`noavx2\*(C'\fR, 1133 \&\f(CW\*(C`adx\*(C'\fR, 1134 \&\f(CW\*(C`rdseed\*(C'\fR, 1135 \&\f(CW\*(C`prfchw\*(C'\fR, 1136 \&\f(CW\*(C`smap\*(C'\fR, 1137 \&\f(CW\*(C`mpx\*(C'\fR, 1138 \&\f(CW\*(C`sha\*(C'\fR, 1139 \&\f(CW\*(C`rdpid\*(C'\fR, 1140 \&\f(CW\*(C`prefetchwt1\*(C'\fR, 1141 \&\f(CW\*(C`clflushopt\*(C'\fR, 1142 \&\f(CW\*(C`se1\*(C'\fR, 1143 \&\f(CW\*(C`clwb\*(C'\fR, 1144 \&\f(CW\*(C`pcommit\*(C'\fR, 1145 \&\f(CW\*(C`avx512f\*(C'\fR, 1146 \&\f(CW\*(C`avx512cd\*(C'\fR, 1147 \&\f(CW\*(C`avx512er\*(C'\fR, 1148 \&\f(CW\*(C`avx512pf\*(C'\fR, 1149 \&\f(CW\*(C`avx512vl\*(C'\fR, 1150 \&\f(CW\*(C`avx512bw\*(C'\fR, 1151 \&\f(CW\*(C`avx512dq\*(C'\fR, 1152 \&\f(CW\*(C`avx512ifma\*(C'\fR, 1153 \&\f(CW\*(C`avx512vbmi\*(C'\fR, 1154 \&\f(CW\*(C`noavx512f\*(C'\fR, 1155 \&\f(CW\*(C`noavx512cd\*(C'\fR, 1156 \&\f(CW\*(C`noavx512er\*(C'\fR, 1157 \&\f(CW\*(C`noavx512pf\*(C'\fR, 1158 \&\f(CW\*(C`noavx512vl\*(C'\fR, 1159 \&\f(CW\*(C`noavx512bw\*(C'\fR, 1160 \&\f(CW\*(C`noavx512dq\*(C'\fR, 1161 \&\f(CW\*(C`noavx512ifma\*(C'\fR, 1162 \&\f(CW\*(C`noavx512vbmi\*(C'\fR, 1163 \&\f(CW\*(C`vmx\*(C'\fR, 1164 \&\f(CW\*(C`vmfunc\*(C'\fR, 1165 \&\f(CW\*(C`smx\*(C'\fR, 1166 \&\f(CW\*(C`xsave\*(C'\fR, 1167 \&\f(CW\*(C`xsaveopt\*(C'\fR, 1168 \&\f(CW\*(C`xsavec\*(C'\fR, 1169 \&\f(CW\*(C`xsaves\*(C'\fR, 1170 \&\f(CW\*(C`aes\*(C'\fR, 1171 \&\f(CW\*(C`pclmul\*(C'\fR, 1172 \&\f(CW\*(C`fsgsbase\*(C'\fR, 1173 \&\f(CW\*(C`rdrnd\*(C'\fR, 1174 \&\f(CW\*(C`f16c\*(C'\fR, 1175 \&\f(CW\*(C`bmi2\*(C'\fR, 1176 \&\f(CW\*(C`fma\*(C'\fR, 1177 \&\f(CW\*(C`movbe\*(C'\fR, 1178 \&\f(CW\*(C`ept\*(C'\fR, 1179 \&\f(CW\*(C`lzcnt\*(C'\fR, 1180 \&\f(CW\*(C`hle\*(C'\fR, 1181 \&\f(CW\*(C`rtm\*(C'\fR, 1182 \&\f(CW\*(C`invpcid\*(C'\fR, 1183 \&\f(CW\*(C`clflush\*(C'\fR, 1184 \&\f(CW\*(C`mwaitx\*(C'\fR, 1185 \&\f(CW\*(C`clzero\*(C'\fR, 1186 \&\f(CW\*(C`lwp\*(C'\fR, 1187 \&\f(CW\*(C`fma4\*(C'\fR, 1188 \&\f(CW\*(C`xop\*(C'\fR, 1189 \&\f(CW\*(C`cx16\*(C'\fR, 1190 \&\f(CW\*(C`syscall\*(C'\fR, 1191 \&\f(CW\*(C`rdtscp\*(C'\fR, 1192 \&\f(CW\*(C`3dnow\*(C'\fR, 1193 \&\f(CW\*(C`3dnowa\*(C'\fR, 1194 \&\f(CW\*(C`sse4a\*(C'\fR, 1195 \&\f(CW\*(C`sse5\*(C'\fR, 1196 \&\f(CW\*(C`svme\*(C'\fR, 1197 \&\f(CW\*(C`abm\*(C'\fR and 1198 \&\f(CW\*(C`padlock\*(C'\fR. 1199 Note that rather than extending a basic instruction set, the extension 1200 mnemonics starting with \f(CW\*(C`no\*(C'\fR revoke the respective functionality. 1201 .Sp 1202 When the \f(CW\*(C`.arch\*(C'\fR directive is used with \fB\-march\fR, the 1203 \&\f(CW\*(C`.arch\*(C'\fR directive will take precedent. 1204 .IP "\fB\-mtune=\fR\fI\s-1CPU\s0\fR" 4 1205 .IX Item "-mtune=CPU" 1206 This option specifies a processor to optimize for. When used in 1207 conjunction with the \fB\-march\fR option, only instructions 1208 of the processor specified by the \fB\-march\fR option will be 1209 generated. 1210 .Sp 1211 Valid \fI\s-1CPU\s0\fR values are identical to the processor list of 1212 \&\fB\-march=\fR\fI\s-1CPU\s0\fR. 1213 .IP "\fB\-msse2avx\fR" 4 1214 .IX Item "-msse2avx" 1215 This option specifies that the assembler should encode \s-1SSE\s0 instructions 1216 with \s-1VEX\s0 prefix. 1217 .IP "\fB\-msse\-check=\fR\fInone\fR" 4 1218 .IX Item "-msse-check=none" 1219 .PD 0 1220 .IP "\fB\-msse\-check=\fR\fIwarning\fR" 4 1221 .IX Item "-msse-check=warning" 1222 .IP "\fB\-msse\-check=\fR\fIerror\fR" 4 1223 .IX Item "-msse-check=error" 1224 .PD 1225 These options control if the assembler should check \s-1SSE\s0 instructions. 1226 \&\fB\-msse\-check=\fR\fInone\fR will make the assembler not to check \s-1SSE\s0 1227 instructions, which is the default. \fB\-msse\-check=\fR\fIwarning\fR 1228 will make the assembler issue a warning for any \s-1SSE\s0 instruction. 1229 \&\fB\-msse\-check=\fR\fIerror\fR will make the assembler issue an error 1230 for any \s-1SSE\s0 instruction. 1231 .IP "\fB\-mavxscalar=\fR\fI128\fR" 4 1232 .IX Item "-mavxscalar=128" 1233 .PD 0 1234 .IP "\fB\-mavxscalar=\fR\fI256\fR" 4 1235 .IX Item "-mavxscalar=256" 1236 .PD 1237 These options control how the assembler should encode scalar \s-1AVX\s0 1238 instructions. \fB\-mavxscalar=\fR\fI128\fR will encode scalar 1239 \&\s-1AVX\s0 instructions with 128bit vector length, which is the default. 1240 \&\fB\-mavxscalar=\fR\fI256\fR will encode scalar \s-1AVX\s0 instructions 1241 with 256bit vector length. 1242 .IP "\fB\-mevexlig=\fR\fI128\fR" 4 1243 .IX Item "-mevexlig=128" 1244 .PD 0 1245 .IP "\fB\-mevexlig=\fR\fI256\fR" 4 1246 .IX Item "-mevexlig=256" 1247 .IP "\fB\-mevexlig=\fR\fI512\fR" 4 1248 .IX Item "-mevexlig=512" 1249 .PD 1250 These options control how the assembler should encode length-ignored 1251 (\s-1LIG\s0) \s-1EVEX\s0 instructions. \fB\-mevexlig=\fR\fI128\fR will encode \s-1LIG 1252 EVEX\s0 instructions with 128bit vector length, which is the default. 1253 \&\fB\-mevexlig=\fR\fI256\fR and \fB\-mevexlig=\fR\fI512\fR will 1254 encode \s-1LIG EVEX\s0 instructions with 256bit and 512bit vector length, 1255 respectively. 1256 .IP "\fB\-mevexwig=\fR\fI0\fR" 4 1257 .IX Item "-mevexwig=0" 1258 .PD 0 1259 .IP "\fB\-mevexwig=\fR\fI1\fR" 4 1260 .IX Item "-mevexwig=1" 1261 .PD 1262 These options control how the assembler should encode w\-ignored (\s-1WIG\s0) 1263 \&\s-1EVEX\s0 instructions. \fB\-mevexwig=\fR\fI0\fR will encode \s-1WIG 1264 EVEX\s0 instructions with evex.w = 0, which is the default. 1265 \&\fB\-mevexwig=\fR\fI1\fR will encode \s-1WIG EVEX\s0 instructions with 1266 evex.w = 1. 1267 .IP "\fB\-mmnemonic=\fR\fIatt\fR" 4 1268 .IX Item "-mmnemonic=att" 1269 .PD 0 1270 .IP "\fB\-mmnemonic=\fR\fIintel\fR" 4 1271 .IX Item "-mmnemonic=intel" 1272 .PD 1273 This option specifies instruction mnemonic for matching instructions. 1274 The \f(CW\*(C`.att_mnemonic\*(C'\fR and \f(CW\*(C`.intel_mnemonic\*(C'\fR directives will 1275 take precedent. 1276 .IP "\fB\-msyntax=\fR\fIatt\fR" 4 1277 .IX Item "-msyntax=att" 1278 .PD 0 1279 .IP "\fB\-msyntax=\fR\fIintel\fR" 4 1280 .IX Item "-msyntax=intel" 1281 .PD 1282 This option specifies instruction syntax when processing instructions. 1283 The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will 1284 take precedent. 1285 .IP "\fB\-mnaked\-reg\fR" 4 1286 .IX Item "-mnaked-reg" 1287 This opetion specifies that registers don't require a \fB%\fR prefix. 1288 The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will take precedent. 1289 .IP "\fB\-madd\-bnd\-prefix\fR" 4 1290 .IX Item "-madd-bnd-prefix" 1291 This option forces the assembler to add \s-1BND\s0 prefix to all branches, even 1292 if such prefix was not explicitly specified in the source code. 1293 .IP "\fB\-mno\-shared\fR" 4 1294 .IX Item "-mno-shared" 1295 On \s-1ELF\s0 target, the assembler normally optimizes out non-PLT relocations 1296 against defined non-weak global branch targets with default visibility. 1297 The \fB\-mshared\fR option tells the assembler to generate code which 1298 may go into a shared library where all non-weak global branch targets 1299 with default visibility can be preempted. The resulting code is 1300 slightly bigger. This option only affects the handling of branch 1301 instructions. 1302 .IP "\fB\-mbig\-obj\fR" 4 1303 .IX Item "-mbig-obj" 1304 On x86\-64 \s-1PE/COFF\s0 target this option forces the use of big object file 1305 format, which allows more than 32768 sections. 1306 .IP "\fB\-momit\-lock\-prefix=\fR\fIno\fR" 4 1307 .IX Item "-momit-lock-prefix=no" 1308 .PD 0 1309 .IP "\fB\-momit\-lock\-prefix=\fR\fIyes\fR" 4 1310 .IX Item "-momit-lock-prefix=yes" 1311 .PD 1312 These options control how the assembler should encode lock prefix. 1313 This option is intended as a workaround for processors, that fail on 1314 lock prefix. This option can only be safely used with single-core, 1315 single-thread computers 1316 \&\fB\-momit\-lock\-prefix=\fR\fIyes\fR will omit all lock prefixes. 1317 \&\fB\-momit\-lock\-prefix=\fR\fIno\fR will encode lock prefix as usual, 1318 which is the default. 1319 .IP "\fB\-mfence\-as\-lock\-add=\fR\fIno\fR" 4 1320 .IX Item "-mfence-as-lock-add=no" 1321 .PD 0 1322 .IP "\fB\-mfence\-as\-lock\-add=\fR\fIyes\fR" 4 1323 .IX Item "-mfence-as-lock-add=yes" 1324 .PD 1325 These options control how the assembler should encode lfence, mfence and 1326 sfence. 1327 \&\fB\-mfence\-as\-lock\-add=\fR\fIyes\fR will encode lfence, mfence and 1328 sfence as \fBlock addl \f(CB$0x0\fB, (%rsp)\fR in 64\-bit mode and 1329 \&\fBlock addl \f(CB$0x0\fB, (%esp)\fR in 32\-bit mode. 1330 \&\fB\-mfence\-as\-lock\-add=\fR\fIno\fR will encode lfence, mfence and 1331 sfence as usual, which is the default. 1332 .IP "\fB\-mrelax\-relocations=\fR\fIno\fR" 4 1333 .IX Item "-mrelax-relocations=no" 1334 .PD 0 1335 .IP "\fB\-mrelax\-relocations=\fR\fIyes\fR" 4 1336 .IX Item "-mrelax-relocations=yes" 1337 .PD 1338 These options control whether the assembler should generate relax 1339 relocations, R_386_GOT32X, in 32\-bit mode, or R_X86_64_GOTPCRELX and 1340 R_X86_64_REX_GOTPCRELX, in 64\-bit mode. 1341 \&\fB\-mrelax\-relocations=\fR\fIyes\fR will generate relax relocations. 1342 \&\fB\-mrelax\-relocations=\fR\fIno\fR will not generate relax 1343 relocations. The default can be controlled by a configure option 1344 \&\fB\-\-enable\-x86\-relax\-relocations\fR. 1345 .IP "\fB\-mevexrcig=\fR\fIrne\fR" 4 1346 .IX Item "-mevexrcig=rne" 1347 .PD 0 1348 .IP "\fB\-mevexrcig=\fR\fIrd\fR" 4 1349 .IX Item "-mevexrcig=rd" 1350 .IP "\fB\-mevexrcig=\fR\fIru\fR" 4 1351 .IX Item "-mevexrcig=ru" 1352 .IP "\fB\-mevexrcig=\fR\fIrz\fR" 4 1353 .IX Item "-mevexrcig=rz" 1354 .PD 1355 These options control how the assembler should encode SAE-only 1356 \&\s-1EVEX\s0 instructions. \fB\-mevexrcig=\fR\fIrne\fR will encode \s-1RC\s0 bits 1357 of \s-1EVEX\s0 instruction with 00, which is the default. 1358 \&\fB\-mevexrcig=\fR\fIrd\fR, \fB\-mevexrcig=\fR\fIru\fR 1359 and \fB\-mevexrcig=\fR\fIrz\fR will encode SAE-only \s-1EVEX\s0 instructions 1360 with 01, 10 and 11 \s-1RC\s0 bits, respectively. 1361 .IP "\fB\-mamd64\fR" 4 1362 .IX Item "-mamd64" 1363 .PD 0 1364 .IP "\fB\-mintel64\fR" 4 1365 .IX Item "-mintel64" 1366 .PD 1367 This option specifies that the assembler should accept only \s-1AMD64\s0 or 1368 Intel64 \s-1ISA\s0 in 64\-bit mode. The default is to accept both. 1369 .PP 1370 The following options are available when as is configured for the 1371 Intel 80960 processor. 1372 .IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4 1373 .IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC" 1374 Specify which variant of the 960 architecture is the target. 1375 .IP "\fB\-b\fR" 4 1376 .IX Item "-b" 1377 Add code to collect statistics about branches taken. 1378 .IP "\fB\-no\-relax\fR" 4 1379 .IX Item "-no-relax" 1380 Do not alter compare-and-branch instructions for long displacements; 1381 error if necessary. 1382 .PP 1383 The following options are available when as is configured for the 1384 Ubicom \s-1IP2K\s0 series. 1385 .IP "\fB\-mip2022ext\fR" 4 1386 .IX Item "-mip2022ext" 1387 Specifies that the extended \s-1IP2022\s0 instructions are allowed. 1388 .IP "\fB\-mip2022\fR" 4 1389 .IX Item "-mip2022" 1390 Restores the default behaviour, which restricts the permitted instructions to 1391 just the basic \s-1IP2022\s0 ones. 1392 .PP 1393 The following options are available when as is configured for the 1394 Renesas M32C and M16C processors. 1395 .IP "\fB\-m32c\fR" 4 1396 .IX Item "-m32c" 1397 Assemble M32C instructions. 1398 .IP "\fB\-m16c\fR" 4 1399 .IX Item "-m16c" 1400 Assemble M16C instructions (the default). 1401 .IP "\fB\-relax\fR" 4 1402 .IX Item "-relax" 1403 Enable support for link-time relaxations. 1404 .IP "\fB\-h\-tick\-hex\fR" 4 1405 .IX Item "-h-tick-hex" 1406 Support H'00 style hex constants in addition to 0x00 style. 1407 .PP 1408 The following options are available when as is configured for the 1409 Renesas M32R (formerly Mitsubishi M32R) series. 1410 .IP "\fB\-\-m32rx\fR" 4 1411 .IX Item "--m32rx" 1412 Specify which processor in the M32R family is the target. The default 1413 is normally the M32R, but this option changes it to the M32RX. 1414 .IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4 1415 .IX Item "--warn-explicit-parallel-conflicts or --Wp" 1416 Produce warning messages when questionable parallel constructs are 1417 encountered. 1418 .IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4 1419 .IX Item "--no-warn-explicit-parallel-conflicts or --Wnp" 1420 Do not produce warning messages when questionable parallel constructs are 1421 encountered. 1422 .PP 1423 The following options are available when as is configured for the 1424 Motorola 68000 series. 1425 .IP "\fB\-l\fR" 4 1426 .IX Item "-l" 1427 Shorten references to undefined symbols, to one word instead of two. 1428 .IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4 1429 .IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030" 1430 .PD 0 1431 .IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4 1432 .IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332" 1433 .IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4 1434 .IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200" 1435 .PD 1436 Specify what processor in the 68000 family is the target. The default 1437 is normally the 68020, but this can be changed at configuration time. 1438 .IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4 1439 .IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882" 1440 The target machine does (or does not) have a floating-point coprocessor. 1441 The default is to assume a coprocessor for 68020, 68030, and cpu32. Although 1442 the basic 68000 is not compatible with the 68881, a combination of the 1443 two can be specified, since it's possible to do emulation of the 1444 coprocessor instructions with the main processor. 1445 .IP "\fB\-m68851 | \-mno\-68851\fR" 4 1446 .IX Item "-m68851 | -mno-68851" 1447 The target machine does (or does not) have a memory-management 1448 unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up. 1449 .PP 1450 The following options are available when as is configured for an 1451 Altera Nios \s-1II\s0 processor. 1452 .IP "\fB\-relax\-section\fR" 4 1453 .IX Item "-relax-section" 1454 Replace identified out-of-range branches with PC-relative \f(CW\*(C`jmp\*(C'\fR 1455 sequences when possible. The generated code sequences are suitable 1456 for use in position-independent code, but there is a practical limit 1457 on the extended branch range because of the length of the sequences. 1458 This option is the default. 1459 .IP "\fB\-relax\-all\fR" 4 1460 .IX Item "-relax-all" 1461 Replace branch instructions not determinable to be in range 1462 and all call instructions with \f(CW\*(C`jmp\*(C'\fR and \f(CW\*(C`callr\*(C'\fR sequences 1463 (respectively). This option generates absolute relocations against the 1464 target symbols and is not appropriate for position-independent code. 1465 .IP "\fB\-no\-relax\fR" 4 1466 .IX Item "-no-relax" 1467 Do not replace any branches or calls. 1468 .IP "\fB\-EB\fR" 4 1469 .IX Item "-EB" 1470 Generate big-endian output. 1471 .IP "\fB\-EL\fR" 4 1472 .IX Item "-EL" 1473 Generate little-endian output. This is the default. 1474 .IP "\fB\-march=\fR\fIarchitecture\fR" 4 1475 .IX Item "-march=architecture" 1476 This option specifies the target architecture. The assembler issues 1477 an error message if an attempt is made to assemble an instruction which 1478 will not execute on the target architecture. The following architecture 1479 names are recognized: 1480 \&\f(CW\*(C`r1\*(C'\fR, 1481 \&\f(CW\*(C`r2\*(C'\fR. 1482 The default is \f(CW\*(C`r1\*(C'\fR. 1483 .PP 1484 The following options are available when as is configured for a 1485 Meta processor. 1486 .ie n .IP """\-mcpu=metac11""" 4 1487 .el .IP "\f(CW\-mcpu=metac11\fR" 4 1488 .IX Item "-mcpu=metac11" 1489 Generate code for Meta 1.1. 1490 .ie n .IP """\-mcpu=metac12""" 4 1491 .el .IP "\f(CW\-mcpu=metac12\fR" 4 1492 .IX Item "-mcpu=metac12" 1493 Generate code for Meta 1.2. 1494 .ie n .IP """\-mcpu=metac21""" 4 1495 .el .IP "\f(CW\-mcpu=metac21\fR" 4 1496 .IX Item "-mcpu=metac21" 1497 Generate code for Meta 2.1. 1498 .ie n .IP """\-mfpu=metac21""" 4 1499 .el .IP "\f(CW\-mfpu=metac21\fR" 4 1500 .IX Item "-mfpu=metac21" 1501 Allow code to use \s-1FPU\s0 hardware of Meta 2.1. 1502 .PP 1503 See the info pages for documentation of the MMIX-specific options. 1504 .PP 1505 The following options are available when as is configured for a 1506 \&\s-1NDS32\s0 processor. 1507 .ie n .IP """\-O1""" 4 1508 .el .IP "\f(CW\-O1\fR" 4 1509 .IX Item "-O1" 1510 Optimize for performance. 1511 .ie n .IP """\-Os""" 4 1512 .el .IP "\f(CW\-Os\fR" 4 1513 .IX Item "-Os" 1514 Optimize for space. 1515 .ie n .IP """\-EL""" 4 1516 .el .IP "\f(CW\-EL\fR" 4 1517 .IX Item "-EL" 1518 Produce little endian data output. 1519 .ie n .IP """\-EB""" 4 1520 .el .IP "\f(CW\-EB\fR" 4 1521 .IX Item "-EB" 1522 Produce little endian data output. 1523 .ie n .IP """\-mpic""" 4 1524 .el .IP "\f(CW\-mpic\fR" 4 1525 .IX Item "-mpic" 1526 Generate \s-1PIC.\s0 1527 .ie n .IP """\-mno\-fp\-as\-gp\-relax""" 4 1528 .el .IP "\f(CW\-mno\-fp\-as\-gp\-relax\fR" 4 1529 .IX Item "-mno-fp-as-gp-relax" 1530 Suppress fp-as-gp relaxation for this file. 1531 .ie n .IP """\-mb2bb\-relax""" 4 1532 .el .IP "\f(CW\-mb2bb\-relax\fR" 4 1533 .IX Item "-mb2bb-relax" 1534 Back-to-back branch optimization. 1535 .ie n .IP """\-mno\-all\-relax""" 4 1536 .el .IP "\f(CW\-mno\-all\-relax\fR" 4 1537 .IX Item "-mno-all-relax" 1538 Suppress all relaxation for this file. 1539 .ie n .IP """\-march=<arch name>""" 4 1540 .el .IP "\f(CW\-march=<arch name>\fR" 4 1541 .IX Item "-march=<arch name>" 1542 Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f, 1543 v3s, v2, v2j, v2f, v2s. 1544 .ie n .IP """\-mbaseline=<baseline>""" 4 1545 .el .IP "\f(CW\-mbaseline=<baseline>\fR" 4 1546 .IX Item "-mbaseline=<baseline>" 1547 Assemble for baseline <baseline> which could be v2, v3, v3m. 1548 .ie n .IP """\-mfpu\-freg=\f(CIFREG\f(CW""" 4 1549 .el .IP "\f(CW\-mfpu\-freg=\f(CIFREG\f(CW\fR" 4 1550 .IX Item "-mfpu-freg=FREG" 1551 Specify a \s-1FPU\s0 configuration. 1552 .RS 4 1553 .ie n .IP """0 8 SP / 4 DP registers""" 4 1554 .el .IP "\f(CW0 8 SP / 4 DP registers\fR" 4 1555 .IX Item "0 8 SP / 4 DP registers" 1556 .PD 0 1557 .ie n .IP """1 16 SP / 8 DP registers""" 4 1558 .el .IP "\f(CW1 16 SP / 8 DP registers\fR" 4 1559 .IX Item "1 16 SP / 8 DP registers" 1560 .ie n .IP """2 32 SP / 16 DP registers""" 4 1561 .el .IP "\f(CW2 32 SP / 16 DP registers\fR" 4 1562 .IX Item "2 32 SP / 16 DP registers" 1563 .ie n .IP """3 32 SP / 32 DP registers""" 4 1564 .el .IP "\f(CW3 32 SP / 32 DP registers\fR" 4 1565 .IX Item "3 32 SP / 32 DP registers" 1566 .RE 1567 .RS 4 1568 .RE 1569 .ie n .IP """\-mabi=\f(CIabi\f(CW""" 4 1570 .el .IP "\f(CW\-mabi=\f(CIabi\f(CW\fR" 4 1571 .IX Item "-mabi=abi" 1572 .PD 1573 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp. 1574 .ie n .IP """\-m[no\-]mac""" 4 1575 .el .IP "\f(CW\-m[no\-]mac\fR" 4 1576 .IX Item "-m[no-]mac" 1577 Enable/Disable Multiply instructions support. 1578 .ie n .IP """\-m[no\-]div""" 4 1579 .el .IP "\f(CW\-m[no\-]div\fR" 4 1580 .IX Item "-m[no-]div" 1581 Enable/Disable Divide instructions support. 1582 .ie n .IP """\-m[no\-]16bit\-ext""" 4 1583 .el .IP "\f(CW\-m[no\-]16bit\-ext\fR" 4 1584 .IX Item "-m[no-]16bit-ext" 1585 Enable/Disable 16\-bit extension 1586 .ie n .IP """\-m[no\-]dx\-regs""" 4 1587 .el .IP "\f(CW\-m[no\-]dx\-regs\fR" 4 1588 .IX Item "-m[no-]dx-regs" 1589 Enable/Disable d0/d1 registers 1590 .ie n .IP """\-m[no\-]perf\-ext""" 4 1591 .el .IP "\f(CW\-m[no\-]perf\-ext\fR" 4 1592 .IX Item "-m[no-]perf-ext" 1593 Enable/Disable Performance extension 1594 .ie n .IP """\-m[no\-]perf2\-ext""" 4 1595 .el .IP "\f(CW\-m[no\-]perf2\-ext\fR" 4 1596 .IX Item "-m[no-]perf2-ext" 1597 Enable/Disable Performance extension 2 1598 .ie n .IP """\-m[no\-]string\-ext""" 4 1599 .el .IP "\f(CW\-m[no\-]string\-ext\fR" 4 1600 .IX Item "-m[no-]string-ext" 1601 Enable/Disable String extension 1602 .ie n .IP """\-m[no\-]reduced\-regs""" 4 1603 .el .IP "\f(CW\-m[no\-]reduced\-regs\fR" 4 1604 .IX Item "-m[no-]reduced-regs" 1605 Enable/Disable Reduced Register configuration (\s-1GPR16\s0) option 1606 .ie n .IP """\-m[no\-]audio\-isa\-ext""" 4 1607 .el .IP "\f(CW\-m[no\-]audio\-isa\-ext\fR" 4 1608 .IX Item "-m[no-]audio-isa-ext" 1609 Enable/Disable \s-1AUDIO ISA\s0 extension 1610 .ie n .IP """\-m[no\-]fpu\-sp\-ext""" 4 1611 .el .IP "\f(CW\-m[no\-]fpu\-sp\-ext\fR" 4 1612 .IX Item "-m[no-]fpu-sp-ext" 1613 Enable/Disable \s-1FPU SP\s0 extension 1614 .ie n .IP """\-m[no\-]fpu\-dp\-ext""" 4 1615 .el .IP "\f(CW\-m[no\-]fpu\-dp\-ext\fR" 4 1616 .IX Item "-m[no-]fpu-dp-ext" 1617 Enable/Disable \s-1FPU DP\s0 extension 1618 .ie n .IP """\-m[no\-]fpu\-fma""" 4 1619 .el .IP "\f(CW\-m[no\-]fpu\-fma\fR" 4 1620 .IX Item "-m[no-]fpu-fma" 1621 Enable/Disable \s-1FPU\s0 fused-multiply-add instructions 1622 .ie n .IP """\-mall\-ext""" 4 1623 .el .IP "\f(CW\-mall\-ext\fR" 4 1624 .IX Item "-mall-ext" 1625 Turn on all extensions and instructions support 1626 .PP 1627 The following options are available when as is configured for a 1628 PowerPC processor. 1629 .IP "\fB\-a32\fR" 4 1630 .IX Item "-a32" 1631 Generate \s-1ELF32\s0 or \s-1XCOFF32.\s0 1632 .IP "\fB\-a64\fR" 4 1633 .IX Item "-a64" 1634 Generate \s-1ELF64\s0 or \s-1XCOFF64.\s0 1635 .IP "\fB\-K \s-1PIC\s0\fR" 4 1636 .IX Item "-K PIC" 1637 Set \s-1EF_PPC_RELOCATABLE_LIB\s0 in \s-1ELF\s0 flags. 1638 .IP "\fB\-mpwrx | \-mpwr2\fR" 4 1639 .IX Item "-mpwrx | -mpwr2" 1640 Generate code for \s-1POWER/2 \s0(\s-1RIOS2\s0). 1641 .IP "\fB\-mpwr\fR" 4 1642 .IX Item "-mpwr" 1643 Generate code for \s-1POWER \s0(\s-1RIOS1\s0) 1644 .IP "\fB\-m601\fR" 4 1645 .IX Item "-m601" 1646 Generate code for PowerPC 601. 1647 .IP "\fB\-mppc, \-mppc32, \-m603, \-m604\fR" 4 1648 .IX Item "-mppc, -mppc32, -m603, -m604" 1649 Generate code for PowerPC 603/604. 1650 .IP "\fB\-m403, \-m405\fR" 4 1651 .IX Item "-m403, -m405" 1652 Generate code for PowerPC 403/405. 1653 .IP "\fB\-m440\fR" 4 1654 .IX Item "-m440" 1655 Generate code for PowerPC 440. BookE and some 405 instructions. 1656 .IP "\fB\-m464\fR" 4 1657 .IX Item "-m464" 1658 Generate code for PowerPC 464. 1659 .IP "\fB\-m476\fR" 4 1660 .IX Item "-m476" 1661 Generate code for PowerPC 476. 1662 .IP "\fB\-m7400, \-m7410, \-m7450, \-m7455\fR" 4 1663 .IX Item "-m7400, -m7410, -m7450, -m7455" 1664 Generate code for PowerPC 7400/7410/7450/7455. 1665 .IP "\fB\-m750cl\fR" 4 1666 .IX Item "-m750cl" 1667 Generate code for PowerPC 750CL. 1668 .IP "\fB\-m821, \-m850, \-m860\fR" 4 1669 .IX Item "-m821, -m850, -m860" 1670 Generate code for PowerPC 821/850/860. 1671 .IP "\fB\-mppc64, \-m620\fR" 4 1672 .IX Item "-mppc64, -m620" 1673 Generate code for PowerPC 620/625/630. 1674 .IP "\fB\-me500, \-me500x2\fR" 4 1675 .IX Item "-me500, -me500x2" 1676 Generate code for Motorola e500 core complex. 1677 .IP "\fB\-me500mc\fR" 4 1678 .IX Item "-me500mc" 1679 Generate code for Freescale e500mc core complex. 1680 .IP "\fB\-me500mc64\fR" 4 1681 .IX Item "-me500mc64" 1682 Generate code for Freescale e500mc64 core complex. 1683 .IP "\fB\-me5500\fR" 4 1684 .IX Item "-me5500" 1685 Generate code for Freescale e5500 core complex. 1686 .IP "\fB\-me6500\fR" 4 1687 .IX Item "-me6500" 1688 Generate code for Freescale e6500 core complex. 1689 .IP "\fB\-mspe\fR" 4 1690 .IX Item "-mspe" 1691 Generate code for Motorola \s-1SPE\s0 instructions. 1692 .IP "\fB\-mtitan\fR" 4 1693 .IX Item "-mtitan" 1694 Generate code for AppliedMicro Titan core complex. 1695 .IP "\fB\-mppc64bridge\fR" 4 1696 .IX Item "-mppc64bridge" 1697 Generate code for PowerPC 64, including bridge insns. 1698 .IP "\fB\-mbooke\fR" 4 1699 .IX Item "-mbooke" 1700 Generate code for 32\-bit BookE. 1701 .IP "\fB\-ma2\fR" 4 1702 .IX Item "-ma2" 1703 Generate code for A2 architecture. 1704 .IP "\fB\-me300\fR" 4 1705 .IX Item "-me300" 1706 Generate code for PowerPC e300 family. 1707 .IP "\fB\-maltivec\fR" 4 1708 .IX Item "-maltivec" 1709 Generate code for processors with AltiVec instructions. 1710 .IP "\fB\-mvle\fR" 4 1711 .IX Item "-mvle" 1712 Generate code for Freescale PowerPC \s-1VLE\s0 instructions. 1713 .IP "\fB\-mvsx\fR" 4 1714 .IX Item "-mvsx" 1715 Generate code for processors with Vector-Scalar (\s-1VSX\s0) instructions. 1716 .IP "\fB\-mhtm\fR" 4 1717 .IX Item "-mhtm" 1718 Generate code for processors with Hardware Transactional Memory instructions. 1719 .IP "\fB\-mpower4, \-mpwr4\fR" 4 1720 .IX Item "-mpower4, -mpwr4" 1721 Generate code for Power4 architecture. 1722 .IP "\fB\-mpower5, \-mpwr5, \-mpwr5x\fR" 4 1723 .IX Item "-mpower5, -mpwr5, -mpwr5x" 1724 Generate code for Power5 architecture. 1725 .IP "\fB\-mpower6, \-mpwr6\fR" 4 1726 .IX Item "-mpower6, -mpwr6" 1727 Generate code for Power6 architecture. 1728 .IP "\fB\-mpower7, \-mpwr7\fR" 4 1729 .IX Item "-mpower7, -mpwr7" 1730 Generate code for Power7 architecture. 1731 .IP "\fB\-mpower8, \-mpwr8\fR" 4 1732 .IX Item "-mpower8, -mpwr8" 1733 Generate code for Power8 architecture. 1734 .IP "\fB\-mpower9, \-mpwr9\fR" 4 1735 .IX Item "-mpower9, -mpwr9" 1736 Generate code for Power9 architecture. 1737 .IP "\fB\-mcell\fR" 4 1738 .IX Item "-mcell" 1739 .PD 0 1740 .IP "\fB\-mcell\fR" 4 1741 .IX Item "-mcell" 1742 .PD 1743 Generate code for Cell Broadband Engine architecture. 1744 .IP "\fB\-mcom\fR" 4 1745 .IX Item "-mcom" 1746 Generate code Power/PowerPC common instructions. 1747 .IP "\fB\-many\fR" 4 1748 .IX Item "-many" 1749 Generate code for any architecture (\s-1PWR/PWRX/PPC\s0). 1750 .IP "\fB\-mregnames\fR" 4 1751 .IX Item "-mregnames" 1752 Allow symbolic names for registers. 1753 .IP "\fB\-mno\-regnames\fR" 4 1754 .IX Item "-mno-regnames" 1755 Do not allow symbolic names for registers. 1756 .IP "\fB\-mrelocatable\fR" 4 1757 .IX Item "-mrelocatable" 1758 Support for \s-1GCC\s0's \-mrelocatable option. 1759 .IP "\fB\-mrelocatable\-lib\fR" 4 1760 .IX Item "-mrelocatable-lib" 1761 Support for \s-1GCC\s0's \-mrelocatable\-lib option. 1762 .IP "\fB\-memb\fR" 4 1763 .IX Item "-memb" 1764 Set \s-1PPC_EMB\s0 bit in \s-1ELF\s0 flags. 1765 .IP "\fB\-mlittle, \-mlittle\-endian, \-le\fR" 4 1766 .IX Item "-mlittle, -mlittle-endian, -le" 1767 Generate code for a little endian machine. 1768 .IP "\fB\-mbig, \-mbig\-endian, \-be\fR" 4 1769 .IX Item "-mbig, -mbig-endian, -be" 1770 Generate code for a big endian machine. 1771 .IP "\fB\-msolaris\fR" 4 1772 .IX Item "-msolaris" 1773 Generate code for Solaris. 1774 .IP "\fB\-mno\-solaris\fR" 4 1775 .IX Item "-mno-solaris" 1776 Do not generate code for Solaris. 1777 .IP "\fB\-nops=\fR\fIcount\fR" 4 1778 .IX Item "-nops=count" 1779 If an alignment directive inserts more than \fIcount\fR nops, put a 1780 branch at the beginning to skip execution of the nops. 1781 .PP 1782 See the info pages for documentation of the RX-specific options. 1783 .PP 1784 The following options are available when as is configured for the s390 1785 processor family. 1786 .IP "\fB\-m31\fR" 4 1787 .IX Item "-m31" 1788 .PD 0 1789 .IP "\fB\-m64\fR" 4 1790 .IX Item "-m64" 1791 .PD 1792 Select the word size, either 31/32 bits or 64 bits. 1793 .IP "\fB\-mesa\fR" 4 1794 .IX Item "-mesa" 1795 .PD 0 1796 .IP "\fB\-mzarch\fR" 4 1797 .IX Item "-mzarch" 1798 .PD 1799 Select the architecture mode, either the Enterprise System 1800 Architecture (esa) or the z/Architecture mode (zarch). 1801 .IP "\fB\-march=\fR\fIprocessor\fR" 4 1802 .IX Item "-march=processor" 1803 Specify which s390 processor variant is the target, \fBg6\fR, \fBg6\fR, 1804 \&\fBz900\fR, \fBz990\fR, \fBz9\-109\fR, \fBz9\-ec\fR, \fBz10\fR, 1805 \&\fBz196\fR, \fBzEC12\fR, or \fBz13\fR. 1806 .IP "\fB\-mregnames\fR" 4 1807 .IX Item "-mregnames" 1808 .PD 0 1809 .IP "\fB\-mno\-regnames\fR" 4 1810 .IX Item "-mno-regnames" 1811 .PD 1812 Allow or disallow symbolic names for registers. 1813 .IP "\fB\-mwarn\-areg\-zero\fR" 4 1814 .IX Item "-mwarn-areg-zero" 1815 Warn whenever the operand for a base or index register has been specified 1816 but evaluates to zero. 1817 .PP 1818 The following options are available when as is configured for a 1819 \&\s-1TMS320C6000\s0 processor. 1820 .IP "\fB\-march=\fR\fIarch\fR" 4 1821 .IX Item "-march=arch" 1822 Enable (only) instructions from architecture \fIarch\fR. By default, 1823 all instructions are permitted. 1824 .Sp 1825 The following values of \fIarch\fR are accepted: \f(CW\*(C`c62x\*(C'\fR, 1826 \&\f(CW\*(C`c64x\*(C'\fR, \f(CW\*(C`c64x+\*(C'\fR, \f(CW\*(C`c67x\*(C'\fR, \f(CW\*(C`c67x+\*(C'\fR, \f(CW\*(C`c674x\*(C'\fR. 1827 .IP "\fB\-mdsbt\fR" 4 1828 .IX Item "-mdsbt" 1829 .PD 0 1830 .IP "\fB\-mno\-dsbt\fR" 4 1831 .IX Item "-mno-dsbt" 1832 .PD 1833 The \fB\-mdsbt\fR option causes the assembler to generate the 1834 \&\f(CW\*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that the 1835 code is using \s-1DSBT\s0 addressing. The \fB\-mno\-dsbt\fR option, the 1836 default, causes the tag to have a value of 0, indicating that the code 1837 does not use \s-1DSBT\s0 addressing. The linker will emit a warning if 1838 objects of different type (\s-1DSBT\s0 and non-DSBT) are linked together. 1839 .IP "\fB\-mpid=no\fR" 4 1840 .IX Item "-mpid=no" 1841 .PD 0 1842 .IP "\fB\-mpid=near\fR" 4 1843 .IX Item "-mpid=near" 1844 .IP "\fB\-mpid=far\fR" 4 1845 .IX Item "-mpid=far" 1846 .PD 1847 The \fB\-mpid=\fR option causes the assembler to generate the 1848 \&\f(CW\*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of data 1849 addressing used by the code. \fB\-mpid=no\fR, the default, 1850 indicates position-dependent data addressing, \fB\-mpid=near\fR 1851 indicates position-independent addressing with \s-1GOT\s0 accesses using near 1852 \&\s-1DP\s0 addressing, and \fB\-mpid=far\fR indicates position-independent 1853 addressing with \s-1GOT\s0 accesses using far \s-1DP\s0 addressing. The linker will 1854 emit a warning if objects built with different settings of this option 1855 are linked together. 1856 .IP "\fB\-mpic\fR" 4 1857 .IX Item "-mpic" 1858 .PD 0 1859 .IP "\fB\-mno\-pic\fR" 4 1860 .IX Item "-mno-pic" 1861 .PD 1862 The \fB\-mpic\fR option causes the assembler to generate the 1863 \&\f(CW\*(C`Tag_ABI_PIC\*(C'\fR attribute with a value of 1, indicating that the 1864 code is using position-independent code addressing, The 1865 \&\f(CW\*(C`\-mno\-pic\*(C'\fR option, the default, causes the tag to have a value of 1866 0, indicating position-dependent code addressing. The linker will 1867 emit a warning if objects of different type (position-dependent and 1868 position-independent) are linked together. 1869 .IP "\fB\-mbig\-endian\fR" 4 1870 .IX Item "-mbig-endian" 1871 .PD 0 1872 .IP "\fB\-mlittle\-endian\fR" 4 1873 .IX Item "-mlittle-endian" 1874 .PD 1875 Generate code for the specified endianness. The default is 1876 little-endian. 1877 .PP 1878 The following options are available when as is configured for a TILE-Gx 1879 processor. 1880 .IP "\fB\-m32 | \-m64\fR" 4 1881 .IX Item "-m32 | -m64" 1882 Select the word size, either 32 bits or 64 bits. 1883 .IP "\fB\-EB | \-EL\fR" 4 1884 .IX Item "-EB | -EL" 1885 Select the endianness, either big-endian (\-EB) or little-endian (\-EL). 1886 .PP 1887 The following option is available when as is configured for a Visium 1888 processor. 1889 .IP "\fB\-mtune=\fR\fIarch\fR" 4 1890 .IX Item "-mtune=arch" 1891 This option specifies the target architecture. If an attempt is made to 1892 assemble an instruction that will not execute on the target architecture, 1893 the assembler will issue an error message. 1894 .Sp 1895 The following names are recognized: 1896 \&\f(CW\*(C`mcm24\*(C'\fR 1897 \&\f(CW\*(C`mcm\*(C'\fR 1898 \&\f(CW\*(C`gr5\*(C'\fR 1899 \&\f(CW\*(C`gr6\*(C'\fR 1900 .PP 1901 The following options are available when as is configured for an 1902 Xtensa processor. 1903 .IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4 1904 .IX Item "--text-section-literals | --no-text-section-literals" 1905 Control the treatment of literal pools. The default is 1906 \&\fB\-\-no\-text\-section\-literals\fR, which places literals in 1907 separate sections in the output file. This allows the literal pool to be 1908 placed in a data \s-1RAM/ROM. \s0 With \fB\-\-text\-section\-literals\fR, the 1909 literals are interspersed in the text section in order to keep them as 1910 close as possible to their references. This may be necessary for large 1911 assembly files, where the literals would otherwise be out of range of the 1912 \&\f(CW\*(C`L32R\*(C'\fR instructions in the text section. Literals are grouped into 1913 pools following \f(CW\*(C`.literal_position\*(C'\fR directives or preceding 1914 \&\f(CW\*(C`ENTRY\*(C'\fR instructions. These options only affect literals referenced 1915 via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for absolute mode 1916 \&\f(CW\*(C`L32R\*(C'\fR instructions are handled separately. 1917 .IP "\fB\-\-auto\-litpools | \-\-no\-auto\-litpools\fR" 4 1918 .IX Item "--auto-litpools | --no-auto-litpools" 1919 Control the treatment of literal pools. The default is 1920 \&\fB\-\-no\-auto\-litpools\fR, which in the absence of 1921 \&\fB\-\-text\-section\-literals\fR places literals in separate sections 1922 in the output file. This allows the literal pool to be placed in a data 1923 \&\s-1RAM/ROM. \s0 With \fB\-\-auto\-litpools\fR, the literals are interspersed 1924 in the text section in order to keep them as close as possible to their 1925 references, explicit \f(CW\*(C`.literal_position\*(C'\fR directives are not 1926 required. This may be necessary for very large functions, where single 1927 literal pool at the beginning of the function may not be reachable by 1928 \&\f(CW\*(C`L32R\*(C'\fR instructions at the end. These options only affect 1929 literals referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals 1930 for absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately. 1931 When used together with \fB\-\-text\-section\-literals\fR, 1932 \&\fB\-\-auto\-litpools\fR takes precedence. 1933 .IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4 1934 .IX Item "--absolute-literals | --no-absolute-literals" 1935 Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute 1936 or PC-relative addressing. If the processor includes the absolute 1937 addressing option, the default is to use absolute \f(CW\*(C`L32R\*(C'\fR 1938 relocations. Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR relocations 1939 can be used. 1940 .IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4 1941 .IX Item "--target-align | --no-target-align" 1942 Enable or disable automatic alignment to reduce branch penalties at some 1943 expense in code size. This optimization is enabled by default. Note 1944 that the assembler will always align instructions like \f(CW\*(C`LOOP\*(C'\fR that 1945 have fixed alignment requirements. 1946 .IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4 1947 .IX Item "--longcalls | --no-longcalls" 1948 Enable or disable transformation of call instructions to allow calls 1949 across a greater range of addresses. This option should be used when call 1950 targets can potentially be out of range. It may degrade both code size 1951 and performance, but the linker can generally optimize away the 1952 unnecessary overhead when a call ends up within range. The default is 1953 \&\fB\-\-no\-longcalls\fR. 1954 .IP "\fB\-\-transform | \-\-no\-transform\fR" 4 1955 .IX Item "--transform | --no-transform" 1956 Enable or disable all assembler transformations of Xtensa instructions, 1957 including both relaxation and optimization. The default is 1958 \&\fB\-\-transform\fR; \fB\-\-no\-transform\fR should only be used in the 1959 rare cases when the instructions must be exactly as specified in the 1960 assembly source. Using \fB\-\-no\-transform\fR causes out of range 1961 instruction operands to be errors. 1962 .IP "\fB\-\-rename\-section\fR \fIoldname\fR\fB=\fR\fInewname\fR" 4 1963 .IX Item "--rename-section oldname=newname" 1964 Rename the \fIoldname\fR section to \fInewname\fR. This option can be used 1965 multiple times to rename multiple sections. 1966 .IP "\fB\-\-trampolines | \-\-no\-trampolines\fR" 4 1967 .IX Item "--trampolines | --no-trampolines" 1968 Enable or disable transformation of jump instructions to allow jumps 1969 across a greater range of addresses. This option should be used when jump targets can 1970 potentially be out of range. In the absence of such jumps this option 1971 does not affect code size or performance. The default is 1972 \&\fB\-\-trampolines\fR. 1973 .PP 1974 The following options are available when as is configured for 1975 a Z80 family processor. 1976 .IP "\fB\-z80\fR" 4 1977 .IX Item "-z80" 1978 Assemble for Z80 processor. 1979 .IP "\fB\-r800\fR" 4 1980 .IX Item "-r800" 1981 Assemble for R800 processor. 1982 .IP "\fB\-ignore\-undocumented\-instructions\fR" 4 1983 .IX Item "-ignore-undocumented-instructions" 1984 .PD 0 1985 .IP "\fB\-Wnud\fR" 4 1986 .IX Item "-Wnud" 1987 .PD 1988 Assemble undocumented Z80 instructions that also work on R800 without warning. 1989 .IP "\fB\-ignore\-unportable\-instructions\fR" 4 1990 .IX Item "-ignore-unportable-instructions" 1991 .PD 0 1992 .IP "\fB\-Wnup\fR" 4 1993 .IX Item "-Wnup" 1994 .PD 1995 Assemble all undocumented Z80 instructions without warning. 1996 .IP "\fB\-warn\-undocumented\-instructions\fR" 4 1997 .IX Item "-warn-undocumented-instructions" 1998 .PD 0 1999 .IP "\fB\-Wud\fR" 4 2000 .IX Item "-Wud" 2001 .PD 2002 Issue a warning for undocumented Z80 instructions that also work on R800. 2003 .IP "\fB\-warn\-unportable\-instructions\fR" 4 2004 .IX Item "-warn-unportable-instructions" 2005 .PD 0 2006 .IP "\fB\-Wup\fR" 4 2007 .IX Item "-Wup" 2008 .PD 2009 Issue a warning for undocumented Z80 instructions that do not work on R800. 2010 .IP "\fB\-forbid\-undocumented\-instructions\fR" 4 2011 .IX Item "-forbid-undocumented-instructions" 2012 .PD 0 2013 .IP "\fB\-Fud\fR" 4 2014 .IX Item "-Fud" 2015 .PD 2016 Treat all undocumented instructions as errors. 2017 .IP "\fB\-forbid\-unportable\-instructions\fR" 4 2018 .IX Item "-forbid-unportable-instructions" 2019 .PD 0 2020 .IP "\fB\-Fup\fR" 4 2021 .IX Item "-Fup" 2022 .PD 2023 Treat undocumented Z80 instructions that do not work on R800 as errors. 2024 .SH "SEE ALSO" 2025 .IX Header "SEE ALSO" 2026 \&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR. 2027 .SH "COPYRIGHT" 2028 .IX Header "COPYRIGHT" 2029 Copyright (c) 1991\-2016 Free Software Foundation, Inc. 2030 .PP 2031 Permission is granted to copy, distribute and/or modify this document 2032 under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 2033 or any later version published by the Free Software Foundation; 2034 with no Invariant Sections, with no Front-Cover Texts, and with no 2035 Back-Cover Texts. A copy of the license is included in the 2036 section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".
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