| 1 | //===----------------------------------------------------------------------===//
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| 2 | //
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| 3 | // The LLVM Compiler Infrastructure
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| 4 | //
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| 5 | // This file is distributed under the University of Illinois Open Source
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| 6 | // License. See LICENSE.TXT for details.
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| 7 | //
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| 8 | //===----------------------------------------------------------------------===//
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| 9 | //
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| 10 | // This file describes the X86 instruction set, defining the instructions, and
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| 11 | // properties of the instructions which are needed for code generation, machine
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| 12 | // code emission, and analysis.
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| 13 | //
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| 14 | //===----------------------------------------------------------------------===//
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| 15 |
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| 16 | //===----------------------------------------------------------------------===//
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| 17 | // X86 specific DAG Nodes.
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| 18 | //
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| 19 |
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| 20 | def SDTIntShiftDOp: SDTypeProfile<1, 3,
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| 21 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
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| 22 | SDTCisInt<0>, SDTCisInt<3>]>;
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| 23 |
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| 24 | def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
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| 25 |
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| 26 | def SDTX86Cmov : SDTypeProfile<1, 4,
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| 27 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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| 28 | SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
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| 29 |
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| 30 | // Unary and binary operator instructions that set EFLAGS as a side-effect.
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| 31 | def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
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| 32 | [SDTCisInt<0>, SDTCisVT<1, i32>]>;
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| 33 |
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| 34 | def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
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| 35 | [SDTCisSameAs<0, 2>,
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| 36 | SDTCisSameAs<0, 3>,
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| 37 | SDTCisInt<0>, SDTCisVT<1, i32>]>;
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| 38 | def SDTX86BrCond : SDTypeProfile<0, 3,
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| 39 | [SDTCisVT<0, OtherVT>,
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| 40 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
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| 41 |
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| 42 | def SDTX86SetCC : SDTypeProfile<1, 2,
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| 43 | [SDTCisVT<0, i8>,
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| 44 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
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| 45 | def SDTX86SetCC_C : SDTypeProfile<1, 2,
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| 46 | [SDTCisInt<0>,
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| 47 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
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| 48 |
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| 49 | def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
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| 50 | SDTCisVT<2, i8>]>;
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| 51 | def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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| 52 |
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| 53 | def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
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| 54 | SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
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| 55 | def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
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| 56 |
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| 57 | def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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| 58 | def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
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| 59 | SDTCisVT<1, i32>]>;
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| 60 |
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| 61 | def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
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| 62 |
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| 63 | def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
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| 64 | SDTCisVT<1, iPTR>,
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| 65 | SDTCisVT<2, iPTR>]>;
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| 66 |
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| 67 | def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
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| 68 |
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| 69 | def SDTX86Void : SDTypeProfile<0, 0, []>;
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| 70 |
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| 71 | def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
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| 72 |
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| 73 | def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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| 74 |
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| 75 | def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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| 76 |
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| 77 | def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
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| 78 |
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| 79 | def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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| 80 |
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| 81 | def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
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| 82 |
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| 83 | def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
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| 84 | def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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| 85 |
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| 86 | def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
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| 87 | [SDNPHasChain]>;
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| 88 | def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
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| 89 | [SDNPHasChain]>;
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| 90 | def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
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| 91 | [SDNPHasChain]>;
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| 92 | def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
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| 93 | [SDNPHasChain]>;
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| 94 | def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
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| 95 | [SDNPHasChain]>;
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| 96 |
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| 97 |
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| 98 | def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
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| 99 | def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
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| 100 | def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
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| 101 | def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
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| 102 |
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| 103 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
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| 104 | def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
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| 105 |
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| 106 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
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| 107 | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
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| 108 | [SDNPHasChain]>;
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| 109 | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
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| 110 | def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
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| 111 |
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| 112 | def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
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| 113 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
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| 114 | SDNPMayLoad]>;
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| 115 | def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
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| 116 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
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| 117 | SDNPMayLoad]>;
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| 118 | def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
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| 119 | [SDNPHasChain, SDNPMayStore,
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| 120 | SDNPMayLoad, SDNPMemOperand]>;
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| 121 | def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
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| 122 | [SDNPHasChain, SDNPMayStore,
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| 123 | SDNPMayLoad, SDNPMemOperand]>;
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| 124 | def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
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| 125 | [SDNPHasChain, SDNPMayStore,
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| 126 | SDNPMayLoad, SDNPMemOperand]>;
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| 127 | def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
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| 128 | [SDNPHasChain, SDNPMayStore,
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| 129 | SDNPMayLoad, SDNPMemOperand]>;
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| 130 | def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
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| 131 | [SDNPHasChain, SDNPMayStore,
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| 132 | SDNPMayLoad, SDNPMemOperand]>;
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| 133 | def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
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| 134 | [SDNPHasChain, SDNPMayStore,
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| 135 | SDNPMayLoad, SDNPMemOperand]>;
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| 136 | def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
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| 137 | [SDNPHasChain, SDNPMayStore,
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| 138 | SDNPMayLoad, SDNPMemOperand]>;
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| 139 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
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| 140 | [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
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| 141 |
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| 142 | def X86vastart_save_xmm_regs :
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| 143 | SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
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| 144 | SDT_X86VASTART_SAVE_XMM_REGS,
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| 145 | [SDNPHasChain, SDNPVariadic]>;
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| 146 |
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| 147 | def X86callseq_start :
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| 148 | SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
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| 149 | [SDNPHasChain, SDNPOutFlag]>;
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| 150 | def X86callseq_end :
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| 151 | SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
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| 152 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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| 153 |
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| 154 | def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
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| 155 | [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
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| 156 | SDNPVariadic]>;
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| 157 |
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| 158 | def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
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| 159 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
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| 160 | def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
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| 161 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
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| 162 | SDNPMayLoad]>;
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| 163 |
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| 164 | def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
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| 165 | [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
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| 166 |
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| 167 | def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
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| 168 | def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
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| 169 |
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| 170 | def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
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| 171 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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| 172 | def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
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| 173 | SDT_X86SegmentBaseAddress, []>;
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| 174 |
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| 175 | def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
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| 176 | [SDNPHasChain]>;
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| 177 |
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| 178 | def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
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| 179 | [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
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| 180 |
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| 181 | def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
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| 182 | [SDNPCommutative]>;
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| 183 | def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
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| 184 | def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
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| 185 | [SDNPCommutative]>;
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| 186 | def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
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| 187 | [SDNPCommutative]>;
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| 188 |
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| 189 | def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
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| 190 | def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
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| 191 | def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
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| 192 | [SDNPCommutative]>;
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| 193 | def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
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| 194 | [SDNPCommutative]>;
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| 195 | def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
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| 196 | [SDNPCommutative]>;
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| 197 |
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| 198 | def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
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| 199 |
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| 200 | def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
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| 201 | [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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| 202 |
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| 203 | def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
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| 204 | []>;
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| 205 |
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| 206 | //===----------------------------------------------------------------------===//
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| 207 | // X86 Operand Definitions.
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| 208 | //
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| 209 |
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| 210 | // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
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| 211 | // the index operand of an address, to conform to x86 encoding restrictions.
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| 212 | def ptr_rc_nosp : PointerLikeRegClass<1>;
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| 213 |
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| 214 | // *mem - Operand definitions for the funky X86 addressing mode operands.
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| 215 | //
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| 216 | def X86MemAsmOperand : AsmOperandClass {
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| 217 | let Name = "Mem";
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| 218 | let SuperClasses = [];
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| 219 | }
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| 220 | def X86AbsMemAsmOperand : AsmOperandClass {
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| 221 | let Name = "AbsMem";
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| 222 | let SuperClasses = [X86MemAsmOperand];
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| 223 | }
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| 224 | class X86MemOperand<string printMethod> : Operand<iPTR> {
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| 225 | let PrintMethod = printMethod;
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| 226 | let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
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| 227 | let ParserMatchClass = X86MemAsmOperand;
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| 228 | }
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| 229 |
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| 230 | def opaque32mem : X86MemOperand<"printopaquemem">;
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| 231 | def opaque48mem : X86MemOperand<"printopaquemem">;
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| 232 | def opaque80mem : X86MemOperand<"printopaquemem">;
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| 233 | def opaque512mem : X86MemOperand<"printopaquemem">;
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| 234 |
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| 235 | def i8mem : X86MemOperand<"printi8mem">;
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| 236 | def i16mem : X86MemOperand<"printi16mem">;
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| 237 | def i32mem : X86MemOperand<"printi32mem">;
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| 238 | def i64mem : X86MemOperand<"printi64mem">;
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| 239 | def i128mem : X86MemOperand<"printi128mem">;
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| 240 | def i256mem : X86MemOperand<"printi256mem">;
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| 241 | def f32mem : X86MemOperand<"printf32mem">;
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| 242 | def f64mem : X86MemOperand<"printf64mem">;
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| 243 | def f80mem : X86MemOperand<"printf80mem">;
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| 244 | def f128mem : X86MemOperand<"printf128mem">;
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| 245 | def f256mem : X86MemOperand<"printf256mem">;
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| 246 |
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| 247 | // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
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| 248 | // plain GR64, so that it doesn't potentially require a REX prefix.
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| 249 | def i8mem_NOREX : Operand<i64> {
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| 250 | let PrintMethod = "printi8mem";
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| 251 | let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
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| 252 | let ParserMatchClass = X86MemAsmOperand;
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| 253 | }
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| 254 |
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| 255 | // Special i32mem for addresses of load folding tail calls. These are not
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| 256 | // allowed to use callee-saved registers since they must be scheduled
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| 257 | // after callee-saved register are popped.
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| 258 | def i32mem_TC : Operand<i32> {
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| 259 | let PrintMethod = "printi32mem";
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| 260 | let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
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| 261 | let ParserMatchClass = X86MemAsmOperand;
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| 262 | }
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| 263 |
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| 264 |
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| 265 | let ParserMatchClass = X86AbsMemAsmOperand,
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| 266 | PrintMethod = "print_pcrel_imm" in {
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| 267 | def i32imm_pcrel : Operand<i32>;
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| 268 | def i16imm_pcrel : Operand<i16>;
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| 269 |
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| 270 | def offset8 : Operand<i64>;
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| 271 | def offset16 : Operand<i64>;
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| 272 | def offset32 : Operand<i64>;
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| 273 | def offset64 : Operand<i64>;
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| 274 |
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| 275 | // Branch targets have OtherVT type and print as pc-relative values.
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| 276 | def brtarget : Operand<OtherVT>;
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| 277 | def brtarget8 : Operand<OtherVT>;
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| 278 |
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| 279 | }
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| 280 |
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| 281 | def SSECC : Operand<i8> {
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| 282 | let PrintMethod = "printSSECC";
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| 283 | }
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| 284 |
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| 285 | class ImmSExtAsmOperandClass : AsmOperandClass {
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| 286 | let SuperClasses = [ImmAsmOperand];
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| 287 | let RenderMethod = "addImmOperands";
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| 288 | }
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| 289 |
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| 290 | // Sign-extended immediate classes. We don't need to define the full lattice
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| 291 | // here because there is no instruction with an ambiguity between ImmSExti64i32
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| 292 | // and ImmSExti32i8.
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| 293 | //
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| 294 | // The strange ranges come from the fact that the assembler always works with
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| 295 | // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
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| 296 | // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
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| 297 |
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| 298 | // [0, 0x7FFFFFFF] |
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| 299 | // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
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| 300 | def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
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| 301 | let Name = "ImmSExti64i32";
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| 302 | }
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| 303 |
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| 304 | // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
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| 305 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
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| 306 | def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
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| 307 | let Name = "ImmSExti16i8";
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| 308 | let SuperClasses = [ImmSExti64i32AsmOperand];
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| 309 | }
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| 310 |
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| 311 | // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
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| 312 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
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| 313 | def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
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| 314 | let Name = "ImmSExti32i8";
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| 315 | }
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| 316 |
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| 317 | // [0, 0x0000007F] |
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| 318 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
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| 319 | def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
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| 320 | let Name = "ImmSExti64i8";
|
|---|
| 321 | let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
|
|---|
| 322 | ImmSExti64i32AsmOperand];
|
|---|
| 323 | }
|
|---|
| 324 |
|
|---|
| 325 | // A couple of more descriptive operand definitions.
|
|---|
| 326 | // 16-bits but only 8 bits are significant.
|
|---|
| 327 | def i16i8imm : Operand<i16> {
|
|---|
| 328 | let ParserMatchClass = ImmSExti16i8AsmOperand;
|
|---|
| 329 | }
|
|---|
| 330 | // 32-bits but only 8 bits are significant.
|
|---|
| 331 | def i32i8imm : Operand<i32> {
|
|---|
| 332 | let ParserMatchClass = ImmSExti32i8AsmOperand;
|
|---|
| 333 | }
|
|---|
| 334 |
|
|---|
| 335 | //===----------------------------------------------------------------------===//
|
|---|
| 336 | // X86 Complex Pattern Definitions.
|
|---|
| 337 | //
|
|---|
| 338 |
|
|---|
| 339 | // Define X86 specific addressing mode.
|
|---|
| 340 | def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
|
|---|
| 341 | def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
|
|---|
| 342 | [add, sub, mul, X86mul_imm, shl, or, frameindex],
|
|---|
| 343 | []>;
|
|---|
| 344 | def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
|
|---|
| 345 | [tglobaltlsaddr], []>;
|
|---|
| 346 |
|
|---|
| 347 | //===----------------------------------------------------------------------===//
|
|---|
| 348 | // X86 Instruction Predicate Definitions.
|
|---|
| 349 | def HasCMov : Predicate<"Subtarget->hasCMov()">;
|
|---|
| 350 | def NoCMov : Predicate<"!Subtarget->hasCMov()">;
|
|---|
| 351 |
|
|---|
| 352 | // FIXME: temporary hack to let codegen assert or generate poor code in case
|
|---|
| 353 | // no AVX version of the desired intructions is present, this is better for
|
|---|
| 354 | // incremental dev (without fallbacks it's easier to spot what's missing)
|
|---|
| 355 | def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
|
|---|
| 356 | def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
|
|---|
| 357 | def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
|
|---|
| 358 | def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
|
|---|
| 359 | def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
|
|---|
| 360 | def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
|
|---|
| 361 | def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
|
|---|
| 362 | def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">;
|
|---|
| 363 |
|
|---|
| 364 | def HasAVX : Predicate<"Subtarget->hasAVX()">;
|
|---|
| 365 | def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
|
|---|
| 366 | def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
|
|---|
| 367 | def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
|
|---|
| 368 | def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
|
|---|
| 369 | def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
|
|---|
| 370 | def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
|
|---|
| 371 | def In64BitMode : Predicate<"Subtarget->is64Bit()">;
|
|---|
| 372 | def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
|
|---|
| 373 | def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
|
|---|
| 374 | def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
|
|---|
| 375 | def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
|
|---|
| 376 | def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
|
|---|
| 377 | "TM.getCodeModel() != CodeModel::Kernel">;
|
|---|
| 378 | def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
|
|---|
| 379 | "TM.getCodeModel() == CodeModel::Kernel">;
|
|---|
| 380 | def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
|
|---|
| 381 | def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
|
|---|
| 382 | def OptForSize : Predicate<"OptForSize">;
|
|---|
| 383 | def OptForSpeed : Predicate<"!OptForSize">;
|
|---|
| 384 | def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
|
|---|
| 385 | def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
|
|---|
| 386 | def HasAES : Predicate<"Subtarget->hasAES()">;
|
|---|
| 387 |
|
|---|
| 388 | //===----------------------------------------------------------------------===//
|
|---|
| 389 | // X86 Instruction Format Definitions.
|
|---|
| 390 | //
|
|---|
| 391 |
|
|---|
| 392 | include "X86InstrFormats.td"
|
|---|
| 393 |
|
|---|
| 394 | //===----------------------------------------------------------------------===//
|
|---|
| 395 | // Pattern fragments...
|
|---|
| 396 | //
|
|---|
| 397 |
|
|---|
| 398 | // X86 specific condition code. These correspond to CondCode in
|
|---|
| 399 | // X86InstrInfo.h. They must be kept in synch.
|
|---|
| 400 | def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
|
|---|
| 401 | def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
|
|---|
| 402 | def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
|
|---|
| 403 | def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
|
|---|
| 404 | def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
|
|---|
| 405 | def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
|
|---|
| 406 | def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
|
|---|
| 407 | def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
|
|---|
| 408 | def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
|
|---|
| 409 | def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
|
|---|
| 410 | def X86_COND_NO : PatLeaf<(i8 10)>;
|
|---|
| 411 | def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
|
|---|
| 412 | def X86_COND_NS : PatLeaf<(i8 12)>;
|
|---|
| 413 | def X86_COND_O : PatLeaf<(i8 13)>;
|
|---|
| 414 | def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
|
|---|
| 415 | def X86_COND_S : PatLeaf<(i8 15)>;
|
|---|
| 416 |
|
|---|
| 417 | def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
|
|---|
| 418 |
|
|---|
| 419 | def i16immSExt8 : PatLeaf<(i16 immSext8)>;
|
|---|
| 420 | def i32immSExt8 : PatLeaf<(i32 immSext8)>;
|
|---|
| 421 |
|
|---|
| 422 | /// Load patterns: these constraint the match to the right address space.
|
|---|
| 423 | def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
|---|
| 424 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
|
|---|
| 425 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
|
|---|
| 426 | if (PT->getAddressSpace() > 255)
|
|---|
| 427 | return false;
|
|---|
| 428 | return true;
|
|---|
| 429 | }]>;
|
|---|
| 430 |
|
|---|
| 431 | def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
|---|
| 432 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
|
|---|
| 433 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
|
|---|
| 434 | return PT->getAddressSpace() == 256;
|
|---|
| 435 | return false;
|
|---|
| 436 | }]>;
|
|---|
| 437 |
|
|---|
| 438 | def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|
|---|
| 439 | if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
|
|---|
| 440 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
|
|---|
| 441 | return PT->getAddressSpace() == 257;
|
|---|
| 442 | return false;
|
|---|
| 443 | }]>;
|
|---|
| 444 |
|
|---|
| 445 |
|
|---|
| 446 | // Helper fragments for loads.
|
|---|
| 447 | // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
|
|---|
| 448 | // known to be 32-bit aligned or better. Ditto for i8 to i16.
|
|---|
| 449 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
|
|---|
| 450 | LoadSDNode *LD = cast<LoadSDNode>(N);
|
|---|
| 451 | if (const Value *Src = LD->getSrcValue())
|
|---|
| 452 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
|
|---|
| 453 | if (PT->getAddressSpace() > 255)
|
|---|
| 454 | return false;
|
|---|
| 455 | ISD::LoadExtType ExtType = LD->getExtensionType();
|
|---|
| 456 | if (ExtType == ISD::NON_EXTLOAD)
|
|---|
| 457 | return true;
|
|---|
| 458 | if (ExtType == ISD::EXTLOAD)
|
|---|
| 459 | return LD->getAlignment() >= 2 && !LD->isVolatile();
|
|---|
| 460 | return false;
|
|---|
| 461 | }]>;
|
|---|
| 462 |
|
|---|
| 463 | def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
|
|---|
| 464 | LoadSDNode *LD = cast<LoadSDNode>(N);
|
|---|
| 465 | if (const Value *Src = LD->getSrcValue())
|
|---|
| 466 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
|
|---|
| 467 | if (PT->getAddressSpace() > 255)
|
|---|
| 468 | return false;
|
|---|
| 469 | ISD::LoadExtType ExtType = LD->getExtensionType();
|
|---|
| 470 | if (ExtType == ISD::EXTLOAD)
|
|---|
| 471 | return LD->getAlignment() >= 2 && !LD->isVolatile();
|
|---|
| 472 | return false;
|
|---|
| 473 | }]>;
|
|---|
| 474 |
|
|---|
| 475 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
|
|---|
| 476 | LoadSDNode *LD = cast<LoadSDNode>(N);
|
|---|
| 477 | if (const Value *Src = LD->getSrcValue())
|
|---|
| 478 | if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
|
|---|
| 479 | if (PT->getAddressSpace() > 255)
|
|---|
| 480 | return false;
|
|---|
| 481 | ISD::LoadExtType ExtType = LD->getExtensionType();
|
|---|
| 482 | if (ExtType == ISD::NON_EXTLOAD)
|
|---|
| 483 | return true;
|
|---|
| 484 | if (ExtType == ISD::EXTLOAD)
|
|---|
| 485 | return LD->getAlignment() >= 4 && !LD->isVolatile();
|
|---|
| 486 | return false;
|
|---|
| 487 | }]>;
|
|---|
| 488 |
|
|---|
| 489 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
|
|---|
| 490 | def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
|
|---|
| 491 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
|
|---|
| 492 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
|
|---|
| 493 | def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
|
|---|
| 494 |
|
|---|
| 495 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
|
|---|
| 496 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
|
|---|
| 497 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
|
|---|
| 498 |
|
|---|
| 499 | def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
|
|---|
| 500 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
|
|---|
| 501 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
|
|---|
| 502 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
|
|---|
| 503 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
|
|---|
| 504 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
|
|---|
| 505 |
|
|---|
| 506 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
|
|---|
| 507 | def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
|
|---|
| 508 | def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
|
|---|
| 509 | def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
|
|---|
| 510 | def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
|
|---|
| 511 | def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
|
|---|
| 512 |
|
|---|
| 513 |
|
|---|
| 514 | // An 'and' node with a single use.
|
|---|
| 515 | def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
|
|---|
| 516 | return N->hasOneUse();
|
|---|
| 517 | }]>;
|
|---|
| 518 | // An 'srl' node with a single use.
|
|---|
| 519 | def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
|
|---|
| 520 | return N->hasOneUse();
|
|---|
| 521 | }]>;
|
|---|
| 522 | // An 'trunc' node with a single use.
|
|---|
| 523 | def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
|
|---|
| 524 | return N->hasOneUse();
|
|---|
| 525 | }]>;
|
|---|
| 526 |
|
|---|
| 527 | // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
|
|---|
| 528 | def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
|
|---|
| 529 | if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
|
|---|
| 530 | return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
|
|---|
| 531 |
|
|---|
| 532 | unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
|
|---|
| 533 | APInt Mask = APInt::getAllOnesValue(BitWidth);
|
|---|
| 534 | APInt KnownZero0, KnownOne0;
|
|---|
| 535 | CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
|
|---|
| 536 | APInt KnownZero1, KnownOne1;
|
|---|
| 537 | CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
|
|---|
| 538 | return (~KnownZero0 & ~KnownZero1) == 0;
|
|---|
| 539 | }]>;
|
|---|
| 540 |
|
|---|
| 541 | //===----------------------------------------------------------------------===//
|
|---|
| 542 | // Instruction list...
|
|---|
| 543 | //
|
|---|
| 544 |
|
|---|
| 545 | // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
|
|---|
| 546 | // a stack adjustment and the codegen must know that they may modify the stack
|
|---|
| 547 | // pointer before prolog-epilog rewriting occurs.
|
|---|
| 548 | // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
|
|---|
| 549 | // sub / add which can clobber EFLAGS.
|
|---|
| 550 | let Defs = [ESP, EFLAGS], Uses = [ESP] in {
|
|---|
| 551 | def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
|
|---|
| 552 | "#ADJCALLSTACKDOWN",
|
|---|
| 553 | [(X86callseq_start timm:$amt)]>,
|
|---|
| 554 | Requires<[In32BitMode]>;
|
|---|
| 555 | def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
|---|
| 556 | "#ADJCALLSTACKUP",
|
|---|
| 557 | [(X86callseq_end timm:$amt1, timm:$amt2)]>,
|
|---|
| 558 | Requires<[In32BitMode]>;
|
|---|
| 559 | }
|
|---|
| 560 |
|
|---|
| 561 | // x86-64 va_start lowering magic.
|
|---|
| 562 | let usesCustomInserter = 1 in {
|
|---|
| 563 | def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
|
|---|
| 564 | (outs),
|
|---|
| 565 | (ins GR8:$al,
|
|---|
| 566 | i64imm:$regsavefi, i64imm:$offset,
|
|---|
| 567 | variable_ops),
|
|---|
| 568 | "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
|
|---|
| 569 | [(X86vastart_save_xmm_regs GR8:$al,
|
|---|
| 570 | imm:$regsavefi,
|
|---|
| 571 | imm:$offset)]>;
|
|---|
| 572 |
|
|---|
| 573 | // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
|
|---|
| 574 | // to _alloca is needed to probe the stack when allocating more than 4k bytes in
|
|---|
| 575 | // one go. Touching the stack at 4K increments is necessary to ensure that the
|
|---|
| 576 | // guard pages used by the OS virtual memory manager are allocated in correct
|
|---|
| 577 | // sequence.
|
|---|
| 578 | // The main point of having separate instruction are extra unmodelled effects
|
|---|
| 579 | // (compared to ordinary calls) like stack pointer change.
|
|---|
| 580 |
|
|---|
| 581 | let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
|
|---|
| 582 | def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
|
|---|
| 583 | "# dynamic stack allocation",
|
|---|
| 584 | [(X86MingwAlloca)]>;
|
|---|
| 585 | }
|
|---|
| 586 |
|
|---|
| 587 | // Nop
|
|---|
| 588 | let neverHasSideEffects = 1 in {
|
|---|
| 589 | def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
|
|---|
| 590 | def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
|
|---|
| 591 | "nop{w}\t$zero", []>, TB, OpSize;
|
|---|
| 592 | def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
|
|---|
| 593 | "nop{l}\t$zero", []>, TB;
|
|---|
| 594 | }
|
|---|
| 595 |
|
|---|
| 596 | // Trap
|
|---|
| 597 | let Uses = [EFLAGS] in {
|
|---|
| 598 | def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
|
|---|
| 599 | }
|
|---|
| 600 | def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
|
|---|
| 601 | [(int_x86_int (i8 3))]>;
|
|---|
| 602 | // FIXME: need to make sure that "int $3" matches int3
|
|---|
| 603 | def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
|
|---|
| 604 | [(int_x86_int imm:$trap)]>;
|
|---|
| 605 | def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
|
|---|
| 606 | def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
|
|---|
| 607 |
|
|---|
| 608 | // PIC base construction. This expands to code that looks like this:
|
|---|
| 609 | // call $next_inst
|
|---|
| 610 | // popl %destreg"
|
|---|
| 611 | let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
|
|---|
| 612 | def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
|
|---|
| 613 | "", []>;
|
|---|
| 614 |
|
|---|
| 615 | //===----------------------------------------------------------------------===//
|
|---|
| 616 | // Control Flow Instructions.
|
|---|
| 617 | //
|
|---|
| 618 |
|
|---|
| 619 | // Return instructions.
|
|---|
| 620 | let isTerminator = 1, isReturn = 1, isBarrier = 1,
|
|---|
| 621 | hasCtrlDep = 1, FPForm = SpecialFP in {
|
|---|
| 622 | def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
|
|---|
| 623 | "ret",
|
|---|
| 624 | [(X86retflag 0)]>;
|
|---|
| 625 | def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
|
|---|
| 626 | "ret\t$amt",
|
|---|
| 627 | [(X86retflag timm:$amt)]>;
|
|---|
| 628 | def LRET : I <0xCB, RawFrm, (outs), (ins),
|
|---|
| 629 | "lret", []>;
|
|---|
| 630 | def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
|
|---|
| 631 | "lret\t$amt", []>;
|
|---|
| 632 | }
|
|---|
| 633 |
|
|---|
| 634 | // Unconditional branches.
|
|---|
| 635 | let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
|
|---|
| 636 | def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
|
|---|
| 637 | "jmp\t$dst", [(br bb:$dst)]>;
|
|---|
| 638 | def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
|
|---|
| 639 | "jmp\t$dst", []>;
|
|---|
| 640 | }
|
|---|
| 641 |
|
|---|
| 642 | // Conditional Branches.
|
|---|
| 643 | let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
|
|---|
| 644 | multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
|
|---|
| 645 | def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
|
|---|
| 646 | def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
|
|---|
| 647 | [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
|
|---|
| 648 | }
|
|---|
| 649 | }
|
|---|
| 650 |
|
|---|
| 651 | defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
|
|---|
| 652 | defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
|
|---|
| 653 | defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
|
|---|
| 654 | defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
|
|---|
| 655 | defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
|
|---|
| 656 | defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
|
|---|
| 657 | defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
|
|---|
| 658 | defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
|
|---|
| 659 | defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
|
|---|
| 660 | defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
|
|---|
| 661 | defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
|
|---|
| 662 | defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
|
|---|
| 663 | defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
|
|---|
| 664 | defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
|
|---|
| 665 | defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
|
|---|
| 666 | defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
|
|---|
| 667 |
|
|---|
| 668 | // FIXME: What about the CX/RCX versions of this instruction?
|
|---|
| 669 | let Uses = [ECX], isBranch = 1, isTerminator = 1 in
|
|---|
| 670 | def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
|
|---|
| 671 | "jcxz\t$dst", []>;
|
|---|
| 672 |
|
|---|
| 673 |
|
|---|
| 674 | // Indirect branches
|
|---|
| 675 | let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
|
|---|
| 676 | def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
|
|---|
| 677 | [(brind GR32:$dst)]>, Requires<[In32BitMode]>;
|
|---|
| 678 | def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
|
|---|
| 679 | [(brind (loadi32 addr:$dst))]>, Requires<[In32BitMode]>;
|
|---|
| 680 |
|
|---|
| 681 | def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
|
|---|
| 682 | (ins i16imm:$off, i16imm:$seg),
|
|---|
| 683 | "ljmp{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
|
|---|
| 684 | def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
|
|---|
| 685 | (ins i32imm:$off, i16imm:$seg),
|
|---|
| 686 | "ljmp{l}\t{$seg, $off|$off, $seg}", []>;
|
|---|
| 687 |
|
|---|
| 688 | def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
|
|---|
| 689 | "ljmp{w}\t{*}$dst", []>, OpSize;
|
|---|
| 690 | def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
|
|---|
| 691 | "ljmp{l}\t{*}$dst", []>;
|
|---|
| 692 | }
|
|---|
| 693 |
|
|---|
| 694 |
|
|---|
| 695 | // Loop instructions
|
|---|
| 696 |
|
|---|
| 697 | def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
|
|---|
| 698 | def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
|
|---|
| 699 | def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
|
|---|
| 700 |
|
|---|
| 701 | //===----------------------------------------------------------------------===//
|
|---|
| 702 | // Call Instructions...
|
|---|
| 703 | //
|
|---|
| 704 | let isCall = 1 in
|
|---|
| 705 | // All calls clobber the non-callee saved registers. ESP is marked as
|
|---|
| 706 | // a use to prevent stack-pointer assignments that appear immediately
|
|---|
| 707 | // before calls from potentially appearing dead. Uses for argument
|
|---|
| 708 | // registers are added manually.
|
|---|
| 709 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
|
|---|
| 710 | MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
|---|
| 711 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|---|
| 712 | XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
|
|---|
| 713 | Uses = [ESP] in {
|
|---|
| 714 | def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
|
|---|
| 715 | (outs), (ins i32imm_pcrel:$dst,variable_ops),
|
|---|
| 716 | "call\t$dst", []>;
|
|---|
| 717 | def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
|
|---|
| 718 | "call\t{*}$dst", [(X86call GR32:$dst)]>;
|
|---|
| 719 | def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
|
|---|
| 720 | "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
|
|---|
| 721 |
|
|---|
| 722 | def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
|
|---|
| 723 | (ins i16imm:$off, i16imm:$seg),
|
|---|
| 724 | "lcall{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
|
|---|
| 725 | def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
|
|---|
| 726 | (ins i32imm:$off, i16imm:$seg),
|
|---|
| 727 | "lcall{l}\t{$seg, $off|$off, $seg}", []>;
|
|---|
| 728 |
|
|---|
| 729 | def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
|
|---|
| 730 | "lcall{w}\t{*}$dst", []>, OpSize;
|
|---|
| 731 | def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
|
|---|
| 732 | "lcall{l}\t{*}$dst", []>;
|
|---|
| 733 |
|
|---|
| 734 | // callw for 16 bit code for the assembler.
|
|---|
| 735 | let isAsmParserOnly = 1 in
|
|---|
| 736 | def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
|
|---|
| 737 | (outs), (ins i16imm_pcrel:$dst, variable_ops),
|
|---|
| 738 | "callw\t$dst", []>, OpSize;
|
|---|
| 739 | }
|
|---|
| 740 |
|
|---|
| 741 | // Constructing a stack frame.
|
|---|
| 742 |
|
|---|
| 743 | def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
|
|---|
| 744 | "enter\t$len, $lvl", []>;
|
|---|
| 745 |
|
|---|
| 746 | // Tail call stuff.
|
|---|
| 747 |
|
|---|
| 748 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
|
|---|
| 749 | isCodeGenOnly = 1 in
|
|---|
| 750 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
|
|---|
| 751 | MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
|---|
| 752 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|---|
| 753 | XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
|
|---|
| 754 | Uses = [ESP] in {
|
|---|
| 755 | def TCRETURNdi : I<0, Pseudo, (outs),
|
|---|
| 756 | (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
|
|---|
| 757 | "#TC_RETURN $dst $offset", []>;
|
|---|
| 758 | def TCRETURNri : I<0, Pseudo, (outs),
|
|---|
| 759 | (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
|
|---|
| 760 | "#TC_RETURN $dst $offset", []>;
|
|---|
| 761 | let mayLoad = 1 in
|
|---|
| 762 | def TCRETURNmi : I<0, Pseudo, (outs),
|
|---|
| 763 | (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
|
|---|
| 764 | "#TC_RETURN $dst $offset", []>;
|
|---|
| 765 |
|
|---|
| 766 | // FIXME: The should be pseudo instructions that are lowered when going to
|
|---|
| 767 | // mcinst.
|
|---|
| 768 | def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
|
|---|
| 769 | (ins i32imm_pcrel:$dst, variable_ops),
|
|---|
| 770 | "jmp\t$dst # TAILCALL",
|
|---|
| 771 | []>;
|
|---|
| 772 | def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
|
|---|
| 773 | "", []>; // FIXME: Remove encoding when JIT is dead.
|
|---|
| 774 | let mayLoad = 1 in
|
|---|
| 775 | def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
|
|---|
| 776 | "jmp{l}\t{*}$dst # TAILCALL", []>;
|
|---|
| 777 | }
|
|---|
| 778 |
|
|---|
| 779 | //===----------------------------------------------------------------------===//
|
|---|
| 780 | // Miscellaneous Instructions...
|
|---|
| 781 | //
|
|---|
| 782 | let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
|
|---|
| 783 | def LEAVE : I<0xC9, RawFrm,
|
|---|
| 784 | (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
|
|---|
| 785 |
|
|---|
| 786 | def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
|---|
| 787 | "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
|
|---|
| 788 | let mayLoad = 1 in
|
|---|
| 789 | def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
|---|
| 790 | "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
|
|---|
| 791 | def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 792 | "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
|
|---|
| 793 | let mayLoad = 1 in
|
|---|
| 794 | def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|---|
| 795 | "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
|
|---|
| 796 |
|
|---|
| 797 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
|
|---|
| 798 | let mayLoad = 1 in {
|
|---|
| 799 | def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
|
|---|
| 800 | OpSize;
|
|---|
| 801 | def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
|
|---|
| 802 | def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
|
|---|
| 803 | OpSize;
|
|---|
| 804 | def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
|
|---|
| 805 | OpSize;
|
|---|
| 806 | def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
|
|---|
| 807 | def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
|
|---|
| 808 | }
|
|---|
| 809 |
|
|---|
| 810 | let mayStore = 1 in {
|
|---|
| 811 | def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
|
|---|
| 812 | OpSize;
|
|---|
| 813 | def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
|
|---|
| 814 | def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
|
|---|
| 815 | OpSize;
|
|---|
| 816 | def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
|
|---|
| 817 | OpSize;
|
|---|
| 818 | def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
|
|---|
| 819 | def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
|
|---|
| 820 | }
|
|---|
| 821 | }
|
|---|
| 822 |
|
|---|
| 823 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
|
|---|
| 824 | def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
|
|---|
| 825 | "push{l}\t$imm", []>;
|
|---|
| 826 | def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
|
|---|
| 827 | "push{w}\t$imm", []>, OpSize;
|
|---|
| 828 | def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
|
|---|
| 829 | "push{l}\t$imm", []>;
|
|---|
| 830 | }
|
|---|
| 831 |
|
|---|
| 832 | let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
|
|---|
| 833 | def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
|
|---|
| 834 | def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
|
|---|
| 835 | Requires<[In32BitMode]>;
|
|---|
| 836 | }
|
|---|
| 837 | let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
|
|---|
| 838 | def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
|
|---|
| 839 | def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
|
|---|
| 840 | Requires<[In32BitMode]>;
|
|---|
| 841 | }
|
|---|
| 842 |
|
|---|
| 843 | let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
|
|---|
| 844 | mayLoad=1, neverHasSideEffects=1 in {
|
|---|
| 845 | def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
|
|---|
| 846 | Requires<[In32BitMode]>;
|
|---|
| 847 | }
|
|---|
| 848 | let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
|
|---|
| 849 | mayStore=1, neverHasSideEffects=1 in {
|
|---|
| 850 | def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
|
|---|
| 851 | Requires<[In32BitMode]>;
|
|---|
| 852 | }
|
|---|
| 853 |
|
|---|
| 854 | let Uses = [EFLAGS], Constraints = "$src = $dst" in // GR32 = bswap GR32
|
|---|
| 855 | def BSWAP32r : I<0xC8, AddRegFrm,
|
|---|
| 856 | (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 857 | "bswap{l}\t$dst",
|
|---|
| 858 | [(set GR32:$dst, (bswap GR32:$src))]>, TB;
|
|---|
| 859 |
|
|---|
| 860 |
|
|---|
| 861 | // Bit scan instructions.
|
|---|
| 862 | let Defs = [EFLAGS] in {
|
|---|
| 863 | def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
|---|
| 864 | "bsf{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 865 | [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
|
|---|
| 866 | def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
|---|
| 867 | "bsf{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 868 | [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
|
|---|
| 869 | OpSize;
|
|---|
| 870 | def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 871 | "bsf{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 872 | [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
|
|---|
| 873 | def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|---|
| 874 | "bsf{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 875 | [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
|
|---|
| 876 |
|
|---|
| 877 | def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
|---|
| 878 | "bsr{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 879 | [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
|
|---|
| 880 | def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
|---|
| 881 | "bsr{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 882 | [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
|
|---|
| 883 | OpSize;
|
|---|
| 884 | def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 885 | "bsr{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 886 | [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
|
|---|
| 887 | def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|---|
| 888 | "bsr{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 889 | [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
|
|---|
| 890 | } // Defs = [EFLAGS]
|
|---|
| 891 |
|
|---|
| 892 | let neverHasSideEffects = 1 in
|
|---|
| 893 | def LEA16r : I<0x8D, MRMSrcMem,
|
|---|
| 894 | (outs GR16:$dst), (ins i32mem:$src),
|
|---|
| 895 | "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
|
|---|
| 896 | let isReMaterializable = 1 in
|
|---|
| 897 | def LEA32r : I<0x8D, MRMSrcMem,
|
|---|
| 898 | (outs GR32:$dst), (ins i32mem:$src),
|
|---|
| 899 | "lea{l}\t{$src|$dst}, {$dst|$src}",
|
|---|
| 900 | [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
|
|---|
| 901 |
|
|---|
| 902 | let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
|
|---|
| 903 | def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
|
|---|
| 904 | [(X86rep_movs i8)]>, REP;
|
|---|
| 905 | def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
|
|---|
| 906 | [(X86rep_movs i16)]>, REP, OpSize;
|
|---|
| 907 | def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
|
|---|
| 908 | [(X86rep_movs i32)]>, REP;
|
|---|
| 909 | }
|
|---|
| 910 |
|
|---|
| 911 | // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
|
|---|
| 912 | let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
|
|---|
| 913 | def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
|
|---|
| 914 | def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
|
|---|
| 915 | def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
|
|---|
| 916 | }
|
|---|
| 917 |
|
|---|
| 918 | let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
|
|---|
| 919 | def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
|
|---|
| 920 | [(X86rep_stos i8)]>, REP;
|
|---|
| 921 | let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
|
|---|
| 922 | def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
|
|---|
| 923 | [(X86rep_stos i16)]>, REP, OpSize;
|
|---|
| 924 | let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
|
|---|
| 925 | def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
|
|---|
| 926 | [(X86rep_stos i32)]>, REP;
|
|---|
| 927 |
|
|---|
| 928 | // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
|
|---|
| 929 | let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
|
|---|
| 930 | def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
|
|---|
| 931 | let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
|
|---|
| 932 | def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
|
|---|
| 933 | let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
|
|---|
| 934 | def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
|
|---|
| 935 |
|
|---|
| 936 | def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
|
|---|
| 937 | def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
|
|---|
| 938 | def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
|
|---|
| 939 |
|
|---|
| 940 | def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
|
|---|
| 941 | def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
|
|---|
| 942 | def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
|
|---|
| 943 |
|
|---|
| 944 | let Defs = [RAX, RDX] in
|
|---|
| 945 | def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
|
|---|
| 946 | TB;
|
|---|
| 947 |
|
|---|
| 948 | let Defs = [RAX, RCX, RDX] in
|
|---|
| 949 | def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
|
|---|
| 950 |
|
|---|
| 951 | let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
|
|---|
| 952 | def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
|
|---|
| 953 | }
|
|---|
| 954 |
|
|---|
| 955 | def SYSCALL : I<0x05, RawFrm,
|
|---|
| 956 | (outs), (ins), "syscall", []>, TB;
|
|---|
| 957 | def SYSRET : I<0x07, RawFrm,
|
|---|
| 958 | (outs), (ins), "sysret", []>, TB;
|
|---|
| 959 | def SYSENTER : I<0x34, RawFrm,
|
|---|
| 960 | (outs), (ins), "sysenter", []>, TB;
|
|---|
| 961 | def SYSEXIT : I<0x35, RawFrm,
|
|---|
| 962 | (outs), (ins), "sysexit", []>, TB, Requires<[In32BitMode]>;
|
|---|
| 963 |
|
|---|
| 964 | def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
|
|---|
| 965 |
|
|---|
| 966 |
|
|---|
| 967 | //===----------------------------------------------------------------------===//
|
|---|
| 968 | // Input/Output Instructions...
|
|---|
| 969 | //
|
|---|
| 970 | let Defs = [AL], Uses = [DX] in
|
|---|
| 971 | def IN8rr : I<0xEC, RawFrm, (outs), (ins),
|
|---|
| 972 | "in{b}\t{%dx, %al|%AL, %DX}", []>;
|
|---|
| 973 | let Defs = [AX], Uses = [DX] in
|
|---|
| 974 | def IN16rr : I<0xED, RawFrm, (outs), (ins),
|
|---|
| 975 | "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
|
|---|
| 976 | let Defs = [EAX], Uses = [DX] in
|
|---|
| 977 | def IN32rr : I<0xED, RawFrm, (outs), (ins),
|
|---|
| 978 | "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
|
|---|
| 979 |
|
|---|
| 980 | let Defs = [AL] in
|
|---|
| 981 | def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
|
|---|
| 982 | "in{b}\t{$port, %al|%AL, $port}", []>;
|
|---|
| 983 | let Defs = [AX] in
|
|---|
| 984 | def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
|
|---|
| 985 | "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
|
|---|
| 986 | let Defs = [EAX] in
|
|---|
| 987 | def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
|
|---|
| 988 | "in{l}\t{$port, %eax|%EAX, $port}", []>;
|
|---|
| 989 |
|
|---|
| 990 | let Uses = [DX, AL] in
|
|---|
| 991 | def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
|
|---|
| 992 | "out{b}\t{%al, %dx|%DX, %AL}", []>;
|
|---|
| 993 | let Uses = [DX, AX] in
|
|---|
| 994 | def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
|
|---|
| 995 | "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
|
|---|
| 996 | let Uses = [DX, EAX] in
|
|---|
| 997 | def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
|
|---|
| 998 | "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
|
|---|
| 999 |
|
|---|
| 1000 | let Uses = [AL] in
|
|---|
| 1001 | def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
|
|---|
| 1002 | "out{b}\t{%al, $port|$port, %AL}", []>;
|
|---|
| 1003 | let Uses = [AX] in
|
|---|
| 1004 | def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
|
|---|
| 1005 | "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
|
|---|
| 1006 | let Uses = [EAX] in
|
|---|
| 1007 | def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
|
|---|
| 1008 | "out{l}\t{%eax, $port|$port, %EAX}", []>;
|
|---|
| 1009 |
|
|---|
| 1010 | def IN8 : I<0x6C, RawFrm, (outs), (ins),
|
|---|
| 1011 | "ins{b}", []>;
|
|---|
| 1012 | def IN16 : I<0x6D, RawFrm, (outs), (ins),
|
|---|
| 1013 | "ins{w}", []>, OpSize;
|
|---|
| 1014 | def IN32 : I<0x6D, RawFrm, (outs), (ins),
|
|---|
| 1015 | "ins{l}", []>;
|
|---|
| 1016 |
|
|---|
| 1017 | //===----------------------------------------------------------------------===//
|
|---|
| 1018 | // Move Instructions...
|
|---|
| 1019 | //
|
|---|
| 1020 | let neverHasSideEffects = 1 in {
|
|---|
| 1021 | def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
|
|---|
| 1022 | "mov{b}\t{$src, $dst|$dst, $src}", []>;
|
|---|
| 1023 | def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
|
|---|
| 1024 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
|---|
| 1025 | def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 1026 | "mov{l}\t{$src, $dst|$dst, $src}", []>;
|
|---|
| 1027 | }
|
|---|
| 1028 | let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
|
|---|
| 1029 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
|
|---|
| 1030 | "mov{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 1031 | [(set GR8:$dst, imm:$src)]>;
|
|---|
| 1032 | def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
|
|---|
| 1033 | "mov{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 1034 | [(set GR16:$dst, imm:$src)]>, OpSize;
|
|---|
| 1035 | def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
|
|---|
| 1036 | "mov{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 1037 | [(set GR32:$dst, imm:$src)]>;
|
|---|
| 1038 | }
|
|---|
| 1039 |
|
|---|
| 1040 | def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
|
|---|
| 1041 | "mov{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 1042 | [(store (i8 imm:$src), addr:$dst)]>;
|
|---|
| 1043 | def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
|
|---|
| 1044 | "mov{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 1045 | [(store (i16 imm:$src), addr:$dst)]>, OpSize;
|
|---|
| 1046 | def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
|
|---|
| 1047 | "mov{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 1048 | [(store (i32 imm:$src), addr:$dst)]>;
|
|---|
| 1049 |
|
|---|
| 1050 | /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
|
|---|
| 1051 | /// 32-bit offset from the PC. These are only valid in x86-32 mode.
|
|---|
| 1052 | def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
|
|---|
| 1053 | "mov{b}\t{$src, %al|%al, $src}", []>,
|
|---|
| 1054 | Requires<[In32BitMode]>;
|
|---|
| 1055 | def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
|
|---|
| 1056 | "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
|
|---|
| 1057 | Requires<[In32BitMode]>;
|
|---|
| 1058 | def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
|
|---|
| 1059 | "mov{l}\t{$src, %eax|%eax, $src}", []>,
|
|---|
| 1060 | Requires<[In32BitMode]>;
|
|---|
| 1061 | def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
|
|---|
| 1062 | "mov{b}\t{%al, $dst|$dst, %al}", []>,
|
|---|
| 1063 | Requires<[In32BitMode]>;
|
|---|
| 1064 | def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
|
|---|
| 1065 | "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
|
|---|
| 1066 | Requires<[In32BitMode]>;
|
|---|
| 1067 | def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
|
|---|
| 1068 | "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
|
|---|
| 1069 | Requires<[In32BitMode]>;
|
|---|
| 1070 |
|
|---|
| 1071 | // Moves to and from segment registers
|
|---|
| 1072 | def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
|
|---|
| 1073 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
|---|
| 1074 | def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
|
|---|
| 1075 | "mov{l}\t{$src, $dst|$dst, $src}", []>;
|
|---|
| 1076 | def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
|
|---|
| 1077 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
|---|
| 1078 | def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
|
|---|
| 1079 | "mov{l}\t{$src, $dst|$dst, $src}", []>;
|
|---|
| 1080 | def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
|
|---|
| 1081 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
|---|
| 1082 | def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
|
|---|
| 1083 | "mov{l}\t{$src, $dst|$dst, $src}", []>;
|
|---|
| 1084 | def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
|
|---|
| 1085 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
|---|
| 1086 | def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
|
|---|
| 1087 | "mov{l}\t{$src, $dst|$dst, $src}", []>;
|
|---|
| 1088 |
|
|---|
| 1089 | let isCodeGenOnly = 1 in {
|
|---|
| 1090 | def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
|
|---|
| 1091 | "mov{b}\t{$src, $dst|$dst, $src}", []>;
|
|---|
| 1092 | def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
|---|
| 1093 | "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
|---|
| 1094 | def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 1095 | "mov{l}\t{$src, $dst|$dst, $src}", []>;
|
|---|
| 1096 | }
|
|---|
| 1097 |
|
|---|
| 1098 | let canFoldAsLoad = 1, isReMaterializable = 1 in {
|
|---|
| 1099 | def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
|
|---|
| 1100 | "mov{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 1101 | [(set GR8:$dst, (loadi8 addr:$src))]>;
|
|---|
| 1102 | def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
|---|
| 1103 | "mov{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 1104 | [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
|
|---|
| 1105 | def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|---|
| 1106 | "mov{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 1107 | [(set GR32:$dst, (loadi32 addr:$src))]>;
|
|---|
| 1108 | }
|
|---|
| 1109 |
|
|---|
| 1110 | def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
|
|---|
| 1111 | "mov{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 1112 | [(store GR8:$src, addr:$dst)]>;
|
|---|
| 1113 | def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
|---|
| 1114 | "mov{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 1115 | [(store GR16:$src, addr:$dst)]>, OpSize;
|
|---|
| 1116 | def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
|---|
| 1117 | "mov{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 1118 | [(store GR32:$src, addr:$dst)]>;
|
|---|
| 1119 |
|
|---|
| 1120 | /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
|
|---|
| 1121 | let isCodeGenOnly = 1 in {
|
|---|
| 1122 | let neverHasSideEffects = 1 in
|
|---|
| 1123 | def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
|
|---|
| 1124 | "mov{l}\t{$src, $dst|$dst, $src}", []>;
|
|---|
| 1125 |
|
|---|
| 1126 | let mayLoad = 1,
|
|---|
| 1127 | canFoldAsLoad = 1, isReMaterializable = 1 in
|
|---|
| 1128 | def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
|
|---|
| 1129 | "mov{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 1130 | []>;
|
|---|
| 1131 |
|
|---|
| 1132 | let mayStore = 1 in
|
|---|
| 1133 | def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
|
|---|
| 1134 | "mov{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 1135 | []>;
|
|---|
| 1136 | }
|
|---|
| 1137 |
|
|---|
| 1138 | // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
|
|---|
| 1139 | // that they can be used for copying and storing h registers, which can't be
|
|---|
| 1140 | // encoded when a REX prefix is present.
|
|---|
| 1141 | let isCodeGenOnly = 1 in {
|
|---|
| 1142 | let neverHasSideEffects = 1 in
|
|---|
| 1143 | def MOV8rr_NOREX : I<0x88, MRMDestReg,
|
|---|
| 1144 | (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
|
|---|
| 1145 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
|
|---|
| 1146 | let mayStore = 1 in
|
|---|
| 1147 | def MOV8mr_NOREX : I<0x88, MRMDestMem,
|
|---|
| 1148 | (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
|
|---|
| 1149 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
|
|---|
| 1150 | let mayLoad = 1,
|
|---|
| 1151 | canFoldAsLoad = 1, isReMaterializable = 1 in
|
|---|
| 1152 | def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
|
|---|
| 1153 | (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
|
|---|
| 1154 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
|
|---|
| 1155 | }
|
|---|
| 1156 |
|
|---|
| 1157 | // Moves to and from debug registers
|
|---|
| 1158 | def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
|
|---|
| 1159 | "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 1160 | def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
|
|---|
| 1161 | "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 1162 |
|
|---|
| 1163 | // Moves to and from control registers
|
|---|
| 1164 | def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
|
|---|
| 1165 | "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 1166 | def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
|
|---|
| 1167 | "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 1168 |
|
|---|
| 1169 | //===----------------------------------------------------------------------===//
|
|---|
| 1170 | // Fixed-Register Multiplication and Division Instructions...
|
|---|
| 1171 | //
|
|---|
| 1172 |
|
|---|
| 1173 | // Extra precision multiplication
|
|---|
| 1174 |
|
|---|
| 1175 | // AL is really implied by AX, but the registers in Defs must match the
|
|---|
| 1176 | // SDNode results (i8, i32).
|
|---|
| 1177 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in
|
|---|
| 1178 | def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
|
|---|
| 1179 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
|
|---|
| 1180 | // This probably ought to be moved to a def : Pat<> if the
|
|---|
| 1181 | // syntax can be accepted.
|
|---|
| 1182 | [(set AL, (mul AL, GR8:$src)),
|
|---|
| 1183 | (implicit EFLAGS)]>; // AL,AH = AL*GR8
|
|---|
| 1184 |
|
|---|
| 1185 | let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
|
|---|
| 1186 | def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
|
|---|
| 1187 | "mul{w}\t$src",
|
|---|
| 1188 | []>, OpSize; // AX,DX = AX*GR16
|
|---|
| 1189 |
|
|---|
| 1190 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
|
|---|
| 1191 | def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
|
|---|
| 1192 | "mul{l}\t$src",
|
|---|
| 1193 | []>; // EAX,EDX = EAX*GR32
|
|---|
| 1194 |
|
|---|
| 1195 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in
|
|---|
| 1196 | def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
|
|---|
| 1197 | "mul{b}\t$src",
|
|---|
| 1198 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
|
|---|
| 1199 | // This probably ought to be moved to a def : Pat<> if the
|
|---|
| 1200 | // syntax can be accepted.
|
|---|
| 1201 | [(set AL, (mul AL, (loadi8 addr:$src))),
|
|---|
| 1202 | (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
|
|---|
| 1203 |
|
|---|
| 1204 | let mayLoad = 1, neverHasSideEffects = 1 in {
|
|---|
| 1205 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in
|
|---|
| 1206 | def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
|
|---|
| 1207 | "mul{w}\t$src",
|
|---|
| 1208 | []>, OpSize; // AX,DX = AX*[mem16]
|
|---|
| 1209 |
|
|---|
| 1210 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
|
|---|
| 1211 | def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
|
|---|
| 1212 | "mul{l}\t$src",
|
|---|
| 1213 | []>; // EAX,EDX = EAX*[mem32]
|
|---|
| 1214 | }
|
|---|
| 1215 |
|
|---|
| 1216 | let neverHasSideEffects = 1 in {
|
|---|
| 1217 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in
|
|---|
| 1218 | def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
|
|---|
| 1219 | // AL,AH = AL*GR8
|
|---|
| 1220 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in
|
|---|
| 1221 | def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
|
|---|
| 1222 | OpSize; // AX,DX = AX*GR16
|
|---|
| 1223 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
|
|---|
| 1224 | def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
|
|---|
| 1225 | // EAX,EDX = EAX*GR32
|
|---|
| 1226 | let mayLoad = 1 in {
|
|---|
| 1227 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in
|
|---|
| 1228 | def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
|
|---|
| 1229 | "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
|
|---|
| 1230 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in
|
|---|
| 1231 | def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
|
|---|
| 1232 | "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
|
|---|
| 1233 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
|
|---|
| 1234 | def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
|
|---|
| 1235 | "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
|
|---|
| 1236 | }
|
|---|
| 1237 | } // neverHasSideEffects
|
|---|
| 1238 |
|
|---|
| 1239 | // unsigned division/remainder
|
|---|
| 1240 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in
|
|---|
| 1241 | def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
|
|---|
| 1242 | "div{b}\t$src", []>;
|
|---|
| 1243 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
|
|---|
| 1244 | def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
|
|---|
| 1245 | "div{w}\t$src", []>, OpSize;
|
|---|
| 1246 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
|
|---|
| 1247 | def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
|
|---|
| 1248 | "div{l}\t$src", []>;
|
|---|
| 1249 | let mayLoad = 1 in {
|
|---|
| 1250 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in
|
|---|
| 1251 | def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
|
|---|
| 1252 | "div{b}\t$src", []>;
|
|---|
| 1253 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
|
|---|
| 1254 | def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
|
|---|
| 1255 | "div{w}\t$src", []>, OpSize;
|
|---|
| 1256 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
|
|---|
| 1257 | // EDX:EAX/[mem32] = EAX,EDX
|
|---|
| 1258 | def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
|
|---|
| 1259 | "div{l}\t$src", []>;
|
|---|
| 1260 | }
|
|---|
| 1261 |
|
|---|
| 1262 | // Signed division/remainder.
|
|---|
| 1263 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in
|
|---|
| 1264 | def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
|
|---|
| 1265 | "idiv{b}\t$src", []>;
|
|---|
| 1266 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
|
|---|
| 1267 | def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
|
|---|
| 1268 | "idiv{w}\t$src", []>, OpSize;
|
|---|
| 1269 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
|
|---|
| 1270 | def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
|
|---|
| 1271 | "idiv{l}\t$src", []>;
|
|---|
| 1272 | let mayLoad = 1, mayLoad = 1 in {
|
|---|
| 1273 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in
|
|---|
| 1274 | def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
|
|---|
| 1275 | "idiv{b}\t$src", []>;
|
|---|
| 1276 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
|
|---|
| 1277 | def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
|
|---|
| 1278 | "idiv{w}\t$src", []>, OpSize;
|
|---|
| 1279 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
|
|---|
| 1280 | def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
|
|---|
| 1281 | // EDX:EAX/[mem32] = EAX,EDX
|
|---|
| 1282 | "idiv{l}\t$src", []>;
|
|---|
| 1283 | }
|
|---|
| 1284 |
|
|---|
| 1285 | //===----------------------------------------------------------------------===//
|
|---|
| 1286 | // Two address Instructions.
|
|---|
| 1287 | //
|
|---|
| 1288 | let Constraints = "$src1 = $dst" in {
|
|---|
| 1289 |
|
|---|
| 1290 | // Conditional moves
|
|---|
| 1291 | let Uses = [EFLAGS] in {
|
|---|
| 1292 |
|
|---|
| 1293 | let Predicates = [HasCMov] in {
|
|---|
| 1294 | let isCommutable = 1 in {
|
|---|
| 1295 | def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
|
|---|
| 1296 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1297 | "cmovb{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1298 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1299 | X86_COND_B, EFLAGS))]>,
|
|---|
| 1300 | TB, OpSize;
|
|---|
| 1301 | def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
|
|---|
| 1302 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1303 | "cmovb{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1304 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1305 | X86_COND_B, EFLAGS))]>,
|
|---|
| 1306 | TB;
|
|---|
| 1307 | def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
|
|---|
| 1308 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1309 | "cmovae{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1310 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1311 | X86_COND_AE, EFLAGS))]>,
|
|---|
| 1312 | TB, OpSize;
|
|---|
| 1313 | def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
|
|---|
| 1314 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1315 | "cmovae{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1316 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1317 | X86_COND_AE, EFLAGS))]>,
|
|---|
| 1318 | TB;
|
|---|
| 1319 | def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
|
|---|
| 1320 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1321 | "cmove{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1322 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1323 | X86_COND_E, EFLAGS))]>,
|
|---|
| 1324 | TB, OpSize;
|
|---|
| 1325 | def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
|
|---|
| 1326 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1327 | "cmove{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1328 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1329 | X86_COND_E, EFLAGS))]>,
|
|---|
| 1330 | TB;
|
|---|
| 1331 | def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
|
|---|
| 1332 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1333 | "cmovne{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1334 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1335 | X86_COND_NE, EFLAGS))]>,
|
|---|
| 1336 | TB, OpSize;
|
|---|
| 1337 | def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
|
|---|
| 1338 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1339 | "cmovne{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1340 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1341 | X86_COND_NE, EFLAGS))]>,
|
|---|
| 1342 | TB;
|
|---|
| 1343 | def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
|
|---|
| 1344 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1345 | "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1346 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1347 | X86_COND_BE, EFLAGS))]>,
|
|---|
| 1348 | TB, OpSize;
|
|---|
| 1349 | def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
|
|---|
| 1350 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1351 | "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1352 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1353 | X86_COND_BE, EFLAGS))]>,
|
|---|
| 1354 | TB;
|
|---|
| 1355 | def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
|
|---|
| 1356 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1357 | "cmova{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1358 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1359 | X86_COND_A, EFLAGS))]>,
|
|---|
| 1360 | TB, OpSize;
|
|---|
| 1361 | def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
|
|---|
| 1362 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1363 | "cmova{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1364 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1365 | X86_COND_A, EFLAGS))]>,
|
|---|
| 1366 | TB;
|
|---|
| 1367 | def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
|
|---|
| 1368 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1369 | "cmovl{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1370 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1371 | X86_COND_L, EFLAGS))]>,
|
|---|
| 1372 | TB, OpSize;
|
|---|
| 1373 | def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
|
|---|
| 1374 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1375 | "cmovl{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1376 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1377 | X86_COND_L, EFLAGS))]>,
|
|---|
| 1378 | TB;
|
|---|
| 1379 | def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
|
|---|
| 1380 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1381 | "cmovge{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1382 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1383 | X86_COND_GE, EFLAGS))]>,
|
|---|
| 1384 | TB, OpSize;
|
|---|
| 1385 | def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
|
|---|
| 1386 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1387 | "cmovge{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1388 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1389 | X86_COND_GE, EFLAGS))]>,
|
|---|
| 1390 | TB;
|
|---|
| 1391 | def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
|
|---|
| 1392 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1393 | "cmovle{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1394 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1395 | X86_COND_LE, EFLAGS))]>,
|
|---|
| 1396 | TB, OpSize;
|
|---|
| 1397 | def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
|
|---|
| 1398 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1399 | "cmovle{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1400 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1401 | X86_COND_LE, EFLAGS))]>,
|
|---|
| 1402 | TB;
|
|---|
| 1403 | def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
|
|---|
| 1404 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1405 | "cmovg{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1406 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1407 | X86_COND_G, EFLAGS))]>,
|
|---|
| 1408 | TB, OpSize;
|
|---|
| 1409 | def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
|
|---|
| 1410 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1411 | "cmovg{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1412 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1413 | X86_COND_G, EFLAGS))]>,
|
|---|
| 1414 | TB;
|
|---|
| 1415 | def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
|
|---|
| 1416 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1417 | "cmovs{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1418 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1419 | X86_COND_S, EFLAGS))]>,
|
|---|
| 1420 | TB, OpSize;
|
|---|
| 1421 | def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
|
|---|
| 1422 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1423 | "cmovs{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1424 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1425 | X86_COND_S, EFLAGS))]>,
|
|---|
| 1426 | TB;
|
|---|
| 1427 | def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
|
|---|
| 1428 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1429 | "cmovns{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1430 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1431 | X86_COND_NS, EFLAGS))]>,
|
|---|
| 1432 | TB, OpSize;
|
|---|
| 1433 | def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
|
|---|
| 1434 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1435 | "cmovns{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1436 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1437 | X86_COND_NS, EFLAGS))]>,
|
|---|
| 1438 | TB;
|
|---|
| 1439 | def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
|
|---|
| 1440 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1441 | "cmovp{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1442 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1443 | X86_COND_P, EFLAGS))]>,
|
|---|
| 1444 | TB, OpSize;
|
|---|
| 1445 | def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
|
|---|
| 1446 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1447 | "cmovp{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1448 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1449 | X86_COND_P, EFLAGS))]>,
|
|---|
| 1450 | TB;
|
|---|
| 1451 | def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
|
|---|
| 1452 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1453 | "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1454 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1455 | X86_COND_NP, EFLAGS))]>,
|
|---|
| 1456 | TB, OpSize;
|
|---|
| 1457 | def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
|
|---|
| 1458 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1459 | "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1460 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1461 | X86_COND_NP, EFLAGS))]>,
|
|---|
| 1462 | TB;
|
|---|
| 1463 | def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
|
|---|
| 1464 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1465 | "cmovo{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1466 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1467 | X86_COND_O, EFLAGS))]>,
|
|---|
| 1468 | TB, OpSize;
|
|---|
| 1469 | def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
|
|---|
| 1470 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1471 | "cmovo{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1472 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1473 | X86_COND_O, EFLAGS))]>,
|
|---|
| 1474 | TB;
|
|---|
| 1475 | def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
|
|---|
| 1476 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1477 | "cmovno{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1478 | [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
|
|---|
| 1479 | X86_COND_NO, EFLAGS))]>,
|
|---|
| 1480 | TB, OpSize;
|
|---|
| 1481 | def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
|
|---|
| 1482 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1483 | "cmovno{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1484 | [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
|
|---|
| 1485 | X86_COND_NO, EFLAGS))]>,
|
|---|
| 1486 | TB;
|
|---|
| 1487 | } // isCommutable = 1
|
|---|
| 1488 |
|
|---|
| 1489 | def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
|
|---|
| 1490 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1491 | "cmovb{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1492 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1493 | X86_COND_B, EFLAGS))]>,
|
|---|
| 1494 | TB, OpSize;
|
|---|
| 1495 | def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
|
|---|
| 1496 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1497 | "cmovb{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1498 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1499 | X86_COND_B, EFLAGS))]>,
|
|---|
| 1500 | TB;
|
|---|
| 1501 | def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
|
|---|
| 1502 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1503 | "cmovae{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1504 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1505 | X86_COND_AE, EFLAGS))]>,
|
|---|
| 1506 | TB, OpSize;
|
|---|
| 1507 | def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
|
|---|
| 1508 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1509 | "cmovae{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1510 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1511 | X86_COND_AE, EFLAGS))]>,
|
|---|
| 1512 | TB;
|
|---|
| 1513 | def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
|
|---|
| 1514 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1515 | "cmove{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1516 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1517 | X86_COND_E, EFLAGS))]>,
|
|---|
| 1518 | TB, OpSize;
|
|---|
| 1519 | def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
|
|---|
| 1520 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1521 | "cmove{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1522 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1523 | X86_COND_E, EFLAGS))]>,
|
|---|
| 1524 | TB;
|
|---|
| 1525 | def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
|
|---|
| 1526 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1527 | "cmovne{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1528 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1529 | X86_COND_NE, EFLAGS))]>,
|
|---|
| 1530 | TB, OpSize;
|
|---|
| 1531 | def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
|
|---|
| 1532 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1533 | "cmovne{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1534 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1535 | X86_COND_NE, EFLAGS))]>,
|
|---|
| 1536 | TB;
|
|---|
| 1537 | def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
|
|---|
| 1538 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1539 | "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1540 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1541 | X86_COND_BE, EFLAGS))]>,
|
|---|
| 1542 | TB, OpSize;
|
|---|
| 1543 | def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
|
|---|
| 1544 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1545 | "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1546 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1547 | X86_COND_BE, EFLAGS))]>,
|
|---|
| 1548 | TB;
|
|---|
| 1549 | def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
|
|---|
| 1550 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1551 | "cmova{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1552 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1553 | X86_COND_A, EFLAGS))]>,
|
|---|
| 1554 | TB, OpSize;
|
|---|
| 1555 | def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
|
|---|
| 1556 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1557 | "cmova{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1558 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1559 | X86_COND_A, EFLAGS))]>,
|
|---|
| 1560 | TB;
|
|---|
| 1561 | def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
|
|---|
| 1562 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1563 | "cmovl{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1564 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1565 | X86_COND_L, EFLAGS))]>,
|
|---|
| 1566 | TB, OpSize;
|
|---|
| 1567 | def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
|
|---|
| 1568 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1569 | "cmovl{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1570 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1571 | X86_COND_L, EFLAGS))]>,
|
|---|
| 1572 | TB;
|
|---|
| 1573 | def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
|
|---|
| 1574 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1575 | "cmovge{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1576 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1577 | X86_COND_GE, EFLAGS))]>,
|
|---|
| 1578 | TB, OpSize;
|
|---|
| 1579 | def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
|
|---|
| 1580 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1581 | "cmovge{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1582 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1583 | X86_COND_GE, EFLAGS))]>,
|
|---|
| 1584 | TB;
|
|---|
| 1585 | def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
|
|---|
| 1586 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1587 | "cmovle{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1588 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1589 | X86_COND_LE, EFLAGS))]>,
|
|---|
| 1590 | TB, OpSize;
|
|---|
| 1591 | def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
|
|---|
| 1592 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1593 | "cmovle{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1594 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1595 | X86_COND_LE, EFLAGS))]>,
|
|---|
| 1596 | TB;
|
|---|
| 1597 | def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
|
|---|
| 1598 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1599 | "cmovg{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1600 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1601 | X86_COND_G, EFLAGS))]>,
|
|---|
| 1602 | TB, OpSize;
|
|---|
| 1603 | def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
|
|---|
| 1604 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1605 | "cmovg{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1606 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1607 | X86_COND_G, EFLAGS))]>,
|
|---|
| 1608 | TB;
|
|---|
| 1609 | def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
|
|---|
| 1610 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1611 | "cmovs{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1612 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1613 | X86_COND_S, EFLAGS))]>,
|
|---|
| 1614 | TB, OpSize;
|
|---|
| 1615 | def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
|
|---|
| 1616 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1617 | "cmovs{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1618 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1619 | X86_COND_S, EFLAGS))]>,
|
|---|
| 1620 | TB;
|
|---|
| 1621 | def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
|
|---|
| 1622 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1623 | "cmovns{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1624 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1625 | X86_COND_NS, EFLAGS))]>,
|
|---|
| 1626 | TB, OpSize;
|
|---|
| 1627 | def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
|
|---|
| 1628 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1629 | "cmovns{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1630 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1631 | X86_COND_NS, EFLAGS))]>,
|
|---|
| 1632 | TB;
|
|---|
| 1633 | def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
|
|---|
| 1634 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1635 | "cmovp{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1636 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1637 | X86_COND_P, EFLAGS))]>,
|
|---|
| 1638 | TB, OpSize;
|
|---|
| 1639 | def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
|
|---|
| 1640 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1641 | "cmovp{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1642 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1643 | X86_COND_P, EFLAGS))]>,
|
|---|
| 1644 | TB;
|
|---|
| 1645 | def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
|
|---|
| 1646 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1647 | "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1648 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1649 | X86_COND_NP, EFLAGS))]>,
|
|---|
| 1650 | TB, OpSize;
|
|---|
| 1651 | def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
|
|---|
| 1652 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1653 | "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1654 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1655 | X86_COND_NP, EFLAGS))]>,
|
|---|
| 1656 | TB;
|
|---|
| 1657 | def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
|
|---|
| 1658 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1659 | "cmovo{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1660 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1661 | X86_COND_O, EFLAGS))]>,
|
|---|
| 1662 | TB, OpSize;
|
|---|
| 1663 | def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
|
|---|
| 1664 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1665 | "cmovo{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1666 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1667 | X86_COND_O, EFLAGS))]>,
|
|---|
| 1668 | TB;
|
|---|
| 1669 | def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
|
|---|
| 1670 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1671 | "cmovno{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1672 | [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
|---|
| 1673 | X86_COND_NO, EFLAGS))]>,
|
|---|
| 1674 | TB, OpSize;
|
|---|
| 1675 | def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
|
|---|
| 1676 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1677 | "cmovno{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1678 | [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
|---|
| 1679 | X86_COND_NO, EFLAGS))]>,
|
|---|
| 1680 | TB;
|
|---|
| 1681 | } // Predicates = [HasCMov]
|
|---|
| 1682 |
|
|---|
| 1683 | // X86 doesn't have 8-bit conditional moves. Use a customInserter to
|
|---|
| 1684 | // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
|
|---|
| 1685 | // however that requires promoting the operands, and can induce additional
|
|---|
| 1686 | // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
|
|---|
| 1687 | // clobber EFLAGS, because if one of the operands is zero, the expansion
|
|---|
| 1688 | // could involve an xor.
|
|---|
| 1689 | let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
|
|---|
| 1690 | def CMOV_GR8 : I<0, Pseudo,
|
|---|
| 1691 | (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
|
|---|
| 1692 | "#CMOV_GR8 PSEUDO!",
|
|---|
| 1693 | [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
|
|---|
| 1694 | imm:$cond, EFLAGS))]>;
|
|---|
| 1695 |
|
|---|
| 1696 | let Predicates = [NoCMov] in {
|
|---|
| 1697 | def CMOV_GR32 : I<0, Pseudo,
|
|---|
| 1698 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
|
|---|
| 1699 | "#CMOV_GR32* PSEUDO!",
|
|---|
| 1700 | [(set GR32:$dst,
|
|---|
| 1701 | (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
|
|---|
| 1702 | def CMOV_GR16 : I<0, Pseudo,
|
|---|
| 1703 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
|
|---|
| 1704 | "#CMOV_GR16* PSEUDO!",
|
|---|
| 1705 | [(set GR16:$dst,
|
|---|
| 1706 | (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
|
|---|
| 1707 | def CMOV_RFP32 : I<0, Pseudo,
|
|---|
| 1708 | (outs RFP32:$dst),
|
|---|
| 1709 | (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
|
|---|
| 1710 | "#CMOV_RFP32 PSEUDO!",
|
|---|
| 1711 | [(set RFP32:$dst,
|
|---|
| 1712 | (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
|
|---|
| 1713 | EFLAGS))]>;
|
|---|
| 1714 | def CMOV_RFP64 : I<0, Pseudo,
|
|---|
| 1715 | (outs RFP64:$dst),
|
|---|
| 1716 | (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
|
|---|
| 1717 | "#CMOV_RFP64 PSEUDO!",
|
|---|
| 1718 | [(set RFP64:$dst,
|
|---|
| 1719 | (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
|
|---|
| 1720 | EFLAGS))]>;
|
|---|
| 1721 | def CMOV_RFP80 : I<0, Pseudo,
|
|---|
| 1722 | (outs RFP80:$dst),
|
|---|
| 1723 | (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
|
|---|
| 1724 | "#CMOV_RFP80 PSEUDO!",
|
|---|
| 1725 | [(set RFP80:$dst,
|
|---|
| 1726 | (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
|
|---|
| 1727 | EFLAGS))]>;
|
|---|
| 1728 | } // Predicates = [NoCMov]
|
|---|
| 1729 | } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
|
|---|
| 1730 | } // Uses = [EFLAGS]
|
|---|
| 1731 |
|
|---|
| 1732 |
|
|---|
| 1733 | // unary instructions
|
|---|
| 1734 | let CodeSize = 2 in {
|
|---|
| 1735 | let Defs = [EFLAGS] in {
|
|---|
| 1736 | def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 1737 | "neg{b}\t$dst",
|
|---|
| 1738 | [(set GR8:$dst, (ineg GR8:$src1)),
|
|---|
| 1739 | (implicit EFLAGS)]>;
|
|---|
| 1740 | def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 1741 | "neg{w}\t$dst",
|
|---|
| 1742 | [(set GR16:$dst, (ineg GR16:$src1)),
|
|---|
| 1743 | (implicit EFLAGS)]>, OpSize;
|
|---|
| 1744 | def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 1745 | "neg{l}\t$dst",
|
|---|
| 1746 | [(set GR32:$dst, (ineg GR32:$src1)),
|
|---|
| 1747 | (implicit EFLAGS)]>;
|
|---|
| 1748 |
|
|---|
| 1749 | let Constraints = "" in {
|
|---|
| 1750 | def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
|
|---|
| 1751 | "neg{b}\t$dst",
|
|---|
| 1752 | [(store (ineg (loadi8 addr:$dst)), addr:$dst),
|
|---|
| 1753 | (implicit EFLAGS)]>;
|
|---|
| 1754 | def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
|
|---|
| 1755 | "neg{w}\t$dst",
|
|---|
| 1756 | [(store (ineg (loadi16 addr:$dst)), addr:$dst),
|
|---|
| 1757 | (implicit EFLAGS)]>, OpSize;
|
|---|
| 1758 | def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
|
|---|
| 1759 | "neg{l}\t$dst",
|
|---|
| 1760 | [(store (ineg (loadi32 addr:$dst)), addr:$dst),
|
|---|
| 1761 | (implicit EFLAGS)]>;
|
|---|
| 1762 | } // Constraints = ""
|
|---|
| 1763 | } // Defs = [EFLAGS]
|
|---|
| 1764 |
|
|---|
| 1765 | // Match xor -1 to not. Favors these over a move imm + xor to save code size.
|
|---|
| 1766 | let AddedComplexity = 15 in {
|
|---|
| 1767 | def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 1768 | "not{b}\t$dst",
|
|---|
| 1769 | [(set GR8:$dst, (not GR8:$src1))]>;
|
|---|
| 1770 | def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 1771 | "not{w}\t$dst",
|
|---|
| 1772 | [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
|
|---|
| 1773 | def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 1774 | "not{l}\t$dst",
|
|---|
| 1775 | [(set GR32:$dst, (not GR32:$src1))]>;
|
|---|
| 1776 | }
|
|---|
| 1777 | let Constraints = "" in {
|
|---|
| 1778 | def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
|
|---|
| 1779 | "not{b}\t$dst",
|
|---|
| 1780 | [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
|
|---|
| 1781 | def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
|
|---|
| 1782 | "not{w}\t$dst",
|
|---|
| 1783 | [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
|
|---|
| 1784 | def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
|
|---|
| 1785 | "not{l}\t$dst",
|
|---|
| 1786 | [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
|
|---|
| 1787 | } // Constraints = ""
|
|---|
| 1788 | } // CodeSize
|
|---|
| 1789 |
|
|---|
| 1790 | // TODO: inc/dec is slow for P4, but fast for Pentium-M.
|
|---|
| 1791 | let Defs = [EFLAGS] in {
|
|---|
| 1792 | let CodeSize = 2 in
|
|---|
| 1793 | def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 1794 | "inc{b}\t$dst",
|
|---|
| 1795 | [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
|
|---|
| 1796 |
|
|---|
| 1797 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
|
|---|
| 1798 | def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 1799 | "inc{w}\t$dst",
|
|---|
| 1800 | [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
|
|---|
| 1801 | OpSize, Requires<[In32BitMode]>;
|
|---|
| 1802 | def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 1803 | "inc{l}\t$dst",
|
|---|
| 1804 | [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
|
|---|
| 1805 | Requires<[In32BitMode]>;
|
|---|
| 1806 | }
|
|---|
| 1807 | let Constraints = "", CodeSize = 2 in {
|
|---|
| 1808 | def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
|
|---|
| 1809 | [(store (add (loadi8 addr:$dst), 1), addr:$dst),
|
|---|
| 1810 | (implicit EFLAGS)]>;
|
|---|
| 1811 | def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
|
|---|
| 1812 | [(store (add (loadi16 addr:$dst), 1), addr:$dst),
|
|---|
| 1813 | (implicit EFLAGS)]>,
|
|---|
| 1814 | OpSize, Requires<[In32BitMode]>;
|
|---|
| 1815 | def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
|
|---|
| 1816 | [(store (add (loadi32 addr:$dst), 1), addr:$dst),
|
|---|
| 1817 | (implicit EFLAGS)]>,
|
|---|
| 1818 | Requires<[In32BitMode]>;
|
|---|
| 1819 | } // Constraints = "", CodeSize = 2
|
|---|
| 1820 |
|
|---|
| 1821 | let CodeSize = 2 in
|
|---|
| 1822 | def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 1823 | "dec{b}\t$dst",
|
|---|
| 1824 | [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
|
|---|
| 1825 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
|
|---|
| 1826 | def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 1827 | "dec{w}\t$dst",
|
|---|
| 1828 | [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
|
|---|
| 1829 | OpSize, Requires<[In32BitMode]>;
|
|---|
| 1830 | def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 1831 | "dec{l}\t$dst",
|
|---|
| 1832 | [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
|
|---|
| 1833 | Requires<[In32BitMode]>;
|
|---|
| 1834 | } // CodeSize = 2
|
|---|
| 1835 |
|
|---|
| 1836 | let Constraints = "", CodeSize = 2 in {
|
|---|
| 1837 | def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
|
|---|
| 1838 | [(store (add (loadi8 addr:$dst), -1), addr:$dst),
|
|---|
| 1839 | (implicit EFLAGS)]>;
|
|---|
| 1840 | def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
|
|---|
| 1841 | [(store (add (loadi16 addr:$dst), -1), addr:$dst),
|
|---|
| 1842 | (implicit EFLAGS)]>,
|
|---|
| 1843 | OpSize, Requires<[In32BitMode]>;
|
|---|
| 1844 | def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
|
|---|
| 1845 | [(store (add (loadi32 addr:$dst), -1), addr:$dst),
|
|---|
| 1846 | (implicit EFLAGS)]>,
|
|---|
| 1847 | Requires<[In32BitMode]>;
|
|---|
| 1848 | } // Constraints = "", CodeSize = 2
|
|---|
| 1849 | } // Defs = [EFLAGS]
|
|---|
| 1850 |
|
|---|
| 1851 | // Logical operators...
|
|---|
| 1852 | let Defs = [EFLAGS] in {
|
|---|
| 1853 | let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
|
|---|
| 1854 | def AND8rr : I<0x20, MRMDestReg,
|
|---|
| 1855 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
|
|---|
| 1856 | "and{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1857 | [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
|
|---|
| 1858 | def AND16rr : I<0x21, MRMDestReg,
|
|---|
| 1859 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 1860 | "and{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1861 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
|
|---|
| 1862 | GR16:$src2))]>, OpSize;
|
|---|
| 1863 | def AND32rr : I<0x21, MRMDestReg,
|
|---|
| 1864 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 1865 | "and{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1866 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
|
|---|
| 1867 | GR32:$src2))]>;
|
|---|
| 1868 | }
|
|---|
| 1869 |
|
|---|
| 1870 | // AND instructions with the destination register in REG and the source register
|
|---|
| 1871 | // in R/M. Included for the disassembler.
|
|---|
| 1872 | let isCodeGenOnly = 1 in {
|
|---|
| 1873 | def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
|---|
| 1874 | "and{b}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 1875 | def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
|
|---|
| 1876 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 1877 | "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
|
|---|
| 1878 | def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
|
|---|
| 1879 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 1880 | "and{l}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 1881 | }
|
|---|
| 1882 |
|
|---|
| 1883 | def AND8rm : I<0x22, MRMSrcMem,
|
|---|
| 1884 | (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
|
|---|
| 1885 | "and{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1886 | [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
|
|---|
| 1887 | (loadi8 addr:$src2)))]>;
|
|---|
| 1888 | def AND16rm : I<0x23, MRMSrcMem,
|
|---|
| 1889 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 1890 | "and{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1891 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
|
|---|
| 1892 | (loadi16 addr:$src2)))]>,
|
|---|
| 1893 | OpSize;
|
|---|
| 1894 | def AND32rm : I<0x23, MRMSrcMem,
|
|---|
| 1895 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 1896 | "and{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1897 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
|
|---|
| 1898 | (loadi32 addr:$src2)))]>;
|
|---|
| 1899 |
|
|---|
| 1900 | def AND8ri : Ii8<0x80, MRM4r,
|
|---|
| 1901 | (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
|
|---|
| 1902 | "and{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1903 | [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
|
|---|
| 1904 | imm:$src2))]>;
|
|---|
| 1905 | def AND16ri : Ii16<0x81, MRM4r,
|
|---|
| 1906 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
|
|---|
| 1907 | "and{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1908 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
|
|---|
| 1909 | imm:$src2))]>, OpSize;
|
|---|
| 1910 | def AND32ri : Ii32<0x81, MRM4r,
|
|---|
| 1911 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
|
|---|
| 1912 | "and{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1913 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
|
|---|
| 1914 | imm:$src2))]>;
|
|---|
| 1915 | def AND16ri8 : Ii8<0x83, MRM4r,
|
|---|
| 1916 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 1917 | "and{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1918 | [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
|
|---|
| 1919 | i16immSExt8:$src2))]>,
|
|---|
| 1920 | OpSize;
|
|---|
| 1921 | def AND32ri8 : Ii8<0x83, MRM4r,
|
|---|
| 1922 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 1923 | "and{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1924 | [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
|
|---|
| 1925 | i32immSExt8:$src2))]>;
|
|---|
| 1926 |
|
|---|
| 1927 | let Constraints = "" in {
|
|---|
| 1928 | def AND8mr : I<0x20, MRMDestMem,
|
|---|
| 1929 | (outs), (ins i8mem :$dst, GR8 :$src),
|
|---|
| 1930 | "and{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 1931 | [(store (and (load addr:$dst), GR8:$src), addr:$dst),
|
|---|
| 1932 | (implicit EFLAGS)]>;
|
|---|
| 1933 | def AND16mr : I<0x21, MRMDestMem,
|
|---|
| 1934 | (outs), (ins i16mem:$dst, GR16:$src),
|
|---|
| 1935 | "and{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 1936 | [(store (and (load addr:$dst), GR16:$src), addr:$dst),
|
|---|
| 1937 | (implicit EFLAGS)]>,
|
|---|
| 1938 | OpSize;
|
|---|
| 1939 | def AND32mr : I<0x21, MRMDestMem,
|
|---|
| 1940 | (outs), (ins i32mem:$dst, GR32:$src),
|
|---|
| 1941 | "and{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 1942 | [(store (and (load addr:$dst), GR32:$src), addr:$dst),
|
|---|
| 1943 | (implicit EFLAGS)]>;
|
|---|
| 1944 | def AND8mi : Ii8<0x80, MRM4m,
|
|---|
| 1945 | (outs), (ins i8mem :$dst, i8imm :$src),
|
|---|
| 1946 | "and{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 1947 | [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
|
|---|
| 1948 | (implicit EFLAGS)]>;
|
|---|
| 1949 | def AND16mi : Ii16<0x81, MRM4m,
|
|---|
| 1950 | (outs), (ins i16mem:$dst, i16imm:$src),
|
|---|
| 1951 | "and{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 1952 | [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
|
|---|
| 1953 | (implicit EFLAGS)]>,
|
|---|
| 1954 | OpSize;
|
|---|
| 1955 | def AND32mi : Ii32<0x81, MRM4m,
|
|---|
| 1956 | (outs), (ins i32mem:$dst, i32imm:$src),
|
|---|
| 1957 | "and{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 1958 | [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
|
|---|
| 1959 | (implicit EFLAGS)]>;
|
|---|
| 1960 | def AND16mi8 : Ii8<0x83, MRM4m,
|
|---|
| 1961 | (outs), (ins i16mem:$dst, i16i8imm :$src),
|
|---|
| 1962 | "and{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 1963 | [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
|
|---|
| 1964 | (implicit EFLAGS)]>,
|
|---|
| 1965 | OpSize;
|
|---|
| 1966 | def AND32mi8 : Ii8<0x83, MRM4m,
|
|---|
| 1967 | (outs), (ins i32mem:$dst, i32i8imm :$src),
|
|---|
| 1968 | "and{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 1969 | [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
|
|---|
| 1970 | (implicit EFLAGS)]>;
|
|---|
| 1971 |
|
|---|
| 1972 | def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
|
|---|
| 1973 | "and{b}\t{$src, %al|%al, $src}", []>;
|
|---|
| 1974 | def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
|
|---|
| 1975 | "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
|
|---|
| 1976 | def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
|
|---|
| 1977 | "and{l}\t{$src, %eax|%eax, $src}", []>;
|
|---|
| 1978 |
|
|---|
| 1979 | } // Constraints = ""
|
|---|
| 1980 |
|
|---|
| 1981 |
|
|---|
| 1982 | let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
|
|---|
| 1983 | def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
|
|---|
| 1984 | (ins GR8 :$src1, GR8 :$src2),
|
|---|
| 1985 | "or{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1986 | [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
|
|---|
| 1987 | def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
|
|---|
| 1988 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 1989 | "or{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1990 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
|
|---|
| 1991 | OpSize;
|
|---|
| 1992 | def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
|
|---|
| 1993 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 1994 | "or{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 1995 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
|
|---|
| 1996 | }
|
|---|
| 1997 |
|
|---|
| 1998 | // OR instructions with the destination register in REG and the source register
|
|---|
| 1999 | // in R/M. Included for the disassembler.
|
|---|
| 2000 | let isCodeGenOnly = 1 in {
|
|---|
| 2001 | def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
|---|
| 2002 | "or{b}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 2003 | def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
|
|---|
| 2004 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 2005 | "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
|
|---|
| 2006 | def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
|
|---|
| 2007 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 2008 | "or{l}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 2009 | }
|
|---|
| 2010 |
|
|---|
| 2011 | def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
|
|---|
| 2012 | (ins GR8 :$src1, i8mem :$src2),
|
|---|
| 2013 | "or{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2014 | [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
|
|---|
| 2015 | (load addr:$src2)))]>;
|
|---|
| 2016 | def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
|
|---|
| 2017 | (ins GR16:$src1, i16mem:$src2),
|
|---|
| 2018 | "or{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2019 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
|
|---|
| 2020 | (load addr:$src2)))]>,
|
|---|
| 2021 | OpSize;
|
|---|
| 2022 | def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
|
|---|
| 2023 | (ins GR32:$src1, i32mem:$src2),
|
|---|
| 2024 | "or{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2025 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
|
|---|
| 2026 | (load addr:$src2)))]>;
|
|---|
| 2027 |
|
|---|
| 2028 | def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
|
|---|
| 2029 | (ins GR8 :$src1, i8imm:$src2),
|
|---|
| 2030 | "or{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2031 | [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
|
|---|
| 2032 | def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
|
|---|
| 2033 | (ins GR16:$src1, i16imm:$src2),
|
|---|
| 2034 | "or{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2035 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
|
|---|
| 2036 | imm:$src2))]>, OpSize;
|
|---|
| 2037 | def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
|
|---|
| 2038 | (ins GR32:$src1, i32imm:$src2),
|
|---|
| 2039 | "or{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2040 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
|
|---|
| 2041 | imm:$src2))]>;
|
|---|
| 2042 |
|
|---|
| 2043 | def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
|
|---|
| 2044 | (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 2045 | "or{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2046 | [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
|
|---|
| 2047 | i16immSExt8:$src2))]>, OpSize;
|
|---|
| 2048 | def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
|
|---|
| 2049 | (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 2050 | "or{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2051 | [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
|
|---|
| 2052 | i32immSExt8:$src2))]>;
|
|---|
| 2053 | let Constraints = "" in {
|
|---|
| 2054 | def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
|
|---|
| 2055 | "or{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 2056 | [(store (or (load addr:$dst), GR8:$src), addr:$dst),
|
|---|
| 2057 | (implicit EFLAGS)]>;
|
|---|
| 2058 | def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
|---|
| 2059 | "or{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 2060 | [(store (or (load addr:$dst), GR16:$src), addr:$dst),
|
|---|
| 2061 | (implicit EFLAGS)]>, OpSize;
|
|---|
| 2062 | def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
|---|
| 2063 | "or{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 2064 | [(store (or (load addr:$dst), GR32:$src), addr:$dst),
|
|---|
| 2065 | (implicit EFLAGS)]>;
|
|---|
| 2066 | def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
|
|---|
| 2067 | "or{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 2068 | [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
|
|---|
| 2069 | (implicit EFLAGS)]>;
|
|---|
| 2070 | def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
|
|---|
| 2071 | "or{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 2072 | [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
|
|---|
| 2073 | (implicit EFLAGS)]>,
|
|---|
| 2074 | OpSize;
|
|---|
| 2075 | def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
|
|---|
| 2076 | "or{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 2077 | [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
|
|---|
| 2078 | (implicit EFLAGS)]>;
|
|---|
| 2079 | def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
|
|---|
| 2080 | "or{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 2081 | [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
|
|---|
| 2082 | (implicit EFLAGS)]>,
|
|---|
| 2083 | OpSize;
|
|---|
| 2084 | def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
|
|---|
| 2085 | "or{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 2086 | [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
|
|---|
| 2087 | (implicit EFLAGS)]>;
|
|---|
| 2088 |
|
|---|
| 2089 | def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
|
|---|
| 2090 | "or{b}\t{$src, %al|%al, $src}", []>;
|
|---|
| 2091 | def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
|
|---|
| 2092 | "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
|
|---|
| 2093 | def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
|
|---|
| 2094 | "or{l}\t{$src, %eax|%eax, $src}", []>;
|
|---|
| 2095 | } // Constraints = ""
|
|---|
| 2096 |
|
|---|
| 2097 |
|
|---|
| 2098 | let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
|
|---|
| 2099 | def XOR8rr : I<0x30, MRMDestReg,
|
|---|
| 2100 | (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
|
|---|
| 2101 | "xor{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2102 | [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
|
|---|
| 2103 | GR8:$src2))]>;
|
|---|
| 2104 | def XOR16rr : I<0x31, MRMDestReg,
|
|---|
| 2105 | (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
|
|---|
| 2106 | "xor{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2107 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
|
|---|
| 2108 | GR16:$src2))]>, OpSize;
|
|---|
| 2109 | def XOR32rr : I<0x31, MRMDestReg,
|
|---|
| 2110 | (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|---|
| 2111 | "xor{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2112 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
|
|---|
| 2113 | GR32:$src2))]>;
|
|---|
| 2114 | } // isCommutable = 1
|
|---|
| 2115 |
|
|---|
| 2116 | // XOR instructions with the destination register in REG and the source register
|
|---|
| 2117 | // in R/M. Included for the disassembler.
|
|---|
| 2118 | let isCodeGenOnly = 1 in {
|
|---|
| 2119 | def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
|---|
| 2120 | "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 2121 | def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
|
|---|
| 2122 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 2123 | "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
|
|---|
| 2124 | def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
|
|---|
| 2125 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 2126 | "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 2127 | }
|
|---|
| 2128 |
|
|---|
| 2129 | def XOR8rm : I<0x32, MRMSrcMem,
|
|---|
| 2130 | (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
|
|---|
| 2131 | "xor{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2132 | [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
|
|---|
| 2133 | (load addr:$src2)))]>;
|
|---|
| 2134 | def XOR16rm : I<0x33, MRMSrcMem,
|
|---|
| 2135 | (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 2136 | "xor{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2137 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
|
|---|
| 2138 | (load addr:$src2)))]>,
|
|---|
| 2139 | OpSize;
|
|---|
| 2140 | def XOR32rm : I<0x33, MRMSrcMem,
|
|---|
| 2141 | (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 2142 | "xor{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2143 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
|
|---|
| 2144 | (load addr:$src2)))]>;
|
|---|
| 2145 |
|
|---|
| 2146 | def XOR8ri : Ii8<0x80, MRM6r,
|
|---|
| 2147 | (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
|---|
| 2148 | "xor{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2149 | [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
|
|---|
| 2150 | def XOR16ri : Ii16<0x81, MRM6r,
|
|---|
| 2151 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
|
|---|
| 2152 | "xor{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2153 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
|
|---|
| 2154 | imm:$src2))]>, OpSize;
|
|---|
| 2155 | def XOR32ri : Ii32<0x81, MRM6r,
|
|---|
| 2156 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
|
|---|
| 2157 | "xor{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2158 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
|
|---|
| 2159 | imm:$src2))]>;
|
|---|
| 2160 | def XOR16ri8 : Ii8<0x83, MRM6r,
|
|---|
| 2161 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 2162 | "xor{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2163 | [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
|
|---|
| 2164 | i16immSExt8:$src2))]>,
|
|---|
| 2165 | OpSize;
|
|---|
| 2166 | def XOR32ri8 : Ii8<0x83, MRM6r,
|
|---|
| 2167 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 2168 | "xor{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2169 | [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
|
|---|
| 2170 | i32immSExt8:$src2))]>;
|
|---|
| 2171 |
|
|---|
| 2172 | let Constraints = "" in {
|
|---|
| 2173 | def XOR8mr : I<0x30, MRMDestMem,
|
|---|
| 2174 | (outs), (ins i8mem :$dst, GR8 :$src),
|
|---|
| 2175 | "xor{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 2176 | [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
|
|---|
| 2177 | (implicit EFLAGS)]>;
|
|---|
| 2178 | def XOR16mr : I<0x31, MRMDestMem,
|
|---|
| 2179 | (outs), (ins i16mem:$dst, GR16:$src),
|
|---|
| 2180 | "xor{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 2181 | [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
|
|---|
| 2182 | (implicit EFLAGS)]>,
|
|---|
| 2183 | OpSize;
|
|---|
| 2184 | def XOR32mr : I<0x31, MRMDestMem,
|
|---|
| 2185 | (outs), (ins i32mem:$dst, GR32:$src),
|
|---|
| 2186 | "xor{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 2187 | [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
|
|---|
| 2188 | (implicit EFLAGS)]>;
|
|---|
| 2189 | def XOR8mi : Ii8<0x80, MRM6m,
|
|---|
| 2190 | (outs), (ins i8mem :$dst, i8imm :$src),
|
|---|
| 2191 | "xor{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 2192 | [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
|
|---|
| 2193 | (implicit EFLAGS)]>;
|
|---|
| 2194 | def XOR16mi : Ii16<0x81, MRM6m,
|
|---|
| 2195 | (outs), (ins i16mem:$dst, i16imm:$src),
|
|---|
| 2196 | "xor{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 2197 | [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
|
|---|
| 2198 | (implicit EFLAGS)]>,
|
|---|
| 2199 | OpSize;
|
|---|
| 2200 | def XOR32mi : Ii32<0x81, MRM6m,
|
|---|
| 2201 | (outs), (ins i32mem:$dst, i32imm:$src),
|
|---|
| 2202 | "xor{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 2203 | [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
|
|---|
| 2204 | (implicit EFLAGS)]>;
|
|---|
| 2205 | def XOR16mi8 : Ii8<0x83, MRM6m,
|
|---|
| 2206 | (outs), (ins i16mem:$dst, i16i8imm :$src),
|
|---|
| 2207 | "xor{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 2208 | [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
|
|---|
| 2209 | (implicit EFLAGS)]>,
|
|---|
| 2210 | OpSize;
|
|---|
| 2211 | def XOR32mi8 : Ii8<0x83, MRM6m,
|
|---|
| 2212 | (outs), (ins i32mem:$dst, i32i8imm :$src),
|
|---|
| 2213 | "xor{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 2214 | [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
|
|---|
| 2215 | (implicit EFLAGS)]>;
|
|---|
| 2216 |
|
|---|
| 2217 | def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
|
|---|
| 2218 | "xor{b}\t{$src, %al|%al, $src}", []>;
|
|---|
| 2219 | def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
|
|---|
| 2220 | "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
|
|---|
| 2221 | def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
|
|---|
| 2222 | "xor{l}\t{$src, %eax|%eax, $src}", []>;
|
|---|
| 2223 | } // Constraints = ""
|
|---|
| 2224 | } // Defs = [EFLAGS]
|
|---|
| 2225 |
|
|---|
| 2226 | // Shift instructions
|
|---|
| 2227 | let Defs = [EFLAGS] in {
|
|---|
| 2228 | let Uses = [CL] in {
|
|---|
| 2229 | def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 2230 | "shl{b}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2231 | [(set GR8:$dst, (shl GR8:$src1, CL))]>;
|
|---|
| 2232 | def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2233 | "shl{w}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2234 | [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
|
|---|
| 2235 | def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2236 | "shl{l}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2237 | [(set GR32:$dst, (shl GR32:$src1, CL))]>;
|
|---|
| 2238 | } // Uses = [CL]
|
|---|
| 2239 |
|
|---|
| 2240 | def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
|---|
| 2241 | "shl{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2242 | [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
|
|---|
| 2243 |
|
|---|
| 2244 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
|
|---|
| 2245 | def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
|---|
| 2246 | "shl{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2247 | [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
|
|---|
| 2248 | def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
|---|
| 2249 | "shl{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2250 | [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
|
|---|
| 2251 |
|
|---|
| 2252 | // NOTE: We don't include patterns for shifts of a register by one, because
|
|---|
| 2253 | // 'add reg,reg' is cheaper.
|
|---|
| 2254 |
|
|---|
| 2255 | def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
|
|---|
| 2256 | "shl{b}\t$dst", []>;
|
|---|
| 2257 | def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2258 | "shl{w}\t$dst", []>, OpSize;
|
|---|
| 2259 | def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2260 | "shl{l}\t$dst", []>;
|
|---|
| 2261 |
|
|---|
| 2262 | } // isConvertibleToThreeAddress = 1
|
|---|
| 2263 |
|
|---|
| 2264 | let Constraints = "" in {
|
|---|
| 2265 | let Uses = [CL] in {
|
|---|
| 2266 | def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
|
|---|
| 2267 | "shl{b}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2268 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
|
|---|
| 2269 | def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
|
|---|
| 2270 | "shl{w}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2271 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
|
|---|
| 2272 | def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
|
|---|
| 2273 | "shl{l}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2274 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
|
|---|
| 2275 | }
|
|---|
| 2276 | def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
|
|---|
| 2277 | "shl{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 2278 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|---|
| 2279 | def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
|
|---|
| 2280 | "shl{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 2281 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
|
|---|
| 2282 | OpSize;
|
|---|
| 2283 | def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
|
|---|
| 2284 | "shl{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 2285 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|---|
| 2286 |
|
|---|
| 2287 | // Shift by 1
|
|---|
| 2288 | def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
|
|---|
| 2289 | "shl{b}\t$dst",
|
|---|
| 2290 | [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
|
|---|
| 2291 | def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
|
|---|
| 2292 | "shl{w}\t$dst",
|
|---|
| 2293 | [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
|
|---|
| 2294 | OpSize;
|
|---|
| 2295 | def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
|
|---|
| 2296 | "shl{l}\t$dst",
|
|---|
| 2297 | [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
|---|
| 2298 | } // Constraints = ""
|
|---|
| 2299 |
|
|---|
| 2300 | let Uses = [CL] in {
|
|---|
| 2301 | def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 2302 | "shr{b}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2303 | [(set GR8:$dst, (srl GR8:$src1, CL))]>;
|
|---|
| 2304 | def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2305 | "shr{w}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2306 | [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
|
|---|
| 2307 | def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2308 | "shr{l}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2309 | [(set GR32:$dst, (srl GR32:$src1, CL))]>;
|
|---|
| 2310 | }
|
|---|
| 2311 |
|
|---|
| 2312 | def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
|---|
| 2313 | "shr{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2314 | [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
|
|---|
| 2315 | def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
|---|
| 2316 | "shr{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2317 | [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
|
|---|
| 2318 | def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
|---|
| 2319 | "shr{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2320 | [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
|
|---|
| 2321 |
|
|---|
| 2322 | // Shift by 1
|
|---|
| 2323 | def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
|
|---|
| 2324 | "shr{b}\t$dst",
|
|---|
| 2325 | [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
|
|---|
| 2326 | def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2327 | "shr{w}\t$dst",
|
|---|
| 2328 | [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
|
|---|
| 2329 | def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2330 | "shr{l}\t$dst",
|
|---|
| 2331 | [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
|
|---|
| 2332 |
|
|---|
| 2333 | let Constraints = "" in {
|
|---|
| 2334 | let Uses = [CL] in {
|
|---|
| 2335 | def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
|
|---|
| 2336 | "shr{b}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2337 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
|
|---|
| 2338 | def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
|
|---|
| 2339 | "shr{w}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2340 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
|
|---|
| 2341 | OpSize;
|
|---|
| 2342 | def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
|
|---|
| 2343 | "shr{l}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2344 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
|
|---|
| 2345 | }
|
|---|
| 2346 | def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
|
|---|
| 2347 | "shr{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 2348 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|---|
| 2349 | def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
|
|---|
| 2350 | "shr{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 2351 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
|
|---|
| 2352 | OpSize;
|
|---|
| 2353 | def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
|
|---|
| 2354 | "shr{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 2355 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|---|
| 2356 |
|
|---|
| 2357 | // Shift by 1
|
|---|
| 2358 | def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
|
|---|
| 2359 | "shr{b}\t$dst",
|
|---|
| 2360 | [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
|
|---|
| 2361 | def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
|
|---|
| 2362 | "shr{w}\t$dst",
|
|---|
| 2363 | [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
|
|---|
| 2364 | def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
|
|---|
| 2365 | "shr{l}\t$dst",
|
|---|
| 2366 | [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
|---|
| 2367 | } // Constraints = ""
|
|---|
| 2368 |
|
|---|
| 2369 | let Uses = [CL] in {
|
|---|
| 2370 | def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 2371 | "sar{b}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2372 | [(set GR8:$dst, (sra GR8:$src1, CL))]>;
|
|---|
| 2373 | def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2374 | "sar{w}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2375 | [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
|
|---|
| 2376 | def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2377 | "sar{l}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2378 | [(set GR32:$dst, (sra GR32:$src1, CL))]>;
|
|---|
| 2379 | }
|
|---|
| 2380 |
|
|---|
| 2381 | def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
|---|
| 2382 | "sar{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2383 | [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
|
|---|
| 2384 | def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
|---|
| 2385 | "sar{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2386 | [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
|
|---|
| 2387 | OpSize;
|
|---|
| 2388 | def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
|---|
| 2389 | "sar{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2390 | [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
|
|---|
| 2391 |
|
|---|
| 2392 | // Shift by 1
|
|---|
| 2393 | def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 2394 | "sar{b}\t$dst",
|
|---|
| 2395 | [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
|
|---|
| 2396 | def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2397 | "sar{w}\t$dst",
|
|---|
| 2398 | [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
|
|---|
| 2399 | def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2400 | "sar{l}\t$dst",
|
|---|
| 2401 | [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
|
|---|
| 2402 |
|
|---|
| 2403 | let Constraints = "" in {
|
|---|
| 2404 | let Uses = [CL] in {
|
|---|
| 2405 | def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
|
|---|
| 2406 | "sar{b}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2407 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
|
|---|
| 2408 | def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
|
|---|
| 2409 | "sar{w}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2410 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
|
|---|
| 2411 | def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
|
|---|
| 2412 | "sar{l}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2413 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
|
|---|
| 2414 | }
|
|---|
| 2415 | def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
|
|---|
| 2416 | "sar{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 2417 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|---|
| 2418 | def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
|
|---|
| 2419 | "sar{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 2420 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
|
|---|
| 2421 | OpSize;
|
|---|
| 2422 | def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
|
|---|
| 2423 | "sar{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 2424 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|---|
| 2425 |
|
|---|
| 2426 | // Shift by 1
|
|---|
| 2427 | def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
|
|---|
| 2428 | "sar{b}\t$dst",
|
|---|
| 2429 | [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
|
|---|
| 2430 | def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
|
|---|
| 2431 | "sar{w}\t$dst",
|
|---|
| 2432 | [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
|
|---|
| 2433 | OpSize;
|
|---|
| 2434 | def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
|
|---|
| 2435 | "sar{l}\t$dst",
|
|---|
| 2436 | [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
|---|
| 2437 | } // Constraints = ""
|
|---|
| 2438 |
|
|---|
| 2439 | // Rotate instructions
|
|---|
| 2440 |
|
|---|
| 2441 | def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
|
|---|
| 2442 | "rcl{b}\t{1, $dst|$dst, 1}", []>;
|
|---|
| 2443 | let Uses = [CL] in {
|
|---|
| 2444 | def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
|
|---|
| 2445 | "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
|
|---|
| 2446 | }
|
|---|
| 2447 | def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
|
|---|
| 2448 | "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|---|
| 2449 |
|
|---|
| 2450 | def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2451 | "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
|
|---|
| 2452 | let Uses = [CL] in {
|
|---|
| 2453 | def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2454 | "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
|---|
| 2455 | }
|
|---|
| 2456 | def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
|
|---|
| 2457 | "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
|
|---|
| 2458 |
|
|---|
| 2459 | def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2460 | "rcl{l}\t{1, $dst|$dst, 1}", []>;
|
|---|
| 2461 | let Uses = [CL] in {
|
|---|
| 2462 | def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2463 | "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
|
|---|
| 2464 | }
|
|---|
| 2465 | def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
|
|---|
| 2466 | "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|---|
| 2467 |
|
|---|
| 2468 | def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
|
|---|
| 2469 | "rcr{b}\t{1, $dst|$dst, 1}", []>;
|
|---|
| 2470 | let Uses = [CL] in {
|
|---|
| 2471 | def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
|
|---|
| 2472 | "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
|
|---|
| 2473 | }
|
|---|
| 2474 | def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
|
|---|
| 2475 | "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|---|
| 2476 |
|
|---|
| 2477 | def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2478 | "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
|
|---|
| 2479 | let Uses = [CL] in {
|
|---|
| 2480 | def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2481 | "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
|---|
| 2482 | }
|
|---|
| 2483 | def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
|
|---|
| 2484 | "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
|
|---|
| 2485 |
|
|---|
| 2486 | def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2487 | "rcr{l}\t{1, $dst|$dst, 1}", []>;
|
|---|
| 2488 | let Uses = [CL] in {
|
|---|
| 2489 | def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2490 | "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
|
|---|
| 2491 | }
|
|---|
| 2492 | def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
|
|---|
| 2493 | "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|---|
| 2494 |
|
|---|
| 2495 | let Constraints = "" in {
|
|---|
| 2496 | def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
|
|---|
| 2497 | "rcl{b}\t{1, $dst|$dst, 1}", []>;
|
|---|
| 2498 | def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
|
|---|
| 2499 | "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|---|
| 2500 | def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
|
|---|
| 2501 | "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
|
|---|
| 2502 | def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
|
|---|
| 2503 | "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
|
|---|
| 2504 | def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
|
|---|
| 2505 | "rcl{l}\t{1, $dst|$dst, 1}", []>;
|
|---|
| 2506 | def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
|
|---|
| 2507 | "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|---|
| 2508 | def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
|
|---|
| 2509 | "rcr{b}\t{1, $dst|$dst, 1}", []>;
|
|---|
| 2510 | def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
|
|---|
| 2511 | "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|---|
| 2512 | def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
|
|---|
| 2513 | "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
|
|---|
| 2514 | def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
|
|---|
| 2515 | "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
|
|---|
| 2516 | def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
|
|---|
| 2517 | "rcr{l}\t{1, $dst|$dst, 1}", []>;
|
|---|
| 2518 | def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
|
|---|
| 2519 | "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
|
|---|
| 2520 |
|
|---|
| 2521 | let Uses = [CL] in {
|
|---|
| 2522 | def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
|
|---|
| 2523 | "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
|
|---|
| 2524 | def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
|
|---|
| 2525 | "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
|---|
| 2526 | def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
|
|---|
| 2527 | "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
|
|---|
| 2528 | def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
|
|---|
| 2529 | "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
|
|---|
| 2530 | def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
|
|---|
| 2531 | "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
|
|---|
| 2532 | def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
|
|---|
| 2533 | "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
|
|---|
| 2534 | }
|
|---|
| 2535 | } // Constraints = ""
|
|---|
| 2536 |
|
|---|
| 2537 | // FIXME: provide shorter instructions when imm8 == 1
|
|---|
| 2538 | let Uses = [CL] in {
|
|---|
| 2539 | def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 2540 | "rol{b}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2541 | [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
|
|---|
| 2542 | def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2543 | "rol{w}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2544 | [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
|
|---|
| 2545 | def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2546 | "rol{l}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2547 | [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
|
|---|
| 2548 | }
|
|---|
| 2549 |
|
|---|
| 2550 | def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
|---|
| 2551 | "rol{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2552 | [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
|
|---|
| 2553 | def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
|---|
| 2554 | "rol{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2555 | [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
|
|---|
| 2556 | OpSize;
|
|---|
| 2557 | def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
|---|
| 2558 | "rol{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2559 | [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
|
|---|
| 2560 |
|
|---|
| 2561 | // Rotate by 1
|
|---|
| 2562 | def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 2563 | "rol{b}\t$dst",
|
|---|
| 2564 | [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
|
|---|
| 2565 | def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2566 | "rol{w}\t$dst",
|
|---|
| 2567 | [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
|
|---|
| 2568 | def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2569 | "rol{l}\t$dst",
|
|---|
| 2570 | [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
|
|---|
| 2571 |
|
|---|
| 2572 | let Constraints = "" in {
|
|---|
| 2573 | let Uses = [CL] in {
|
|---|
| 2574 | def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
|
|---|
| 2575 | "rol{b}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2576 | [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
|
|---|
| 2577 | def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
|
|---|
| 2578 | "rol{w}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2579 | [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
|
|---|
| 2580 | def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
|
|---|
| 2581 | "rol{l}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2582 | [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
|
|---|
| 2583 | }
|
|---|
| 2584 | def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
|
|---|
| 2585 | "rol{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 2586 | [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|---|
| 2587 | def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
|
|---|
| 2588 | "rol{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 2589 | [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
|
|---|
| 2590 | OpSize;
|
|---|
| 2591 | def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
|
|---|
| 2592 | "rol{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 2593 | [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|---|
| 2594 |
|
|---|
| 2595 | // Rotate by 1
|
|---|
| 2596 | def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
|
|---|
| 2597 | "rol{b}\t$dst",
|
|---|
| 2598 | [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
|
|---|
| 2599 | def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
|
|---|
| 2600 | "rol{w}\t$dst",
|
|---|
| 2601 | [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
|
|---|
| 2602 | OpSize;
|
|---|
| 2603 | def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
|
|---|
| 2604 | "rol{l}\t$dst",
|
|---|
| 2605 | [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
|---|
| 2606 | } // Constraints = ""
|
|---|
| 2607 |
|
|---|
| 2608 | let Uses = [CL] in {
|
|---|
| 2609 | def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 2610 | "ror{b}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2611 | [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
|
|---|
| 2612 | def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2613 | "ror{w}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2614 | [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
|
|---|
| 2615 | def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2616 | "ror{l}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2617 | [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
|
|---|
| 2618 | }
|
|---|
| 2619 |
|
|---|
| 2620 | def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
|---|
| 2621 | "ror{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2622 | [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
|
|---|
| 2623 | def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
|---|
| 2624 | "ror{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2625 | [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
|
|---|
| 2626 | OpSize;
|
|---|
| 2627 | def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
|---|
| 2628 | "ror{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2629 | [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
|
|---|
| 2630 |
|
|---|
| 2631 | // Rotate by 1
|
|---|
| 2632 | def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
|
|---|
| 2633 | "ror{b}\t$dst",
|
|---|
| 2634 | [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
|
|---|
| 2635 | def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
|---|
| 2636 | "ror{w}\t$dst",
|
|---|
| 2637 | [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
|
|---|
| 2638 | def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
|---|
| 2639 | "ror{l}\t$dst",
|
|---|
| 2640 | [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
|
|---|
| 2641 |
|
|---|
| 2642 | let Constraints = "" in {
|
|---|
| 2643 | let Uses = [CL] in {
|
|---|
| 2644 | def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
|
|---|
| 2645 | "ror{b}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2646 | [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
|
|---|
| 2647 | def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
|
|---|
| 2648 | "ror{w}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2649 | [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
|
|---|
| 2650 | def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
|
|---|
| 2651 | "ror{l}\t{%cl, $dst|$dst, CL}",
|
|---|
| 2652 | [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
|
|---|
| 2653 | }
|
|---|
| 2654 | def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
|
|---|
| 2655 | "ror{b}\t{$src, $dst|$dst, $src}",
|
|---|
| 2656 | [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|---|
| 2657 | def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
|
|---|
| 2658 | "ror{w}\t{$src, $dst|$dst, $src}",
|
|---|
| 2659 | [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
|
|---|
| 2660 | OpSize;
|
|---|
| 2661 | def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
|
|---|
| 2662 | "ror{l}\t{$src, $dst|$dst, $src}",
|
|---|
| 2663 | [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
|
|---|
| 2664 |
|
|---|
| 2665 | // Rotate by 1
|
|---|
| 2666 | def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
|
|---|
| 2667 | "ror{b}\t$dst",
|
|---|
| 2668 | [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
|
|---|
| 2669 | def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
|
|---|
| 2670 | "ror{w}\t$dst",
|
|---|
| 2671 | [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
|
|---|
| 2672 | OpSize;
|
|---|
| 2673 | def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
|
|---|
| 2674 | "ror{l}\t$dst",
|
|---|
| 2675 | [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
|
|---|
| 2676 | } // Constraints = ""
|
|---|
| 2677 |
|
|---|
| 2678 |
|
|---|
| 2679 | // Double shift instructions (generalizations of rotate)
|
|---|
| 2680 | let Uses = [CL] in {
|
|---|
| 2681 | def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
|
|---|
| 2682 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 2683 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
|---|
| 2684 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
|
|---|
| 2685 | def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
|
|---|
| 2686 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 2687 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
|---|
| 2688 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
|
|---|
| 2689 | def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
|
|---|
| 2690 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 2691 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
|---|
| 2692 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
|
|---|
| 2693 | TB, OpSize;
|
|---|
| 2694 | def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
|
|---|
| 2695 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 2696 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
|---|
| 2697 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
|
|---|
| 2698 | TB, OpSize;
|
|---|
| 2699 | }
|
|---|
| 2700 |
|
|---|
| 2701 | let isCommutable = 1 in { // These instructions commute to each other.
|
|---|
| 2702 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
|
|---|
| 2703 | (outs GR32:$dst),
|
|---|
| 2704 | (ins GR32:$src1, GR32:$src2, i8imm:$src3),
|
|---|
| 2705 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|---|
| 2706 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
|
|---|
| 2707 | (i8 imm:$src3)))]>,
|
|---|
| 2708 | TB;
|
|---|
| 2709 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
|
|---|
| 2710 | (outs GR32:$dst),
|
|---|
| 2711 | (ins GR32:$src1, GR32:$src2, i8imm:$src3),
|
|---|
| 2712 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|---|
| 2713 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
|
|---|
| 2714 | (i8 imm:$src3)))]>,
|
|---|
| 2715 | TB;
|
|---|
| 2716 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
|
|---|
| 2717 | (outs GR16:$dst),
|
|---|
| 2718 | (ins GR16:$src1, GR16:$src2, i8imm:$src3),
|
|---|
| 2719 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|---|
| 2720 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
|
|---|
| 2721 | (i8 imm:$src3)))]>,
|
|---|
| 2722 | TB, OpSize;
|
|---|
| 2723 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
|
|---|
| 2724 | (outs GR16:$dst),
|
|---|
| 2725 | (ins GR16:$src1, GR16:$src2, i8imm:$src3),
|
|---|
| 2726 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|---|
| 2727 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
|
|---|
| 2728 | (i8 imm:$src3)))]>,
|
|---|
| 2729 | TB, OpSize;
|
|---|
| 2730 | }
|
|---|
| 2731 |
|
|---|
| 2732 | let Constraints = "" in {
|
|---|
| 2733 | let Uses = [CL] in {
|
|---|
| 2734 | def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
|---|
| 2735 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
|---|
| 2736 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
|
|---|
| 2737 | addr:$dst)]>, TB;
|
|---|
| 2738 | def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
|---|
| 2739 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
|---|
| 2740 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
|
|---|
| 2741 | addr:$dst)]>, TB;
|
|---|
| 2742 | }
|
|---|
| 2743 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
|
|---|
| 2744 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
|
|---|
| 2745 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|---|
| 2746 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
|
|---|
| 2747 | (i8 imm:$src3)), addr:$dst)]>,
|
|---|
| 2748 | TB;
|
|---|
| 2749 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
|
|---|
| 2750 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
|
|---|
| 2751 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|---|
| 2752 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
|
|---|
| 2753 | (i8 imm:$src3)), addr:$dst)]>,
|
|---|
| 2754 | TB;
|
|---|
| 2755 |
|
|---|
| 2756 | let Uses = [CL] in {
|
|---|
| 2757 | def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
|---|
| 2758 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
|---|
| 2759 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
|
|---|
| 2760 | addr:$dst)]>, TB, OpSize;
|
|---|
| 2761 | def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
|---|
| 2762 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
|
|---|
| 2763 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
|
|---|
| 2764 | addr:$dst)]>, TB, OpSize;
|
|---|
| 2765 | }
|
|---|
| 2766 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
|
|---|
| 2767 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
|
|---|
| 2768 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|---|
| 2769 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
|
|---|
| 2770 | (i8 imm:$src3)), addr:$dst)]>,
|
|---|
| 2771 | TB, OpSize;
|
|---|
| 2772 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
|
|---|
| 2773 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
|
|---|
| 2774 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|---|
| 2775 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
|
|---|
| 2776 | (i8 imm:$src3)), addr:$dst)]>,
|
|---|
| 2777 | TB, OpSize;
|
|---|
| 2778 | } // Constraints = ""
|
|---|
| 2779 | } // Defs = [EFLAGS]
|
|---|
| 2780 |
|
|---|
| 2781 |
|
|---|
| 2782 | // Arithmetic.
|
|---|
| 2783 | let Defs = [EFLAGS] in {
|
|---|
| 2784 | let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
|
|---|
| 2785 | // Register-Register Addition
|
|---|
| 2786 | def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
|
|---|
| 2787 | (ins GR8 :$src1, GR8 :$src2),
|
|---|
| 2788 | "add{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2789 | [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
|
|---|
| 2790 |
|
|---|
| 2791 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
|
|---|
| 2792 | // Register-Register Addition
|
|---|
| 2793 | def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
|
|---|
| 2794 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 2795 | "add{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2796 | [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
|
|---|
| 2797 | GR16:$src2))]>, OpSize;
|
|---|
| 2798 | def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
|
|---|
| 2799 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 2800 | "add{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2801 | [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
|
|---|
| 2802 | GR32:$src2))]>;
|
|---|
| 2803 | } // end isConvertibleToThreeAddress
|
|---|
| 2804 | } // end isCommutable
|
|---|
| 2805 |
|
|---|
| 2806 | // These are alternate spellings for use by the disassembler, we mark them as
|
|---|
| 2807 | // code gen only to ensure they aren't matched by the assembler.
|
|---|
| 2808 | let isCodeGenOnly = 1 in {
|
|---|
| 2809 | def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
|---|
| 2810 | "add{b}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 2811 | def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
|
|---|
| 2812 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
|
|---|
| 2813 | def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
|
|---|
| 2814 | "add{l}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 2815 | }
|
|---|
| 2816 |
|
|---|
| 2817 | // Register-Memory Addition
|
|---|
| 2818 | def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
|
|---|
| 2819 | (ins GR8 :$src1, i8mem :$src2),
|
|---|
| 2820 | "add{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2821 | [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
|
|---|
| 2822 | (load addr:$src2)))]>;
|
|---|
| 2823 | def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
|
|---|
| 2824 | (ins GR16:$src1, i16mem:$src2),
|
|---|
| 2825 | "add{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2826 | [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
|
|---|
| 2827 | (load addr:$src2)))]>, OpSize;
|
|---|
| 2828 | def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
|
|---|
| 2829 | (ins GR32:$src1, i32mem:$src2),
|
|---|
| 2830 | "add{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2831 | [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
|
|---|
| 2832 | (load addr:$src2)))]>;
|
|---|
| 2833 |
|
|---|
| 2834 | // Register-Integer Addition
|
|---|
| 2835 | def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
|---|
| 2836 | "add{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2837 | [(set GR8:$dst, EFLAGS,
|
|---|
| 2838 | (X86add_flag GR8:$src1, imm:$src2))]>;
|
|---|
| 2839 |
|
|---|
| 2840 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
|
|---|
| 2841 | // Register-Integer Addition
|
|---|
| 2842 | def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
|
|---|
| 2843 | (ins GR16:$src1, i16imm:$src2),
|
|---|
| 2844 | "add{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2845 | [(set GR16:$dst, EFLAGS,
|
|---|
| 2846 | (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
|
|---|
| 2847 | def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
|
|---|
| 2848 | (ins GR32:$src1, i32imm:$src2),
|
|---|
| 2849 | "add{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2850 | [(set GR32:$dst, EFLAGS,
|
|---|
| 2851 | (X86add_flag GR32:$src1, imm:$src2))]>;
|
|---|
| 2852 | def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
|
|---|
| 2853 | (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 2854 | "add{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2855 | [(set GR16:$dst, EFLAGS,
|
|---|
| 2856 | (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
|
|---|
| 2857 | def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
|
|---|
| 2858 | (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 2859 | "add{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2860 | [(set GR32:$dst, EFLAGS,
|
|---|
| 2861 | (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
|
|---|
| 2862 | }
|
|---|
| 2863 |
|
|---|
| 2864 | let Constraints = "" in {
|
|---|
| 2865 | // Memory-Register Addition
|
|---|
| 2866 | def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
|
|---|
| 2867 | "add{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2868 | [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
|
|---|
| 2869 | (implicit EFLAGS)]>;
|
|---|
| 2870 | def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
|---|
| 2871 | "add{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2872 | [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
|
|---|
| 2873 | (implicit EFLAGS)]>, OpSize;
|
|---|
| 2874 | def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
|---|
| 2875 | "add{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2876 | [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
|
|---|
| 2877 | (implicit EFLAGS)]>;
|
|---|
| 2878 | def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
|
|---|
| 2879 | "add{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2880 | [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
|
|---|
| 2881 | (implicit EFLAGS)]>;
|
|---|
| 2882 | def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
|
|---|
| 2883 | "add{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2884 | [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
|
|---|
| 2885 | (implicit EFLAGS)]>, OpSize;
|
|---|
| 2886 | def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
|
|---|
| 2887 | "add{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2888 | [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
|
|---|
| 2889 | (implicit EFLAGS)]>;
|
|---|
| 2890 | def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
|
|---|
| 2891 | "add{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2892 | [(store (add (load addr:$dst), i16immSExt8:$src2),
|
|---|
| 2893 | addr:$dst),
|
|---|
| 2894 | (implicit EFLAGS)]>, OpSize;
|
|---|
| 2895 | def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
|
|---|
| 2896 | "add{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2897 | [(store (add (load addr:$dst), i32immSExt8:$src2),
|
|---|
| 2898 | addr:$dst),
|
|---|
| 2899 | (implicit EFLAGS)]>;
|
|---|
| 2900 |
|
|---|
| 2901 | // addition to rAX
|
|---|
| 2902 | def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
|
|---|
| 2903 | "add{b}\t{$src, %al|%al, $src}", []>;
|
|---|
| 2904 | def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
|
|---|
| 2905 | "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
|
|---|
| 2906 | def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
|
|---|
| 2907 | "add{l}\t{$src, %eax|%eax, $src}", []>;
|
|---|
| 2908 | } // Constraints = ""
|
|---|
| 2909 |
|
|---|
| 2910 | let Uses = [EFLAGS] in {
|
|---|
| 2911 | let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
|
|---|
| 2912 | def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
|---|
| 2913 | "adc{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2914 | [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
|
|---|
| 2915 | def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
|
|---|
| 2916 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 2917 | "adc{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2918 | [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
|
|---|
| 2919 | def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
|
|---|
| 2920 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 2921 | "adc{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2922 | [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
|
|---|
| 2923 | }
|
|---|
| 2924 |
|
|---|
| 2925 | let isCodeGenOnly = 1 in {
|
|---|
| 2926 | def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
|---|
| 2927 | "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 2928 | def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
|
|---|
| 2929 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 2930 | "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
|
|---|
| 2931 | def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
|
|---|
| 2932 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 2933 | "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 2934 | }
|
|---|
| 2935 |
|
|---|
| 2936 | def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
|
|---|
| 2937 | (ins GR8:$src1, i8mem:$src2),
|
|---|
| 2938 | "adc{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2939 | [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
|
|---|
| 2940 | def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
|
|---|
| 2941 | (ins GR16:$src1, i16mem:$src2),
|
|---|
| 2942 | "adc{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2943 | [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
|
|---|
| 2944 | OpSize;
|
|---|
| 2945 | def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
|
|---|
| 2946 | (ins GR32:$src1, i32mem:$src2),
|
|---|
| 2947 | "adc{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2948 | [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
|
|---|
| 2949 | def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
|---|
| 2950 | "adc{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2951 | [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
|
|---|
| 2952 | def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
|
|---|
| 2953 | (ins GR16:$src1, i16imm:$src2),
|
|---|
| 2954 | "adc{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2955 | [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
|
|---|
| 2956 | def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
|
|---|
| 2957 | (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 2958 | "adc{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2959 | [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
|
|---|
| 2960 | OpSize;
|
|---|
| 2961 | def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
|
|---|
| 2962 | (ins GR32:$src1, i32imm:$src2),
|
|---|
| 2963 | "adc{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2964 | [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
|
|---|
| 2965 | def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
|
|---|
| 2966 | (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 2967 | "adc{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2968 | [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
|
|---|
| 2969 |
|
|---|
| 2970 | let Constraints = "" in {
|
|---|
| 2971 | def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
|
|---|
| 2972 | "adc{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2973 | [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
|
|---|
| 2974 | def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
|---|
| 2975 | "adc{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2976 | [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
|
|---|
| 2977 | OpSize;
|
|---|
| 2978 | def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
|---|
| 2979 | "adc{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2980 | [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
|
|---|
| 2981 | def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
|
|---|
| 2982 | "adc{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2983 | [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
|
|---|
| 2984 | def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
|
|---|
| 2985 | "adc{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2986 | [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
|
|---|
| 2987 | OpSize;
|
|---|
| 2988 | def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
|
|---|
| 2989 | "adc{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2990 | [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
|
|---|
| 2991 | OpSize;
|
|---|
| 2992 | def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
|
|---|
| 2993 | "adc{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2994 | [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
|
|---|
| 2995 | def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
|
|---|
| 2996 | "adc{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 2997 | [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
|
|---|
| 2998 |
|
|---|
| 2999 | def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
|
|---|
| 3000 | "adc{b}\t{$src, %al|%al, $src}", []>;
|
|---|
| 3001 | def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
|
|---|
| 3002 | "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
|
|---|
| 3003 | def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
|
|---|
| 3004 | "adc{l}\t{$src, %eax|%eax, $src}", []>;
|
|---|
| 3005 | } // Constraints = ""
|
|---|
| 3006 | } // Uses = [EFLAGS]
|
|---|
| 3007 |
|
|---|
| 3008 | // Register-Register Subtraction
|
|---|
| 3009 | def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
|---|
| 3010 | "sub{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3011 | [(set GR8:$dst, EFLAGS,
|
|---|
| 3012 | (X86sub_flag GR8:$src1, GR8:$src2))]>;
|
|---|
| 3013 | def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
|
|---|
| 3014 | "sub{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3015 | [(set GR16:$dst, EFLAGS,
|
|---|
| 3016 | (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
|
|---|
| 3017 | def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
|
|---|
| 3018 | "sub{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3019 | [(set GR32:$dst, EFLAGS,
|
|---|
| 3020 | (X86sub_flag GR32:$src1, GR32:$src2))]>;
|
|---|
| 3021 |
|
|---|
| 3022 | let isCodeGenOnly = 1 in {
|
|---|
| 3023 | def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
|---|
| 3024 | "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 3025 | def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
|
|---|
| 3026 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 3027 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
|
|---|
| 3028 | def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
|
|---|
| 3029 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 3030 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 3031 | }
|
|---|
| 3032 |
|
|---|
| 3033 | // Register-Memory Subtraction
|
|---|
| 3034 | def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
|
|---|
| 3035 | (ins GR8 :$src1, i8mem :$src2),
|
|---|
| 3036 | "sub{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3037 | [(set GR8:$dst, EFLAGS,
|
|---|
| 3038 | (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
|
|---|
| 3039 | def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
|
|---|
| 3040 | (ins GR16:$src1, i16mem:$src2),
|
|---|
| 3041 | "sub{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3042 | [(set GR16:$dst, EFLAGS,
|
|---|
| 3043 | (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
|
|---|
| 3044 | def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
|
|---|
| 3045 | (ins GR32:$src1, i32mem:$src2),
|
|---|
| 3046 | "sub{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3047 | [(set GR32:$dst, EFLAGS,
|
|---|
| 3048 | (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
|
|---|
| 3049 |
|
|---|
| 3050 | // Register-Integer Subtraction
|
|---|
| 3051 | def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
|
|---|
| 3052 | (ins GR8:$src1, i8imm:$src2),
|
|---|
| 3053 | "sub{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3054 | [(set GR8:$dst, EFLAGS,
|
|---|
| 3055 | (X86sub_flag GR8:$src1, imm:$src2))]>;
|
|---|
| 3056 | def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
|
|---|
| 3057 | (ins GR16:$src1, i16imm:$src2),
|
|---|
| 3058 | "sub{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3059 | [(set GR16:$dst, EFLAGS,
|
|---|
| 3060 | (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
|
|---|
| 3061 | def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
|
|---|
| 3062 | (ins GR32:$src1, i32imm:$src2),
|
|---|
| 3063 | "sub{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3064 | [(set GR32:$dst, EFLAGS,
|
|---|
| 3065 | (X86sub_flag GR32:$src1, imm:$src2))]>;
|
|---|
| 3066 | def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
|
|---|
| 3067 | (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 3068 | "sub{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3069 | [(set GR16:$dst, EFLAGS,
|
|---|
| 3070 | (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
|
|---|
| 3071 | def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
|
|---|
| 3072 | (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 3073 | "sub{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3074 | [(set GR32:$dst, EFLAGS,
|
|---|
| 3075 | (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
|
|---|
| 3076 |
|
|---|
| 3077 | let Constraints = "" in {
|
|---|
| 3078 | // Memory-Register Subtraction
|
|---|
| 3079 | def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
|
|---|
| 3080 | "sub{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3081 | [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
|
|---|
| 3082 | (implicit EFLAGS)]>;
|
|---|
| 3083 | def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
|---|
| 3084 | "sub{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3085 | [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
|
|---|
| 3086 | (implicit EFLAGS)]>, OpSize;
|
|---|
| 3087 | def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
|---|
| 3088 | "sub{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3089 | [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
|
|---|
| 3090 | (implicit EFLAGS)]>;
|
|---|
| 3091 |
|
|---|
| 3092 | // Memory-Integer Subtraction
|
|---|
| 3093 | def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
|
|---|
| 3094 | "sub{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3095 | [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
|
|---|
| 3096 | (implicit EFLAGS)]>;
|
|---|
| 3097 | def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
|
|---|
| 3098 | "sub{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3099 | [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
|
|---|
| 3100 | (implicit EFLAGS)]>, OpSize;
|
|---|
| 3101 | def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
|
|---|
| 3102 | "sub{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3103 | [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
|
|---|
| 3104 | (implicit EFLAGS)]>;
|
|---|
| 3105 | def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
|
|---|
| 3106 | "sub{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3107 | [(store (sub (load addr:$dst), i16immSExt8:$src2),
|
|---|
| 3108 | addr:$dst),
|
|---|
| 3109 | (implicit EFLAGS)]>, OpSize;
|
|---|
| 3110 | def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
|
|---|
| 3111 | "sub{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3112 | [(store (sub (load addr:$dst), i32immSExt8:$src2),
|
|---|
| 3113 | addr:$dst),
|
|---|
| 3114 | (implicit EFLAGS)]>;
|
|---|
| 3115 |
|
|---|
| 3116 | def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
|
|---|
| 3117 | "sub{b}\t{$src, %al|%al, $src}", []>;
|
|---|
| 3118 | def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
|
|---|
| 3119 | "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
|
|---|
| 3120 | def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
|
|---|
| 3121 | "sub{l}\t{$src, %eax|%eax, $src}", []>;
|
|---|
| 3122 | } // Constraints = ""
|
|---|
| 3123 |
|
|---|
| 3124 | let Uses = [EFLAGS] in {
|
|---|
| 3125 | def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
|
|---|
| 3126 | (ins GR8:$src1, GR8:$src2),
|
|---|
| 3127 | "sbb{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3128 | [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
|
|---|
| 3129 | def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
|
|---|
| 3130 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 3131 | "sbb{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3132 | [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
|
|---|
| 3133 | def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
|
|---|
| 3134 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 3135 | "sbb{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3136 | [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
|
|---|
| 3137 |
|
|---|
| 3138 | let Constraints = "" in {
|
|---|
| 3139 | def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
|
|---|
| 3140 | "sbb{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3141 | [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
|
|---|
| 3142 | def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
|---|
| 3143 | "sbb{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3144 | [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
|
|---|
| 3145 | OpSize;
|
|---|
| 3146 | def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
|---|
| 3147 | "sbb{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3148 | [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
|
|---|
| 3149 | def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
|
|---|
| 3150 | "sbb{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3151 | [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
|
|---|
| 3152 | def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
|
|---|
| 3153 | "sbb{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3154 | [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
|
|---|
| 3155 | OpSize;
|
|---|
| 3156 | def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
|
|---|
| 3157 | "sbb{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3158 | [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
|
|---|
| 3159 | OpSize;
|
|---|
| 3160 | def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
|
|---|
| 3161 | "sbb{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3162 | [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
|
|---|
| 3163 | def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
|
|---|
| 3164 | "sbb{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3165 | [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
|
|---|
| 3166 |
|
|---|
| 3167 | def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
|
|---|
| 3168 | "sbb{b}\t{$src, %al|%al, $src}", []>;
|
|---|
| 3169 | def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
|
|---|
| 3170 | "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
|
|---|
| 3171 | def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
|
|---|
| 3172 | "sbb{l}\t{$src, %eax|%eax, $src}", []>;
|
|---|
| 3173 | } // Constraints = ""
|
|---|
| 3174 |
|
|---|
| 3175 | let isCodeGenOnly = 1 in {
|
|---|
| 3176 | def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
|
|---|
| 3177 | "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 3178 | def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
|
|---|
| 3179 | (ins GR16:$src1, GR16:$src2),
|
|---|
| 3180 | "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
|
|---|
| 3181 | def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
|
|---|
| 3182 | (ins GR32:$src1, GR32:$src2),
|
|---|
| 3183 | "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
|
|---|
| 3184 | }
|
|---|
| 3185 |
|
|---|
| 3186 | def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
|
|---|
| 3187 | "sbb{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3188 | [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
|
|---|
| 3189 | def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
|
|---|
| 3190 | (ins GR16:$src1, i16mem:$src2),
|
|---|
| 3191 | "sbb{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3192 | [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
|
|---|
| 3193 | OpSize;
|
|---|
| 3194 | def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
|
|---|
| 3195 | (ins GR32:$src1, i32mem:$src2),
|
|---|
| 3196 | "sbb{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3197 | [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
|
|---|
| 3198 | def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
|---|
| 3199 | "sbb{b}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3200 | [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
|
|---|
| 3201 | def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
|
|---|
| 3202 | (ins GR16:$src1, i16imm:$src2),
|
|---|
| 3203 | "sbb{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3204 | [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
|
|---|
| 3205 | def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
|
|---|
| 3206 | (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 3207 | "sbb{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3208 | [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
|
|---|
| 3209 | OpSize;
|
|---|
| 3210 | def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
|
|---|
| 3211 | (ins GR32:$src1, i32imm:$src2),
|
|---|
| 3212 | "sbb{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3213 | [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
|
|---|
| 3214 | def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
|
|---|
| 3215 | (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 3216 | "sbb{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3217 | [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
|
|---|
| 3218 | } // Uses = [EFLAGS]
|
|---|
| 3219 | } // Defs = [EFLAGS]
|
|---|
| 3220 |
|
|---|
| 3221 | let Defs = [EFLAGS] in {
|
|---|
| 3222 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
|
|---|
| 3223 | // Register-Register Signed Integer Multiply
|
|---|
| 3224 | def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
|
|---|
| 3225 | "imul{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3226 | [(set GR16:$dst, EFLAGS,
|
|---|
| 3227 | (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
|
|---|
| 3228 | def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
|
|---|
| 3229 | "imul{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3230 | [(set GR32:$dst, EFLAGS,
|
|---|
| 3231 | (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
|
|---|
| 3232 | }
|
|---|
| 3233 |
|
|---|
| 3234 | // Register-Memory Signed Integer Multiply
|
|---|
| 3235 | def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
|
|---|
| 3236 | (ins GR16:$src1, i16mem:$src2),
|
|---|
| 3237 | "imul{w}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3238 | [(set GR16:$dst, EFLAGS,
|
|---|
| 3239 | (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
|
|---|
| 3240 | TB, OpSize;
|
|---|
| 3241 | def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
|
|---|
| 3242 | (ins GR32:$src1, i32mem:$src2),
|
|---|
| 3243 | "imul{l}\t{$src2, $dst|$dst, $src2}",
|
|---|
| 3244 | [(set GR32:$dst, EFLAGS,
|
|---|
| 3245 | (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
|
|---|
| 3246 | } // Defs = [EFLAGS]
|
|---|
| 3247 | } // end Two Address instructions
|
|---|
| 3248 |
|
|---|
| 3249 | // Suprisingly enough, these are not two address instructions!
|
|---|
| 3250 | let Defs = [EFLAGS] in {
|
|---|
| 3251 | // Register-Integer Signed Integer Multiply
|
|---|
| 3252 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
|
|---|
| 3253 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
|
|---|
| 3254 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|---|
| 3255 | [(set GR16:$dst, EFLAGS,
|
|---|
| 3256 | (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
|
|---|
| 3257 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
|
|---|
| 3258 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
|
|---|
| 3259 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|---|
| 3260 | [(set GR32:$dst, EFLAGS,
|
|---|
| 3261 | (X86smul_flag GR32:$src1, imm:$src2))]>;
|
|---|
| 3262 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
|
|---|
| 3263 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 3264 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|---|
| 3265 | [(set GR16:$dst, EFLAGS,
|
|---|
| 3266 | (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
|
|---|
| 3267 | OpSize;
|
|---|
| 3268 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
|
|---|
| 3269 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 3270 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|---|
| 3271 | [(set GR32:$dst, EFLAGS,
|
|---|
| 3272 | (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
|
|---|
| 3273 |
|
|---|
| 3274 | // Memory-Integer Signed Integer Multiply
|
|---|
| 3275 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
|
|---|
| 3276 | (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
|
|---|
| 3277 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|---|
| 3278 | [(set GR16:$dst, EFLAGS,
|
|---|
| 3279 | (X86smul_flag (load addr:$src1), imm:$src2))]>,
|
|---|
| 3280 | OpSize;
|
|---|
| 3281 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
|
|---|
| 3282 | (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
|
|---|
| 3283 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|---|
| 3284 | [(set GR32:$dst, EFLAGS,
|
|---|
| 3285 | (X86smul_flag (load addr:$src1), imm:$src2))]>;
|
|---|
| 3286 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
|
|---|
| 3287 | (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
|
|---|
| 3288 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|---|
| 3289 | [(set GR16:$dst, EFLAGS,
|
|---|
| 3290 | (X86smul_flag (load addr:$src1),
|
|---|
| 3291 | i16immSExt8:$src2))]>, OpSize;
|
|---|
| 3292 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
|
|---|
| 3293 | (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
|
|---|
| 3294 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|---|
| 3295 | [(set GR32:$dst, EFLAGS,
|
|---|
| 3296 | (X86smul_flag (load addr:$src1),
|
|---|
| 3297 | i32immSExt8:$src2))]>;
|
|---|
| 3298 | } // Defs = [EFLAGS]
|
|---|
| 3299 |
|
|---|
| 3300 | //===----------------------------------------------------------------------===//
|
|---|
| 3301 | // Test instructions are just like AND, except they don't generate a result.
|
|---|
| 3302 | //
|
|---|
| 3303 | let Defs = [EFLAGS] in {
|
|---|
| 3304 | let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
|
|---|
| 3305 | def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
|
|---|
| 3306 | "test{b}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3307 | [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
|
|---|
| 3308 | def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
|
|---|
| 3309 | "test{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3310 | [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
|
|---|
| 3311 | 0))]>,
|
|---|
| 3312 | OpSize;
|
|---|
| 3313 | def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
|
|---|
| 3314 | "test{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3315 | [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
|
|---|
| 3316 | 0))]>;
|
|---|
| 3317 | }
|
|---|
| 3318 |
|
|---|
| 3319 | def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
|
|---|
| 3320 | "test{b}\t{$src, %al|%al, $src}", []>;
|
|---|
| 3321 | def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
|
|---|
| 3322 | "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
|
|---|
| 3323 | def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
|
|---|
| 3324 | "test{l}\t{$src, %eax|%eax, $src}", []>;
|
|---|
| 3325 |
|
|---|
| 3326 | def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
|
|---|
| 3327 | "test{b}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3328 | [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
|
|---|
| 3329 | 0))]>;
|
|---|
| 3330 | def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 3331 | "test{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3332 | [(set EFLAGS, (X86cmp (and GR16:$src1,
|
|---|
| 3333 | (loadi16 addr:$src2)), 0))]>, OpSize;
|
|---|
| 3334 | def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 3335 | "test{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3336 | [(set EFLAGS, (X86cmp (and GR32:$src1,
|
|---|
| 3337 | (loadi32 addr:$src2)), 0))]>;
|
|---|
| 3338 |
|
|---|
| 3339 | def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
|
|---|
| 3340 | (outs), (ins GR8:$src1, i8imm:$src2),
|
|---|
| 3341 | "test{b}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3342 | [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
|
|---|
| 3343 | def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
|
|---|
| 3344 | (outs), (ins GR16:$src1, i16imm:$src2),
|
|---|
| 3345 | "test{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3346 | [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
|
|---|
| 3347 | OpSize;
|
|---|
| 3348 | def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
|
|---|
| 3349 | (outs), (ins GR32:$src1, i32imm:$src2),
|
|---|
| 3350 | "test{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3351 | [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
|
|---|
| 3352 |
|
|---|
| 3353 | def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
|
|---|
| 3354 | (outs), (ins i8mem:$src1, i8imm:$src2),
|
|---|
| 3355 | "test{b}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3356 | [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
|
|---|
| 3357 | 0))]>;
|
|---|
| 3358 | def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
|
|---|
| 3359 | (outs), (ins i16mem:$src1, i16imm:$src2),
|
|---|
| 3360 | "test{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3361 | [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
|
|---|
| 3362 | 0))]>, OpSize;
|
|---|
| 3363 | def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
|
|---|
| 3364 | (outs), (ins i32mem:$src1, i32imm:$src2),
|
|---|
| 3365 | "test{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3366 | [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
|
|---|
| 3367 | 0))]>;
|
|---|
| 3368 | } // Defs = [EFLAGS]
|
|---|
| 3369 |
|
|---|
| 3370 |
|
|---|
| 3371 | // Condition code ops, incl. set if equal/not equal/...
|
|---|
| 3372 | let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
|
|---|
| 3373 | def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
|
|---|
| 3374 | let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
|
|---|
| 3375 | def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
|
|---|
| 3376 |
|
|---|
| 3377 | let Uses = [EFLAGS] in {
|
|---|
| 3378 | // Use sbb to materialize carry bit.
|
|---|
| 3379 | let Defs = [EFLAGS], isCodeGenOnly = 1 in {
|
|---|
| 3380 | // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
|
|---|
| 3381 | // However, Pat<> can't replicate the destination reg into the inputs of the
|
|---|
| 3382 | // result.
|
|---|
| 3383 | // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
|
|---|
| 3384 | // X86CodeEmitter.
|
|---|
| 3385 | def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
|
|---|
| 3386 | [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
|
|---|
| 3387 | def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
|
|---|
| 3388 | [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
|
|---|
| 3389 | OpSize;
|
|---|
| 3390 | def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
|
|---|
| 3391 | [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
|
|---|
| 3392 | } // isCodeGenOnly
|
|---|
| 3393 |
|
|---|
| 3394 | def SETEr : I<0x94, MRM0r,
|
|---|
| 3395 | (outs GR8 :$dst), (ins),
|
|---|
| 3396 | "sete\t$dst",
|
|---|
| 3397 | [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
|
|---|
| 3398 | TB; // GR8 = ==
|
|---|
| 3399 | def SETEm : I<0x94, MRM0m,
|
|---|
| 3400 | (outs), (ins i8mem:$dst),
|
|---|
| 3401 | "sete\t$dst",
|
|---|
| 3402 | [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
|
|---|
| 3403 | TB; // [mem8] = ==
|
|---|
| 3404 |
|
|---|
| 3405 | def SETNEr : I<0x95, MRM0r,
|
|---|
| 3406 | (outs GR8 :$dst), (ins),
|
|---|
| 3407 | "setne\t$dst",
|
|---|
| 3408 | [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
|
|---|
| 3409 | TB; // GR8 = !=
|
|---|
| 3410 | def SETNEm : I<0x95, MRM0m,
|
|---|
| 3411 | (outs), (ins i8mem:$dst),
|
|---|
| 3412 | "setne\t$dst",
|
|---|
| 3413 | [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
|
|---|
| 3414 | TB; // [mem8] = !=
|
|---|
| 3415 |
|
|---|
| 3416 | def SETLr : I<0x9C, MRM0r,
|
|---|
| 3417 | (outs GR8 :$dst), (ins),
|
|---|
| 3418 | "setl\t$dst",
|
|---|
| 3419 | [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
|
|---|
| 3420 | TB; // GR8 = < signed
|
|---|
| 3421 | def SETLm : I<0x9C, MRM0m,
|
|---|
| 3422 | (outs), (ins i8mem:$dst),
|
|---|
| 3423 | "setl\t$dst",
|
|---|
| 3424 | [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
|
|---|
| 3425 | TB; // [mem8] = < signed
|
|---|
| 3426 |
|
|---|
| 3427 | def SETGEr : I<0x9D, MRM0r,
|
|---|
| 3428 | (outs GR8 :$dst), (ins),
|
|---|
| 3429 | "setge\t$dst",
|
|---|
| 3430 | [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
|
|---|
| 3431 | TB; // GR8 = >= signed
|
|---|
| 3432 | def SETGEm : I<0x9D, MRM0m,
|
|---|
| 3433 | (outs), (ins i8mem:$dst),
|
|---|
| 3434 | "setge\t$dst",
|
|---|
| 3435 | [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
|
|---|
| 3436 | TB; // [mem8] = >= signed
|
|---|
| 3437 |
|
|---|
| 3438 | def SETLEr : I<0x9E, MRM0r,
|
|---|
| 3439 | (outs GR8 :$dst), (ins),
|
|---|
| 3440 | "setle\t$dst",
|
|---|
| 3441 | [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
|
|---|
| 3442 | TB; // GR8 = <= signed
|
|---|
| 3443 | def SETLEm : I<0x9E, MRM0m,
|
|---|
| 3444 | (outs), (ins i8mem:$dst),
|
|---|
| 3445 | "setle\t$dst",
|
|---|
| 3446 | [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
|
|---|
| 3447 | TB; // [mem8] = <= signed
|
|---|
| 3448 |
|
|---|
| 3449 | def SETGr : I<0x9F, MRM0r,
|
|---|
| 3450 | (outs GR8 :$dst), (ins),
|
|---|
| 3451 | "setg\t$dst",
|
|---|
| 3452 | [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
|
|---|
| 3453 | TB; // GR8 = > signed
|
|---|
| 3454 | def SETGm : I<0x9F, MRM0m,
|
|---|
| 3455 | (outs), (ins i8mem:$dst),
|
|---|
| 3456 | "setg\t$dst",
|
|---|
| 3457 | [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
|
|---|
| 3458 | TB; // [mem8] = > signed
|
|---|
| 3459 |
|
|---|
| 3460 | def SETBr : I<0x92, MRM0r,
|
|---|
| 3461 | (outs GR8 :$dst), (ins),
|
|---|
| 3462 | "setb\t$dst",
|
|---|
| 3463 | [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
|
|---|
| 3464 | TB; // GR8 = < unsign
|
|---|
| 3465 | def SETBm : I<0x92, MRM0m,
|
|---|
| 3466 | (outs), (ins i8mem:$dst),
|
|---|
| 3467 | "setb\t$dst",
|
|---|
| 3468 | [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
|
|---|
| 3469 | TB; // [mem8] = < unsign
|
|---|
| 3470 |
|
|---|
| 3471 | def SETAEr : I<0x93, MRM0r,
|
|---|
| 3472 | (outs GR8 :$dst), (ins),
|
|---|
| 3473 | "setae\t$dst",
|
|---|
| 3474 | [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
|
|---|
| 3475 | TB; // GR8 = >= unsign
|
|---|
| 3476 | def SETAEm : I<0x93, MRM0m,
|
|---|
| 3477 | (outs), (ins i8mem:$dst),
|
|---|
| 3478 | "setae\t$dst",
|
|---|
| 3479 | [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
|
|---|
| 3480 | TB; // [mem8] = >= unsign
|
|---|
| 3481 |
|
|---|
| 3482 | def SETBEr : I<0x96, MRM0r,
|
|---|
| 3483 | (outs GR8 :$dst), (ins),
|
|---|
| 3484 | "setbe\t$dst",
|
|---|
| 3485 | [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
|
|---|
| 3486 | TB; // GR8 = <= unsign
|
|---|
| 3487 | def SETBEm : I<0x96, MRM0m,
|
|---|
| 3488 | (outs), (ins i8mem:$dst),
|
|---|
| 3489 | "setbe\t$dst",
|
|---|
| 3490 | [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
|
|---|
| 3491 | TB; // [mem8] = <= unsign
|
|---|
| 3492 |
|
|---|
| 3493 | def SETAr : I<0x97, MRM0r,
|
|---|
| 3494 | (outs GR8 :$dst), (ins),
|
|---|
| 3495 | "seta\t$dst",
|
|---|
| 3496 | [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
|
|---|
| 3497 | TB; // GR8 = > signed
|
|---|
| 3498 | def SETAm : I<0x97, MRM0m,
|
|---|
| 3499 | (outs), (ins i8mem:$dst),
|
|---|
| 3500 | "seta\t$dst",
|
|---|
| 3501 | [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
|
|---|
| 3502 | TB; // [mem8] = > signed
|
|---|
| 3503 |
|
|---|
| 3504 | def SETSr : I<0x98, MRM0r,
|
|---|
| 3505 | (outs GR8 :$dst), (ins),
|
|---|
| 3506 | "sets\t$dst",
|
|---|
| 3507 | [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
|
|---|
| 3508 | TB; // GR8 = <sign bit>
|
|---|
| 3509 | def SETSm : I<0x98, MRM0m,
|
|---|
| 3510 | (outs), (ins i8mem:$dst),
|
|---|
| 3511 | "sets\t$dst",
|
|---|
| 3512 | [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
|
|---|
| 3513 | TB; // [mem8] = <sign bit>
|
|---|
| 3514 | def SETNSr : I<0x99, MRM0r,
|
|---|
| 3515 | (outs GR8 :$dst), (ins),
|
|---|
| 3516 | "setns\t$dst",
|
|---|
| 3517 | [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
|
|---|
| 3518 | TB; // GR8 = !<sign bit>
|
|---|
| 3519 | def SETNSm : I<0x99, MRM0m,
|
|---|
| 3520 | (outs), (ins i8mem:$dst),
|
|---|
| 3521 | "setns\t$dst",
|
|---|
| 3522 | [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
|
|---|
| 3523 | TB; // [mem8] = !<sign bit>
|
|---|
| 3524 |
|
|---|
| 3525 | def SETPr : I<0x9A, MRM0r,
|
|---|
| 3526 | (outs GR8 :$dst), (ins),
|
|---|
| 3527 | "setp\t$dst",
|
|---|
| 3528 | [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
|
|---|
| 3529 | TB; // GR8 = parity
|
|---|
| 3530 | def SETPm : I<0x9A, MRM0m,
|
|---|
| 3531 | (outs), (ins i8mem:$dst),
|
|---|
| 3532 | "setp\t$dst",
|
|---|
| 3533 | [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
|
|---|
| 3534 | TB; // [mem8] = parity
|
|---|
| 3535 | def SETNPr : I<0x9B, MRM0r,
|
|---|
| 3536 | (outs GR8 :$dst), (ins),
|
|---|
| 3537 | "setnp\t$dst",
|
|---|
| 3538 | [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
|
|---|
| 3539 | TB; // GR8 = not parity
|
|---|
| 3540 | def SETNPm : I<0x9B, MRM0m,
|
|---|
| 3541 | (outs), (ins i8mem:$dst),
|
|---|
| 3542 | "setnp\t$dst",
|
|---|
| 3543 | [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
|
|---|
| 3544 | TB; // [mem8] = not parity
|
|---|
| 3545 |
|
|---|
| 3546 | def SETOr : I<0x90, MRM0r,
|
|---|
| 3547 | (outs GR8 :$dst), (ins),
|
|---|
| 3548 | "seto\t$dst",
|
|---|
| 3549 | [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
|
|---|
| 3550 | TB; // GR8 = overflow
|
|---|
| 3551 | def SETOm : I<0x90, MRM0m,
|
|---|
| 3552 | (outs), (ins i8mem:$dst),
|
|---|
| 3553 | "seto\t$dst",
|
|---|
| 3554 | [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
|
|---|
| 3555 | TB; // [mem8] = overflow
|
|---|
| 3556 | def SETNOr : I<0x91, MRM0r,
|
|---|
| 3557 | (outs GR8 :$dst), (ins),
|
|---|
| 3558 | "setno\t$dst",
|
|---|
| 3559 | [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
|
|---|
| 3560 | TB; // GR8 = not overflow
|
|---|
| 3561 | def SETNOm : I<0x91, MRM0m,
|
|---|
| 3562 | (outs), (ins i8mem:$dst),
|
|---|
| 3563 | "setno\t$dst",
|
|---|
| 3564 | [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
|
|---|
| 3565 | TB; // [mem8] = not overflow
|
|---|
| 3566 | } // Uses = [EFLAGS]
|
|---|
| 3567 |
|
|---|
| 3568 |
|
|---|
| 3569 | // Integer comparisons
|
|---|
| 3570 | let Defs = [EFLAGS] in {
|
|---|
| 3571 | def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
|
|---|
| 3572 | "cmp{b}\t{$src, %al|%al, $src}", []>;
|
|---|
| 3573 | def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
|
|---|
| 3574 | "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
|
|---|
| 3575 | def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
|
|---|
| 3576 | "cmp{l}\t{$src, %eax|%eax, $src}", []>;
|
|---|
| 3577 |
|
|---|
| 3578 | def CMP8rr : I<0x38, MRMDestReg,
|
|---|
| 3579 | (outs), (ins GR8 :$src1, GR8 :$src2),
|
|---|
| 3580 | "cmp{b}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3581 | [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
|
|---|
| 3582 | def CMP16rr : I<0x39, MRMDestReg,
|
|---|
| 3583 | (outs), (ins GR16:$src1, GR16:$src2),
|
|---|
| 3584 | "cmp{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3585 | [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
|
|---|
| 3586 | def CMP32rr : I<0x39, MRMDestReg,
|
|---|
| 3587 | (outs), (ins GR32:$src1, GR32:$src2),
|
|---|
| 3588 | "cmp{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3589 | [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
|
|---|
| 3590 | def CMP8mr : I<0x38, MRMDestMem,
|
|---|
| 3591 | (outs), (ins i8mem :$src1, GR8 :$src2),
|
|---|
| 3592 | "cmp{b}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3593 | [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
|
|---|
| 3594 | def CMP16mr : I<0x39, MRMDestMem,
|
|---|
| 3595 | (outs), (ins i16mem:$src1, GR16:$src2),
|
|---|
| 3596 | "cmp{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3597 | [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
|
|---|
| 3598 | OpSize;
|
|---|
| 3599 | def CMP32mr : I<0x39, MRMDestMem,
|
|---|
| 3600 | (outs), (ins i32mem:$src1, GR32:$src2),
|
|---|
| 3601 | "cmp{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3602 | [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
|
|---|
| 3603 | def CMP8rm : I<0x3A, MRMSrcMem,
|
|---|
| 3604 | (outs), (ins GR8 :$src1, i8mem :$src2),
|
|---|
| 3605 | "cmp{b}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3606 | [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
|
|---|
| 3607 | def CMP16rm : I<0x3B, MRMSrcMem,
|
|---|
| 3608 | (outs), (ins GR16:$src1, i16mem:$src2),
|
|---|
| 3609 | "cmp{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3610 | [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
|
|---|
| 3611 | OpSize;
|
|---|
| 3612 | def CMP32rm : I<0x3B, MRMSrcMem,
|
|---|
| 3613 | (outs), (ins GR32:$src1, i32mem:$src2),
|
|---|
| 3614 | "cmp{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3615 | [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
|
|---|
| 3616 |
|
|---|
| 3617 | // These are alternate spellings for use by the disassembler, we mark them as
|
|---|
| 3618 | // code gen only to ensure they aren't matched by the assembler.
|
|---|
| 3619 | let isCodeGenOnly = 1 in {
|
|---|
| 3620 | def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
|
|---|
| 3621 | "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
|
|---|
| 3622 | def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
|
|---|
| 3623 | "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
|
|---|
| 3624 | def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
|
|---|
| 3625 | "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
|
|---|
| 3626 | }
|
|---|
| 3627 |
|
|---|
| 3628 | def CMP8ri : Ii8<0x80, MRM7r,
|
|---|
| 3629 | (outs), (ins GR8:$src1, i8imm:$src2),
|
|---|
| 3630 | "cmp{b}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3631 | [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
|
|---|
| 3632 | def CMP16ri : Ii16<0x81, MRM7r,
|
|---|
| 3633 | (outs), (ins GR16:$src1, i16imm:$src2),
|
|---|
| 3634 | "cmp{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3635 | [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
|
|---|
| 3636 | def CMP32ri : Ii32<0x81, MRM7r,
|
|---|
| 3637 | (outs), (ins GR32:$src1, i32imm:$src2),
|
|---|
| 3638 | "cmp{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3639 | [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
|
|---|
| 3640 | def CMP8mi : Ii8 <0x80, MRM7m,
|
|---|
| 3641 | (outs), (ins i8mem :$src1, i8imm :$src2),
|
|---|
| 3642 | "cmp{b}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3643 | [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
|
|---|
| 3644 | def CMP16mi : Ii16<0x81, MRM7m,
|
|---|
| 3645 | (outs), (ins i16mem:$src1, i16imm:$src2),
|
|---|
| 3646 | "cmp{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3647 | [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
|
|---|
| 3648 | OpSize;
|
|---|
| 3649 | def CMP32mi : Ii32<0x81, MRM7m,
|
|---|
| 3650 | (outs), (ins i32mem:$src1, i32imm:$src2),
|
|---|
| 3651 | "cmp{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3652 | [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
|
|---|
| 3653 | def CMP16ri8 : Ii8<0x83, MRM7r,
|
|---|
| 3654 | (outs), (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 3655 | "cmp{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3656 | [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
|
|---|
| 3657 | OpSize;
|
|---|
| 3658 | def CMP16mi8 : Ii8<0x83, MRM7m,
|
|---|
| 3659 | (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
|---|
| 3660 | "cmp{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3661 | [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
|
|---|
| 3662 | i16immSExt8:$src2))]>, OpSize;
|
|---|
| 3663 | def CMP32mi8 : Ii8<0x83, MRM7m,
|
|---|
| 3664 | (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
|---|
| 3665 | "cmp{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3666 | [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
|
|---|
| 3667 | i32immSExt8:$src2))]>;
|
|---|
| 3668 | def CMP32ri8 : Ii8<0x83, MRM7r,
|
|---|
| 3669 | (outs), (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 3670 | "cmp{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3671 | [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
|
|---|
| 3672 | } // Defs = [EFLAGS]
|
|---|
| 3673 |
|
|---|
| 3674 | // Bit tests.
|
|---|
| 3675 | // TODO: BTC, BTR, and BTS
|
|---|
| 3676 | let Defs = [EFLAGS] in {
|
|---|
| 3677 | def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
|---|
| 3678 | "bt{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3679 | [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
|
|---|
| 3680 | def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
|---|
| 3681 | "bt{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3682 | [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
|
|---|
| 3683 |
|
|---|
| 3684 | // Unlike with the register+register form, the memory+register form of the
|
|---|
| 3685 | // bt instruction does not ignore the high bits of the index. From ISel's
|
|---|
| 3686 | // perspective, this is pretty bizarre. Make these instructions disassembly
|
|---|
| 3687 | // only for now.
|
|---|
| 3688 |
|
|---|
| 3689 | def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
|---|
| 3690 | "bt{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3691 | // [(X86bt (loadi16 addr:$src1), GR16:$src2),
|
|---|
| 3692 | // (implicit EFLAGS)]
|
|---|
| 3693 | []
|
|---|
| 3694 | >, OpSize, TB, Requires<[FastBTMem]>;
|
|---|
| 3695 | def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
|---|
| 3696 | "bt{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3697 | // [(X86bt (loadi32 addr:$src1), GR32:$src2),
|
|---|
| 3698 | // (implicit EFLAGS)]
|
|---|
| 3699 | []
|
|---|
| 3700 | >, TB, Requires<[FastBTMem]>;
|
|---|
| 3701 |
|
|---|
| 3702 | def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 3703 | "bt{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3704 | [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
|
|---|
| 3705 | OpSize, TB;
|
|---|
| 3706 | def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 3707 | "bt{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3708 | [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
|
|---|
| 3709 | // Note that these instructions don't need FastBTMem because that
|
|---|
| 3710 | // only applies when the other operand is in a register. When it's
|
|---|
| 3711 | // an immediate, bt is still fast.
|
|---|
| 3712 | def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
|---|
| 3713 | "bt{w}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3714 | [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
|
|---|
| 3715 | ]>, OpSize, TB;
|
|---|
| 3716 | def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
|---|
| 3717 | "bt{l}\t{$src2, $src1|$src1, $src2}",
|
|---|
| 3718 | [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
|
|---|
| 3719 | ]>, TB;
|
|---|
| 3720 |
|
|---|
| 3721 | def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
|---|
| 3722 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3723 | def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
|---|
| 3724 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3725 | def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
|---|
| 3726 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3727 | def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
|---|
| 3728 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3729 | def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 3730 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3731 | def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 3732 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3733 | def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
|---|
| 3734 | "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3735 | def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
|---|
| 3736 | "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3737 |
|
|---|
| 3738 | def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
|---|
| 3739 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3740 | def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
|---|
| 3741 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3742 | def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
|---|
| 3743 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3744 | def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
|---|
| 3745 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3746 | def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 3747 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3748 | def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 3749 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3750 | def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
|---|
| 3751 | "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3752 | def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
|---|
| 3753 | "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3754 |
|
|---|
| 3755 | def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
|---|
| 3756 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3757 | def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
|---|
| 3758 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3759 | def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
|---|
| 3760 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3761 | def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
|---|
| 3762 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3763 | def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
|---|
| 3764 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3765 | def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
|---|
| 3766 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3767 | def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
|---|
| 3768 | "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
|
|---|
| 3769 | def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
|---|
| 3770 | "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
|---|
| 3771 | } // Defs = [EFLAGS]
|
|---|
| 3772 |
|
|---|
| 3773 | // Sign/Zero extenders
|
|---|
| 3774 | // Use movsbl intead of movsbw; we don't care about the high 16 bits
|
|---|
| 3775 | // of the register here. This has a smaller encoding and avoids a
|
|---|
| 3776 | // partial-register update. Actual movsbw included for the disassembler.
|
|---|
| 3777 | def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
|
|---|
| 3778 | "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 3779 | def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
|
|---|
| 3780 | "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 3781 | def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
|
|---|
| 3782 | "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
|
|---|
| 3783 | def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
|
|---|
| 3784 | "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
|
|---|
| 3785 | def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
|
|---|
| 3786 | "movs{bl|x}\t{$src, $dst|$dst, $src}",
|
|---|
| 3787 | [(set GR32:$dst, (sext GR8:$src))]>, TB;
|
|---|
| 3788 | def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
|
|---|
| 3789 | "movs{bl|x}\t{$src, $dst|$dst, $src}",
|
|---|
| 3790 | [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
|
|---|
| 3791 | def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
|
|---|
| 3792 | "movs{wl|x}\t{$src, $dst|$dst, $src}",
|
|---|
| 3793 | [(set GR32:$dst, (sext GR16:$src))]>, TB;
|
|---|
| 3794 | def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
|
|---|
| 3795 | "movs{wl|x}\t{$src, $dst|$dst, $src}",
|
|---|
| 3796 | [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
|
|---|
| 3797 |
|
|---|
| 3798 | // Use movzbl intead of movzbw; we don't care about the high 16 bits
|
|---|
| 3799 | // of the register here. This has a smaller encoding and avoids a
|
|---|
| 3800 | // partial-register update. Actual movzbw included for the disassembler.
|
|---|
| 3801 | def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
|
|---|
| 3802 | "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 3803 | def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
|
|---|
| 3804 | "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 3805 | def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
|
|---|
| 3806 | "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
|
|---|
| 3807 | def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
|
|---|
| 3808 | "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
|
|---|
| 3809 | def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
|
|---|
| 3810 | "movz{bl|x}\t{$src, $dst|$dst, $src}",
|
|---|
| 3811 | [(set GR32:$dst, (zext GR8:$src))]>, TB;
|
|---|
| 3812 | def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
|
|---|
| 3813 | "movz{bl|x}\t{$src, $dst|$dst, $src}",
|
|---|
| 3814 | [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
|
|---|
| 3815 | def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
|
|---|
| 3816 | "movz{wl|x}\t{$src, $dst|$dst, $src}",
|
|---|
| 3817 | [(set GR32:$dst, (zext GR16:$src))]>, TB;
|
|---|
| 3818 | def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
|
|---|
| 3819 | "movz{wl|x}\t{$src, $dst|$dst, $src}",
|
|---|
| 3820 | [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
|
|---|
| 3821 |
|
|---|
| 3822 | // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
|
|---|
| 3823 | // except that they use GR32_NOREX for the output operand register class
|
|---|
| 3824 | // instead of GR32. This allows them to operate on h registers on x86-64.
|
|---|
| 3825 | def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
|
|---|
| 3826 | (outs GR32_NOREX:$dst), (ins GR8:$src),
|
|---|
| 3827 | "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
|
|---|
| 3828 | []>, TB;
|
|---|
| 3829 | let mayLoad = 1 in
|
|---|
| 3830 | def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
|
|---|
| 3831 | (outs GR32_NOREX:$dst), (ins i8mem:$src),
|
|---|
| 3832 | "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
|
|---|
| 3833 | []>, TB;
|
|---|
| 3834 |
|
|---|
| 3835 | let neverHasSideEffects = 1 in {
|
|---|
| 3836 | let Defs = [AX], Uses = [AL] in
|
|---|
| 3837 | def CBW : I<0x98, RawFrm, (outs), (ins),
|
|---|
| 3838 | "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
|
|---|
| 3839 | let Defs = [EAX], Uses = [AX] in
|
|---|
| 3840 | def CWDE : I<0x98, RawFrm, (outs), (ins),
|
|---|
| 3841 | "{cwtl|cwde}", []>; // EAX = signext(AX)
|
|---|
| 3842 |
|
|---|
| 3843 | let Defs = [AX,DX], Uses = [AX] in
|
|---|
| 3844 | def CWD : I<0x99, RawFrm, (outs), (ins),
|
|---|
| 3845 | "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
|
|---|
| 3846 | let Defs = [EAX,EDX], Uses = [EAX] in
|
|---|
| 3847 | def CDQ : I<0x99, RawFrm, (outs), (ins),
|
|---|
| 3848 | "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
|
|---|
| 3849 | }
|
|---|
| 3850 |
|
|---|
| 3851 | //===----------------------------------------------------------------------===//
|
|---|
| 3852 | // Alias Instructions
|
|---|
| 3853 | //===----------------------------------------------------------------------===//
|
|---|
| 3854 |
|
|---|
| 3855 | // Alias instructions that map movr0 to xor.
|
|---|
| 3856 | // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
|
|---|
| 3857 | // FIXME: Set encoding to pseudo.
|
|---|
| 3858 | let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
|
|---|
| 3859 | isCodeGenOnly = 1 in {
|
|---|
| 3860 | def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
|
|---|
| 3861 | [(set GR8:$dst, 0)]>;
|
|---|
| 3862 |
|
|---|
| 3863 | // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
|
|---|
| 3864 | // encoding and avoids a partial-register update sometimes, but doing so
|
|---|
| 3865 | // at isel time interferes with rematerialization in the current register
|
|---|
| 3866 | // allocator. For now, this is rewritten when the instruction is lowered
|
|---|
| 3867 | // to an MCInst.
|
|---|
| 3868 | def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
|
|---|
| 3869 | "",
|
|---|
| 3870 | [(set GR16:$dst, 0)]>, OpSize;
|
|---|
| 3871 |
|
|---|
| 3872 | // FIXME: Set encoding to pseudo.
|
|---|
| 3873 | def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
|
|---|
| 3874 | [(set GR32:$dst, 0)]>;
|
|---|
| 3875 | }
|
|---|
| 3876 |
|
|---|
| 3877 | //===----------------------------------------------------------------------===//
|
|---|
| 3878 | // Thread Local Storage Instructions
|
|---|
| 3879 | //
|
|---|
| 3880 |
|
|---|
| 3881 | // ELF TLS Support
|
|---|
| 3882 | // All calls clobber the non-callee saved registers. ESP is marked as
|
|---|
| 3883 | // a use to prevent stack-pointer assignments that appear immediately
|
|---|
| 3884 | // before calls from potentially appearing dead.
|
|---|
| 3885 | let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
|
|---|
| 3886 | MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
|---|
| 3887 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|---|
| 3888 | XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
|
|---|
| 3889 | Uses = [ESP] in
|
|---|
| 3890 | def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
|
|---|
| 3891 | "leal\t$sym, %eax; "
|
|---|
| 3892 | "call\t___tls_get_addr@PLT",
|
|---|
| 3893 | [(X86tlsaddr tls32addr:$sym)]>,
|
|---|
| 3894 | Requires<[In32BitMode]>;
|
|---|
| 3895 |
|
|---|
| 3896 | // Darwin TLS Support
|
|---|
| 3897 | // For i386, the address of the thunk is passed on the stack, on return the
|
|---|
| 3898 | // address of the variable is in %eax. %ecx is trashed during the function
|
|---|
| 3899 | // call. All other registers are preserved.
|
|---|
| 3900 | let Defs = [EAX, ECX],
|
|---|
| 3901 | Uses = [ESP],
|
|---|
| 3902 | usesCustomInserter = 1 in
|
|---|
| 3903 | def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
|
|---|
| 3904 | "# TLSCall_32",
|
|---|
| 3905 | [(X86TLSCall addr:$sym)]>,
|
|---|
| 3906 | Requires<[In32BitMode]>;
|
|---|
| 3907 |
|
|---|
| 3908 | let AddedComplexity = 5, isCodeGenOnly = 1 in
|
|---|
| 3909 | def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|---|
| 3910 | "movl\t%gs:$src, $dst",
|
|---|
| 3911 | [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
|
|---|
| 3912 |
|
|---|
| 3913 | let AddedComplexity = 5, isCodeGenOnly = 1 in
|
|---|
| 3914 | def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|---|
| 3915 | "movl\t%fs:$src, $dst",
|
|---|
| 3916 | [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
|
|---|
| 3917 |
|
|---|
| 3918 | //===----------------------------------------------------------------------===//
|
|---|
| 3919 | // EH Pseudo Instructions
|
|---|
| 3920 | //
|
|---|
| 3921 | let isTerminator = 1, isReturn = 1, isBarrier = 1,
|
|---|
| 3922 | hasCtrlDep = 1, isCodeGenOnly = 1 in {
|
|---|
| 3923 | def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
|
|---|
| 3924 | "ret\t#eh_return, addr: $addr",
|
|---|
| 3925 | [(X86ehret GR32:$addr)]>;
|
|---|
| 3926 |
|
|---|
| 3927 | }
|
|---|
| 3928 |
|
|---|
| 3929 | //===----------------------------------------------------------------------===//
|
|---|
| 3930 | // Atomic support
|
|---|
| 3931 | //
|
|---|
| 3932 |
|
|---|
| 3933 | // Memory barriers
|
|---|
| 3934 |
|
|---|
| 3935 | // TODO: Get this to fold the constant into the instruction.
|
|---|
| 3936 | def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
|
|---|
| 3937 | "lock\n\t"
|
|---|
| 3938 | "or{l}\t{$zero, $dst|$dst, $zero}",
|
|---|
| 3939 | []>, Requires<[In32BitMode]>, LOCK;
|
|---|
| 3940 |
|
|---|
| 3941 | let hasSideEffects = 1 in {
|
|---|
| 3942 | def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
|
|---|
| 3943 | "#MEMBARRIER",
|
|---|
| 3944 | [(X86MemBarrier)]>, Requires<[HasSSE2]>;
|
|---|
| 3945 | }
|
|---|
| 3946 |
|
|---|
| 3947 | // Atomic swap. These are just normal xchg instructions. But since a memory
|
|---|
| 3948 | // operand is referenced, the atomicity is ensured.
|
|---|
| 3949 | let Constraints = "$val = $dst" in {
|
|---|
| 3950 | def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
|
|---|
| 3951 | (ins GR32:$val, i32mem:$ptr),
|
|---|
| 3952 | "xchg{l}\t{$val, $ptr|$ptr, $val}",
|
|---|
| 3953 | [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
|
|---|
| 3954 | def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
|
|---|
| 3955 | (ins GR16:$val, i16mem:$ptr),
|
|---|
| 3956 | "xchg{w}\t{$val, $ptr|$ptr, $val}",
|
|---|
| 3957 | [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
|
|---|
| 3958 | OpSize;
|
|---|
| 3959 | def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
|
|---|
| 3960 | "xchg{b}\t{$val, $ptr|$ptr, $val}",
|
|---|
| 3961 | [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
|
|---|
| 3962 |
|
|---|
| 3963 | def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
|
|---|
| 3964 | "xchg{l}\t{$val, $src|$src, $val}", []>;
|
|---|
| 3965 | def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
|
|---|
| 3966 | "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
|
|---|
| 3967 | def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
|
|---|
| 3968 | "xchg{b}\t{$val, $src|$src, $val}", []>;
|
|---|
| 3969 | }
|
|---|
| 3970 |
|
|---|
| 3971 | def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
|
|---|
| 3972 | "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
|
|---|
| 3973 | def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
|
|---|
| 3974 | "xchg{l}\t{$src, %eax|%eax, $src}", []>;
|
|---|
| 3975 |
|
|---|
| 3976 | // Atomic compare and swap.
|
|---|
| 3977 | let Defs = [EAX, EFLAGS], Uses = [EAX] in {
|
|---|
| 3978 | def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
|
|---|
| 3979 | "lock\n\t"
|
|---|
| 3980 | "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
|
|---|
| 3981 | [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
|
|---|
| 3982 | }
|
|---|
| 3983 | let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
|
|---|
| 3984 | def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
|
|---|
| 3985 | "lock\n\t"
|
|---|
| 3986 | "cmpxchg8b\t$ptr",
|
|---|
| 3987 | [(X86cas8 addr:$ptr)]>, TB, LOCK;
|
|---|
| 3988 | }
|
|---|
| 3989 |
|
|---|
| 3990 | let Defs = [AX, EFLAGS], Uses = [AX] in {
|
|---|
| 3991 | def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
|
|---|
| 3992 | "lock\n\t"
|
|---|
| 3993 | "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
|
|---|
| 3994 | [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
|
|---|
| 3995 | }
|
|---|
| 3996 | let Defs = [AL, EFLAGS], Uses = [AL] in {
|
|---|
| 3997 | def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
|
|---|
| 3998 | "lock\n\t"
|
|---|
| 3999 | "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
|
|---|
| 4000 | [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
|
|---|
| 4001 | }
|
|---|
| 4002 |
|
|---|
| 4003 | // Atomic exchange and add
|
|---|
| 4004 | let Constraints = "$val = $dst", Defs = [EFLAGS] in {
|
|---|
| 4005 | def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
|
|---|
| 4006 | "lock\n\t"
|
|---|
| 4007 | "xadd{l}\t{$val, $ptr|$ptr, $val}",
|
|---|
| 4008 | [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
|
|---|
| 4009 | TB, LOCK;
|
|---|
| 4010 | def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
|
|---|
| 4011 | "lock\n\t"
|
|---|
| 4012 | "xadd{w}\t{$val, $ptr|$ptr, $val}",
|
|---|
| 4013 | [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
|
|---|
| 4014 | TB, OpSize, LOCK;
|
|---|
| 4015 | def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
|
|---|
| 4016 | "lock\n\t"
|
|---|
| 4017 | "xadd{b}\t{$val, $ptr|$ptr, $val}",
|
|---|
| 4018 | [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
|
|---|
| 4019 | TB, LOCK;
|
|---|
| 4020 | }
|
|---|
| 4021 |
|
|---|
| 4022 | def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
|
|---|
| 4023 | "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4024 | def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
|
|---|
| 4025 | "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 4026 | def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 4027 | "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4028 |
|
|---|
| 4029 | let mayLoad = 1, mayStore = 1 in {
|
|---|
| 4030 | def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
|
|---|
| 4031 | "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4032 | def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
|---|
| 4033 | "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 4034 | def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
|---|
| 4035 | "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4036 | }
|
|---|
| 4037 |
|
|---|
| 4038 | def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
|
|---|
| 4039 | "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4040 | def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
|
|---|
| 4041 | "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 4042 | def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 4043 | "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4044 |
|
|---|
| 4045 | let mayLoad = 1, mayStore = 1 in {
|
|---|
| 4046 | def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
|
|---|
| 4047 | "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4048 | def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
|---|
| 4049 | "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 4050 | def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
|---|
| 4051 | "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4052 | }
|
|---|
| 4053 |
|
|---|
| 4054 | let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
|
|---|
| 4055 | def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
|
|---|
| 4056 | "cmpxchg8b\t$dst", []>, TB;
|
|---|
| 4057 |
|
|---|
| 4058 | // Optimized codegen when the non-memory output is not used.
|
|---|
| 4059 | // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
|
|---|
| 4060 | let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
|
|---|
| 4061 | def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
|
|---|
| 4062 | "lock\n\t"
|
|---|
| 4063 | "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|---|
| 4064 | def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
|---|
| 4065 | "lock\n\t"
|
|---|
| 4066 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
|
|---|
| 4067 | def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
|---|
| 4068 | "lock\n\t"
|
|---|
| 4069 | "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|---|
| 4070 | def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
|
|---|
| 4071 | "lock\n\t"
|
|---|
| 4072 | "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|---|
| 4073 | def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
|
|---|
| 4074 | "lock\n\t"
|
|---|
| 4075 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|---|
| 4076 | def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
|
|---|
| 4077 | "lock\n\t"
|
|---|
| 4078 | "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|---|
| 4079 | def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
|
|---|
| 4080 | "lock\n\t"
|
|---|
| 4081 | "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
|
|---|
| 4082 | def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
|
|---|
| 4083 | "lock\n\t"
|
|---|
| 4084 | "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|---|
| 4085 |
|
|---|
| 4086 | def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
|
|---|
| 4087 | "lock\n\t"
|
|---|
| 4088 | "inc{b}\t$dst", []>, LOCK;
|
|---|
| 4089 | def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
|
|---|
| 4090 | "lock\n\t"
|
|---|
| 4091 | "inc{w}\t$dst", []>, OpSize, LOCK;
|
|---|
| 4092 | def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
|
|---|
| 4093 | "lock\n\t"
|
|---|
| 4094 | "inc{l}\t$dst", []>, LOCK;
|
|---|
| 4095 |
|
|---|
| 4096 | def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
|
|---|
| 4097 | "lock\n\t"
|
|---|
| 4098 | "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|---|
| 4099 | def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
|---|
| 4100 | "lock\n\t"
|
|---|
| 4101 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
|
|---|
| 4102 | def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
|---|
| 4103 | "lock\n\t"
|
|---|
| 4104 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|---|
| 4105 | def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
|
|---|
| 4106 | "lock\n\t"
|
|---|
| 4107 | "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|---|
| 4108 | def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
|
|---|
| 4109 | "lock\n\t"
|
|---|
| 4110 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
|
|---|
| 4111 | def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
|
|---|
| 4112 | "lock\n\t"
|
|---|
| 4113 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|---|
| 4114 | def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
|
|---|
| 4115 | "lock\n\t"
|
|---|
| 4116 | "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
|
|---|
| 4117 | def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
|
|---|
| 4118 | "lock\n\t"
|
|---|
| 4119 | "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
|
|---|
| 4120 |
|
|---|
| 4121 | def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
|
|---|
| 4122 | "lock\n\t"
|
|---|
| 4123 | "dec{b}\t$dst", []>, LOCK;
|
|---|
| 4124 | def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
|
|---|
| 4125 | "lock\n\t"
|
|---|
| 4126 | "dec{w}\t$dst", []>, OpSize, LOCK;
|
|---|
| 4127 | def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
|
|---|
| 4128 | "lock\n\t"
|
|---|
| 4129 | "dec{l}\t$dst", []>, LOCK;
|
|---|
| 4130 | }
|
|---|
| 4131 |
|
|---|
| 4132 | // Atomic exchange, and, or, xor
|
|---|
| 4133 | let Constraints = "$val = $dst", Defs = [EFLAGS],
|
|---|
| 4134 | usesCustomInserter = 1 in {
|
|---|
| 4135 | def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
|
|---|
| 4136 | "#ATOMAND32 PSEUDO!",
|
|---|
| 4137 | [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
|
|---|
| 4138 | def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
|
|---|
| 4139 | "#ATOMOR32 PSEUDO!",
|
|---|
| 4140 | [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
|
|---|
| 4141 | def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
|
|---|
| 4142 | "#ATOMXOR32 PSEUDO!",
|
|---|
| 4143 | [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
|
|---|
| 4144 | def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
|
|---|
| 4145 | "#ATOMNAND32 PSEUDO!",
|
|---|
| 4146 | [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
|
|---|
| 4147 | def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
|
|---|
| 4148 | "#ATOMMIN32 PSEUDO!",
|
|---|
| 4149 | [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
|
|---|
| 4150 | def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
|
|---|
| 4151 | "#ATOMMAX32 PSEUDO!",
|
|---|
| 4152 | [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
|
|---|
| 4153 | def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
|
|---|
| 4154 | "#ATOMUMIN32 PSEUDO!",
|
|---|
| 4155 | [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
|
|---|
| 4156 | def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
|
|---|
| 4157 | "#ATOMUMAX32 PSEUDO!",
|
|---|
| 4158 | [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
|
|---|
| 4159 |
|
|---|
| 4160 | def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
|
|---|
| 4161 | "#ATOMAND16 PSEUDO!",
|
|---|
| 4162 | [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
|
|---|
| 4163 | def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
|
|---|
| 4164 | "#ATOMOR16 PSEUDO!",
|
|---|
| 4165 | [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
|
|---|
| 4166 | def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
|
|---|
| 4167 | "#ATOMXOR16 PSEUDO!",
|
|---|
| 4168 | [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
|
|---|
| 4169 | def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
|
|---|
| 4170 | "#ATOMNAND16 PSEUDO!",
|
|---|
| 4171 | [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
|
|---|
| 4172 | def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
|
|---|
| 4173 | "#ATOMMIN16 PSEUDO!",
|
|---|
| 4174 | [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
|
|---|
| 4175 | def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
|
|---|
| 4176 | "#ATOMMAX16 PSEUDO!",
|
|---|
| 4177 | [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
|
|---|
| 4178 | def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
|
|---|
| 4179 | "#ATOMUMIN16 PSEUDO!",
|
|---|
| 4180 | [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
|
|---|
| 4181 | def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
|
|---|
| 4182 | "#ATOMUMAX16 PSEUDO!",
|
|---|
| 4183 | [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
|
|---|
| 4184 |
|
|---|
| 4185 | def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
|
|---|
| 4186 | "#ATOMAND8 PSEUDO!",
|
|---|
| 4187 | [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
|
|---|
| 4188 | def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
|
|---|
| 4189 | "#ATOMOR8 PSEUDO!",
|
|---|
| 4190 | [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
|
|---|
| 4191 | def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
|
|---|
| 4192 | "#ATOMXOR8 PSEUDO!",
|
|---|
| 4193 | [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
|
|---|
| 4194 | def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
|
|---|
| 4195 | "#ATOMNAND8 PSEUDO!",
|
|---|
| 4196 | [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
|
|---|
| 4197 | }
|
|---|
| 4198 |
|
|---|
| 4199 | let Constraints = "$val1 = $dst1, $val2 = $dst2",
|
|---|
| 4200 | Defs = [EFLAGS, EAX, EBX, ECX, EDX],
|
|---|
| 4201 | Uses = [EAX, EBX, ECX, EDX],
|
|---|
| 4202 | mayLoad = 1, mayStore = 1,
|
|---|
| 4203 | usesCustomInserter = 1 in {
|
|---|
| 4204 | def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
|
|---|
| 4205 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
|
|---|
| 4206 | "#ATOMAND6432 PSEUDO!", []>;
|
|---|
| 4207 | def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
|
|---|
| 4208 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
|
|---|
| 4209 | "#ATOMOR6432 PSEUDO!", []>;
|
|---|
| 4210 | def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
|
|---|
| 4211 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
|
|---|
| 4212 | "#ATOMXOR6432 PSEUDO!", []>;
|
|---|
| 4213 | def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
|
|---|
| 4214 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
|
|---|
| 4215 | "#ATOMNAND6432 PSEUDO!", []>;
|
|---|
| 4216 | def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
|
|---|
| 4217 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
|
|---|
| 4218 | "#ATOMADD6432 PSEUDO!", []>;
|
|---|
| 4219 | def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
|
|---|
| 4220 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
|
|---|
| 4221 | "#ATOMSUB6432 PSEUDO!", []>;
|
|---|
| 4222 | def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
|
|---|
| 4223 | (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
|
|---|
| 4224 | "#ATOMSWAP6432 PSEUDO!", []>;
|
|---|
| 4225 | }
|
|---|
| 4226 |
|
|---|
| 4227 | // Segmentation support instructions.
|
|---|
| 4228 |
|
|---|
| 4229 | def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
|---|
| 4230 | "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 4231 | def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
|---|
| 4232 | "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 4233 |
|
|---|
| 4234 | // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
|
|---|
| 4235 | def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
|
|---|
| 4236 | "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4237 | def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 4238 | "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4239 |
|
|---|
| 4240 | def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
|---|
| 4241 | "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 4242 | def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
|---|
| 4243 | "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 4244 | def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|---|
| 4245 | "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4246 | def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 4247 | "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4248 |
|
|---|
| 4249 | def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
|
|---|
| 4250 |
|
|---|
| 4251 | def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
|
|---|
| 4252 | "str{w}\t{$dst}", []>, TB;
|
|---|
| 4253 | def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
|
|---|
| 4254 | "str{w}\t{$dst}", []>, TB;
|
|---|
| 4255 | def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
|
|---|
| 4256 | "ltr{w}\t{$src}", []>, TB;
|
|---|
| 4257 | def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
|
|---|
| 4258 | "ltr{w}\t{$src}", []>, TB;
|
|---|
| 4259 |
|
|---|
| 4260 | def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
|
|---|
| 4261 | "push{w}\t%fs", []>, OpSize, TB;
|
|---|
| 4262 | def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
|
|---|
| 4263 | "push{l}\t%fs", []>, TB;
|
|---|
| 4264 | def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
|
|---|
| 4265 | "push{w}\t%gs", []>, OpSize, TB;
|
|---|
| 4266 | def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
|
|---|
| 4267 | "push{l}\t%gs", []>, TB;
|
|---|
| 4268 |
|
|---|
| 4269 | def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
|
|---|
| 4270 | "pop{w}\t%fs", []>, OpSize, TB;
|
|---|
| 4271 | def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
|
|---|
| 4272 | "pop{l}\t%fs", []>, TB;
|
|---|
| 4273 | def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
|
|---|
| 4274 | "pop{w}\t%gs", []>, OpSize, TB;
|
|---|
| 4275 | def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
|
|---|
| 4276 | "pop{l}\t%gs", []>, TB;
|
|---|
| 4277 |
|
|---|
| 4278 | def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
|---|
| 4279 | "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
|---|
| 4280 | def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
|---|
| 4281 | "lds{l}\t{$src, $dst|$dst, $src}", []>;
|
|---|
| 4282 | def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
|---|
| 4283 | "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 4284 | def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
|---|
| 4285 | "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4286 | def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
|---|
| 4287 | "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
|---|
| 4288 | def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
|---|
| 4289 | "les{l}\t{$src, $dst|$dst, $src}", []>;
|
|---|
| 4290 | def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
|---|
| 4291 | "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 4292 | def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
|---|
| 4293 | "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4294 | def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
|---|
| 4295 | "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|---|
| 4296 | def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
|---|
| 4297 | "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4298 |
|
|---|
| 4299 | def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
|
|---|
| 4300 | "verr\t$seg", []>, TB;
|
|---|
| 4301 | def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
|
|---|
| 4302 | "verr\t$seg", []>, TB;
|
|---|
| 4303 | def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
|
|---|
| 4304 | "verw\t$seg", []>, TB;
|
|---|
| 4305 | def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
|
|---|
| 4306 | "verw\t$seg", []>, TB;
|
|---|
| 4307 |
|
|---|
| 4308 | // Descriptor-table support instructions
|
|---|
| 4309 |
|
|---|
| 4310 | def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
|
|---|
| 4311 | "sgdt\t$dst", []>, TB;
|
|---|
| 4312 | def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
|
|---|
| 4313 | "sidt\t$dst", []>, TB;
|
|---|
| 4314 | def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
|
|---|
| 4315 | "sldt{w}\t$dst", []>, TB;
|
|---|
| 4316 | def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
|
|---|
| 4317 | "sldt{w}\t$dst", []>, TB;
|
|---|
| 4318 | def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
|
|---|
| 4319 | "lgdt\t$src", []>, TB;
|
|---|
| 4320 | def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
|
|---|
| 4321 | "lidt\t$src", []>, TB;
|
|---|
| 4322 | def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
|
|---|
| 4323 | "lldt{w}\t$src", []>, TB;
|
|---|
| 4324 | def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
|
|---|
| 4325 | "lldt{w}\t$src", []>, TB;
|
|---|
| 4326 |
|
|---|
| 4327 | // Lock instruction prefix
|
|---|
| 4328 | def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
|
|---|
| 4329 |
|
|---|
| 4330 | // Repeat string operation instruction prefixes
|
|---|
| 4331 | // These uses the DF flag in the EFLAGS register to inc or dec ECX
|
|---|
| 4332 | let Defs = [ECX], Uses = [ECX,EFLAGS] in {
|
|---|
| 4333 | // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
|
|---|
| 4334 | def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
|
|---|
| 4335 | // Repeat while not equal (used with CMPS and SCAS)
|
|---|
| 4336 | def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
|
|---|
| 4337 | }
|
|---|
| 4338 |
|
|---|
| 4339 | // Segment override instruction prefixes
|
|---|
| 4340 | def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
|
|---|
| 4341 | def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
|
|---|
| 4342 | def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
|
|---|
| 4343 | def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
|
|---|
| 4344 | def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
|
|---|
| 4345 | def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
|
|---|
| 4346 |
|
|---|
| 4347 | // String manipulation instructions
|
|---|
| 4348 |
|
|---|
| 4349 | def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
|
|---|
| 4350 | def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
|
|---|
| 4351 | def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
|
|---|
| 4352 |
|
|---|
| 4353 | def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
|
|---|
| 4354 | def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
|
|---|
| 4355 | def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
|
|---|
| 4356 |
|
|---|
| 4357 | // CPU flow control instructions
|
|---|
| 4358 |
|
|---|
| 4359 | def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
|
|---|
| 4360 | def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
|
|---|
| 4361 |
|
|---|
| 4362 | // FPU control instructions
|
|---|
| 4363 |
|
|---|
| 4364 | def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
|
|---|
| 4365 |
|
|---|
| 4366 | // Flag instructions
|
|---|
| 4367 |
|
|---|
| 4368 | def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
|
|---|
| 4369 | def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
|
|---|
| 4370 | def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
|
|---|
| 4371 | def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
|
|---|
| 4372 | def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
|
|---|
| 4373 | def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
|
|---|
| 4374 | def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
|
|---|
| 4375 |
|
|---|
| 4376 | def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
|
|---|
| 4377 |
|
|---|
| 4378 | // Table lookup instructions
|
|---|
| 4379 |
|
|---|
| 4380 | def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
|
|---|
| 4381 |
|
|---|
| 4382 | // Specialized register support
|
|---|
| 4383 |
|
|---|
| 4384 | def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
|
|---|
| 4385 | def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
|
|---|
| 4386 | def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
|
|---|
| 4387 |
|
|---|
| 4388 | def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
|
|---|
| 4389 | "smsw{w}\t$dst", []>, OpSize, TB;
|
|---|
| 4390 | def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
|
|---|
| 4391 | "smsw{l}\t$dst", []>, TB;
|
|---|
| 4392 | // For memory operands, there is only a 16-bit form
|
|---|
| 4393 | def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
|
|---|
| 4394 | "smsw{w}\t$dst", []>, TB;
|
|---|
| 4395 |
|
|---|
| 4396 | def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
|
|---|
| 4397 | "lmsw{w}\t$src", []>, TB;
|
|---|
| 4398 | def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
|
|---|
| 4399 | "lmsw{w}\t$src", []>, TB;
|
|---|
| 4400 |
|
|---|
| 4401 | def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
|
|---|
| 4402 |
|
|---|
| 4403 | // Cache instructions
|
|---|
| 4404 |
|
|---|
| 4405 | def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
|
|---|
| 4406 | def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
|
|---|
| 4407 |
|
|---|
| 4408 | // VMX instructions
|
|---|
| 4409 |
|
|---|
| 4410 | // 66 0F 38 80
|
|---|
| 4411 | def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
|
|---|
| 4412 | // 66 0F 38 81
|
|---|
| 4413 | def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
|
|---|
| 4414 | // 0F 01 C1
|
|---|
| 4415 | def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
|
|---|
| 4416 | def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
|
|---|
| 4417 | "vmclear\t$vmcs", []>, OpSize, TB;
|
|---|
| 4418 | // 0F 01 C2
|
|---|
| 4419 | def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
|
|---|
| 4420 | // 0F 01 C3
|
|---|
| 4421 | def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
|
|---|
| 4422 | def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
|
|---|
| 4423 | "vmptrld\t$vmcs", []>, TB;
|
|---|
| 4424 | def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
|
|---|
| 4425 | "vmptrst\t$vmcs", []>, TB;
|
|---|
| 4426 | def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
|
|---|
| 4427 | "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4428 | def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
|---|
| 4429 | "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4430 | def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
|
|---|
| 4431 | "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4432 | def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 4433 | "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4434 | def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
|---|
| 4435 | "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4436 | def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
|---|
| 4437 | "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4438 | def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
|---|
| 4439 | "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4440 | def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
|---|
| 4441 | "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|---|
| 4442 | // 0F 01 C4
|
|---|
| 4443 | def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
|
|---|
| 4444 | def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
|
|---|
| 4445 | "vmxon\t{$vmxon}", []>, XS;
|
|---|
| 4446 |
|
|---|
| 4447 | //===----------------------------------------------------------------------===//
|
|---|
| 4448 | // Non-Instruction Patterns
|
|---|
| 4449 | //===----------------------------------------------------------------------===//
|
|---|
| 4450 |
|
|---|
| 4451 | // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
|
|---|
| 4452 | def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
|
|---|
| 4453 | def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
|
|---|
| 4454 | def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
|
|---|
| 4455 | def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
|
|---|
| 4456 | def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
|
|---|
| 4457 | def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
|
|---|
| 4458 |
|
|---|
| 4459 | def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
|
|---|
| 4460 | (ADD32ri GR32:$src1, tconstpool:$src2)>;
|
|---|
| 4461 | def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
|
|---|
| 4462 | (ADD32ri GR32:$src1, tjumptable:$src2)>;
|
|---|
| 4463 | def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
|
|---|
| 4464 | (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
|
|---|
| 4465 | def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
|
|---|
| 4466 | (ADD32ri GR32:$src1, texternalsym:$src2)>;
|
|---|
| 4467 | def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
|
|---|
| 4468 | (ADD32ri GR32:$src1, tblockaddress:$src2)>;
|
|---|
| 4469 |
|
|---|
| 4470 | def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
|
|---|
| 4471 | (MOV32mi addr:$dst, tglobaladdr:$src)>;
|
|---|
| 4472 | def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
|
|---|
| 4473 | (MOV32mi addr:$dst, texternalsym:$src)>;
|
|---|
| 4474 | def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
|
|---|
| 4475 | (MOV32mi addr:$dst, tblockaddress:$src)>;
|
|---|
| 4476 |
|
|---|
| 4477 | // Calls
|
|---|
| 4478 | // tailcall stuff
|
|---|
| 4479 | def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
|
|---|
| 4480 | (TCRETURNri GR32_TC:$dst, imm:$off)>,
|
|---|
| 4481 | Requires<[In32BitMode]>;
|
|---|
| 4482 |
|
|---|
| 4483 | // FIXME: This is disabled for 32-bit PIC mode because the global base
|
|---|
| 4484 | // register which is part of the address mode may be assigned a
|
|---|
| 4485 | // callee-saved register.
|
|---|
| 4486 | def : Pat<(X86tcret (load addr:$dst), imm:$off),
|
|---|
| 4487 | (TCRETURNmi addr:$dst, imm:$off)>,
|
|---|
| 4488 | Requires<[In32BitMode, IsNotPIC]>;
|
|---|
| 4489 |
|
|---|
| 4490 | def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
|
|---|
| 4491 | (TCRETURNdi texternalsym:$dst, imm:$off)>,
|
|---|
| 4492 | Requires<[In32BitMode]>;
|
|---|
| 4493 |
|
|---|
| 4494 | def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
|
|---|
| 4495 | (TCRETURNdi texternalsym:$dst, imm:$off)>,
|
|---|
| 4496 | Requires<[In32BitMode]>;
|
|---|
| 4497 |
|
|---|
| 4498 | // Normal calls, with various flavors of addresses.
|
|---|
| 4499 | def : Pat<(X86call (i32 tglobaladdr:$dst)),
|
|---|
| 4500 | (CALLpcrel32 tglobaladdr:$dst)>;
|
|---|
| 4501 | def : Pat<(X86call (i32 texternalsym:$dst)),
|
|---|
| 4502 | (CALLpcrel32 texternalsym:$dst)>;
|
|---|
| 4503 | def : Pat<(X86call (i32 imm:$dst)),
|
|---|
| 4504 | (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
|
|---|
| 4505 |
|
|---|
| 4506 | // X86 specific add which produces a flag.
|
|---|
| 4507 | def : Pat<(addc GR32:$src1, GR32:$src2),
|
|---|
| 4508 | (ADD32rr GR32:$src1, GR32:$src2)>;
|
|---|
| 4509 | def : Pat<(addc GR32:$src1, (load addr:$src2)),
|
|---|
| 4510 | (ADD32rm GR32:$src1, addr:$src2)>;
|
|---|
| 4511 | def : Pat<(addc GR32:$src1, imm:$src2),
|
|---|
| 4512 | (ADD32ri GR32:$src1, imm:$src2)>;
|
|---|
| 4513 | def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
|
|---|
| 4514 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|---|
| 4515 |
|
|---|
| 4516 | def : Pat<(subc GR32:$src1, GR32:$src2),
|
|---|
| 4517 | (SUB32rr GR32:$src1, GR32:$src2)>;
|
|---|
| 4518 | def : Pat<(subc GR32:$src1, (load addr:$src2)),
|
|---|
| 4519 | (SUB32rm GR32:$src1, addr:$src2)>;
|
|---|
| 4520 | def : Pat<(subc GR32:$src1, imm:$src2),
|
|---|
| 4521 | (SUB32ri GR32:$src1, imm:$src2)>;
|
|---|
| 4522 | def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
|
|---|
| 4523 | (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|---|
| 4524 |
|
|---|
| 4525 | // Comparisons.
|
|---|
| 4526 |
|
|---|
| 4527 | // TEST R,R is smaller than CMP R,0
|
|---|
| 4528 | def : Pat<(X86cmp GR8:$src1, 0),
|
|---|
| 4529 | (TEST8rr GR8:$src1, GR8:$src1)>;
|
|---|
| 4530 | def : Pat<(X86cmp GR16:$src1, 0),
|
|---|
| 4531 | (TEST16rr GR16:$src1, GR16:$src1)>;
|
|---|
| 4532 | def : Pat<(X86cmp GR32:$src1, 0),
|
|---|
| 4533 | (TEST32rr GR32:$src1, GR32:$src1)>;
|
|---|
| 4534 |
|
|---|
| 4535 | // Conditional moves with folded loads with operands swapped and conditions
|
|---|
| 4536 | // inverted.
|
|---|
| 4537 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
|
|---|
| 4538 | (CMOVAE16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4539 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
|
|---|
| 4540 | (CMOVAE32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4541 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
|
|---|
| 4542 | (CMOVB16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4543 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
|
|---|
| 4544 | (CMOVB32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4545 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
|
|---|
| 4546 | (CMOVNE16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4547 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
|
|---|
| 4548 | (CMOVNE32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4549 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
|
|---|
| 4550 | (CMOVE16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4551 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
|
|---|
| 4552 | (CMOVE32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4553 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
|
|---|
| 4554 | (CMOVA16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4555 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
|
|---|
| 4556 | (CMOVA32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4557 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
|
|---|
| 4558 | (CMOVBE16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4559 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
|
|---|
| 4560 | (CMOVBE32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4561 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
|
|---|
| 4562 | (CMOVGE16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4563 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
|
|---|
| 4564 | (CMOVGE32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4565 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
|
|---|
| 4566 | (CMOVL16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4567 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
|
|---|
| 4568 | (CMOVL32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4569 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
|
|---|
| 4570 | (CMOVG16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4571 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
|
|---|
| 4572 | (CMOVG32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4573 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
|
|---|
| 4574 | (CMOVLE16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4575 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
|
|---|
| 4576 | (CMOVLE32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4577 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
|
|---|
| 4578 | (CMOVNP16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4579 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
|
|---|
| 4580 | (CMOVNP32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4581 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
|
|---|
| 4582 | (CMOVP16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4583 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
|
|---|
| 4584 | (CMOVP32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4585 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
|
|---|
| 4586 | (CMOVNS16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4587 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
|
|---|
| 4588 | (CMOVNS32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4589 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
|
|---|
| 4590 | (CMOVS16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4591 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
|
|---|
| 4592 | (CMOVS32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4593 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
|
|---|
| 4594 | (CMOVNO16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4595 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
|
|---|
| 4596 | (CMOVNO32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4597 | def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
|
|---|
| 4598 | (CMOVO16rm GR16:$src2, addr:$src1)>;
|
|---|
| 4599 | def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
|
|---|
| 4600 | (CMOVO32rm GR32:$src2, addr:$src1)>;
|
|---|
| 4601 |
|
|---|
| 4602 | // zextload bool -> zextload byte
|
|---|
| 4603 | def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
|
|---|
| 4604 | def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
|
|---|
| 4605 | def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
|
|---|
| 4606 |
|
|---|
| 4607 | // extload bool -> extload byte
|
|---|
| 4608 | def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
|
|---|
| 4609 | def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
|
|---|
| 4610 | def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
|
|---|
| 4611 | def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
|
|---|
| 4612 | def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
|
|---|
| 4613 | def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
|
|---|
| 4614 |
|
|---|
| 4615 | // anyext. Define these to do an explicit zero-extend to
|
|---|
| 4616 | // avoid partial-register updates.
|
|---|
| 4617 | def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
|
|---|
| 4618 | def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
|
|---|
| 4619 |
|
|---|
| 4620 | // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
|
|---|
| 4621 | def : Pat<(i32 (anyext GR16:$src)),
|
|---|
| 4622 | (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
|
|---|
| 4623 |
|
|---|
| 4624 |
|
|---|
| 4625 | //===----------------------------------------------------------------------===//
|
|---|
| 4626 | // Some peepholes
|
|---|
| 4627 | //===----------------------------------------------------------------------===//
|
|---|
| 4628 |
|
|---|
| 4629 | // Odd encoding trick: -128 fits into an 8-bit immediate field while
|
|---|
| 4630 | // +128 doesn't, so in this special case use a sub instead of an add.
|
|---|
| 4631 | def : Pat<(add GR16:$src1, 128),
|
|---|
| 4632 | (SUB16ri8 GR16:$src1, -128)>;
|
|---|
| 4633 | def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
|
|---|
| 4634 | (SUB16mi8 addr:$dst, -128)>;
|
|---|
| 4635 | def : Pat<(add GR32:$src1, 128),
|
|---|
| 4636 | (SUB32ri8 GR32:$src1, -128)>;
|
|---|
| 4637 | def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
|
|---|
| 4638 | (SUB32mi8 addr:$dst, -128)>;
|
|---|
| 4639 |
|
|---|
| 4640 | // r & (2^16-1) ==> movz
|
|---|
| 4641 | def : Pat<(and GR32:$src1, 0xffff),
|
|---|
| 4642 | (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
|
|---|
| 4643 | // r & (2^8-1) ==> movz
|
|---|
| 4644 | def : Pat<(and GR32:$src1, 0xff),
|
|---|
| 4645 | (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
|
|---|
| 4646 | GR32_ABCD)),
|
|---|
| 4647 | sub_8bit))>,
|
|---|
| 4648 | Requires<[In32BitMode]>;
|
|---|
| 4649 | // r & (2^8-1) ==> movz
|
|---|
| 4650 | def : Pat<(and GR16:$src1, 0xff),
|
|---|
| 4651 | (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
|
|---|
| 4652 | GR16_ABCD)),
|
|---|
| 4653 | sub_8bit))>,
|
|---|
| 4654 | Requires<[In32BitMode]>;
|
|---|
| 4655 |
|
|---|
| 4656 | // sext_inreg patterns
|
|---|
| 4657 | def : Pat<(sext_inreg GR32:$src, i16),
|
|---|
| 4658 | (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
|
|---|
| 4659 | def : Pat<(sext_inreg GR32:$src, i8),
|
|---|
| 4660 | (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
|---|
| 4661 | GR32_ABCD)),
|
|---|
| 4662 | sub_8bit))>,
|
|---|
| 4663 | Requires<[In32BitMode]>;
|
|---|
| 4664 | def : Pat<(sext_inreg GR16:$src, i8),
|
|---|
| 4665 | (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
|---|
| 4666 | GR16_ABCD)),
|
|---|
| 4667 | sub_8bit))>,
|
|---|
| 4668 | Requires<[In32BitMode]>;
|
|---|
| 4669 |
|
|---|
| 4670 | // trunc patterns
|
|---|
| 4671 | def : Pat<(i16 (trunc GR32:$src)),
|
|---|
| 4672 | (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
|
|---|
| 4673 | def : Pat<(i8 (trunc GR32:$src)),
|
|---|
| 4674 | (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
|
|---|
| 4675 | sub_8bit)>,
|
|---|
| 4676 | Requires<[In32BitMode]>;
|
|---|
| 4677 | def : Pat<(i8 (trunc GR16:$src)),
|
|---|
| 4678 | (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|---|
| 4679 | sub_8bit)>,
|
|---|
| 4680 | Requires<[In32BitMode]>;
|
|---|
| 4681 |
|
|---|
| 4682 | // h-register tricks
|
|---|
| 4683 | def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
|
|---|
| 4684 | (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|---|
| 4685 | sub_8bit_hi)>,
|
|---|
| 4686 | Requires<[In32BitMode]>;
|
|---|
| 4687 | def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
|
|---|
| 4688 | (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
|
|---|
| 4689 | sub_8bit_hi)>,
|
|---|
| 4690 | Requires<[In32BitMode]>;
|
|---|
| 4691 | def : Pat<(srl GR16:$src, (i8 8)),
|
|---|
| 4692 | (EXTRACT_SUBREG
|
|---|
| 4693 | (MOVZX32rr8
|
|---|
| 4694 | (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
|
|---|
| 4695 | sub_8bit_hi)),
|
|---|
| 4696 | sub_16bit)>,
|
|---|
| 4697 | Requires<[In32BitMode]>;
|
|---|
| 4698 | def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
|
|---|
| 4699 | (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
|---|
| 4700 | GR16_ABCD)),
|
|---|
| 4701 | sub_8bit_hi))>,
|
|---|
| 4702 | Requires<[In32BitMode]>;
|
|---|
| 4703 | def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
|
|---|
| 4704 | (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
|
|---|
| 4705 | GR16_ABCD)),
|
|---|
| 4706 | sub_8bit_hi))>,
|
|---|
| 4707 | Requires<[In32BitMode]>;
|
|---|
| 4708 | def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
|
|---|
| 4709 | (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
|---|
| 4710 | GR32_ABCD)),
|
|---|
| 4711 | sub_8bit_hi))>,
|
|---|
| 4712 | Requires<[In32BitMode]>;
|
|---|
| 4713 | def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
|
|---|
| 4714 | (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
|
|---|
| 4715 | GR32_ABCD)),
|
|---|
| 4716 | sub_8bit_hi))>,
|
|---|
| 4717 | Requires<[In32BitMode]>;
|
|---|
| 4718 |
|
|---|
| 4719 | // (shl x, 1) ==> (add x, x)
|
|---|
| 4720 | def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
|
|---|
| 4721 | def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
|
|---|
| 4722 | def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
|
|---|
| 4723 |
|
|---|
| 4724 | // (shl x (and y, 31)) ==> (shl x, y)
|
|---|
| 4725 | def : Pat<(shl GR8:$src1, (and CL, 31)),
|
|---|
| 4726 | (SHL8rCL GR8:$src1)>;
|
|---|
| 4727 | def : Pat<(shl GR16:$src1, (and CL, 31)),
|
|---|
| 4728 | (SHL16rCL GR16:$src1)>;
|
|---|
| 4729 | def : Pat<(shl GR32:$src1, (and CL, 31)),
|
|---|
| 4730 | (SHL32rCL GR32:$src1)>;
|
|---|
| 4731 | def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
|
|---|
| 4732 | (SHL8mCL addr:$dst)>;
|
|---|
| 4733 | def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
|
|---|
| 4734 | (SHL16mCL addr:$dst)>;
|
|---|
| 4735 | def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
|
|---|
| 4736 | (SHL32mCL addr:$dst)>;
|
|---|
| 4737 |
|
|---|
| 4738 | def : Pat<(srl GR8:$src1, (and CL, 31)),
|
|---|
| 4739 | (SHR8rCL GR8:$src1)>;
|
|---|
| 4740 | def : Pat<(srl GR16:$src1, (and CL, 31)),
|
|---|
| 4741 | (SHR16rCL GR16:$src1)>;
|
|---|
| 4742 | def : Pat<(srl GR32:$src1, (and CL, 31)),
|
|---|
| 4743 | (SHR32rCL GR32:$src1)>;
|
|---|
| 4744 | def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
|
|---|
| 4745 | (SHR8mCL addr:$dst)>;
|
|---|
| 4746 | def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
|
|---|
| 4747 | (SHR16mCL addr:$dst)>;
|
|---|
| 4748 | def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
|
|---|
| 4749 | (SHR32mCL addr:$dst)>;
|
|---|
| 4750 |
|
|---|
| 4751 | def : Pat<(sra GR8:$src1, (and CL, 31)),
|
|---|
| 4752 | (SAR8rCL GR8:$src1)>;
|
|---|
| 4753 | def : Pat<(sra GR16:$src1, (and CL, 31)),
|
|---|
| 4754 | (SAR16rCL GR16:$src1)>;
|
|---|
| 4755 | def : Pat<(sra GR32:$src1, (and CL, 31)),
|
|---|
| 4756 | (SAR32rCL GR32:$src1)>;
|
|---|
| 4757 | def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
|
|---|
| 4758 | (SAR8mCL addr:$dst)>;
|
|---|
| 4759 | def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
|
|---|
| 4760 | (SAR16mCL addr:$dst)>;
|
|---|
| 4761 | def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
|
|---|
| 4762 | (SAR32mCL addr:$dst)>;
|
|---|
| 4763 |
|
|---|
| 4764 | // (anyext (setcc_carry)) -> (setcc_carry)
|
|---|
| 4765 | def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
|
|---|
| 4766 | (SETB_C16r)>;
|
|---|
| 4767 | def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
|
|---|
| 4768 | (SETB_C32r)>;
|
|---|
| 4769 | def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
|
|---|
| 4770 | (SETB_C32r)>;
|
|---|
| 4771 |
|
|---|
| 4772 | // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
|
|---|
| 4773 | let AddedComplexity = 5 in { // Try this before the selecting to OR
|
|---|
| 4774 | def : Pat<(or_is_add GR16:$src1, imm:$src2),
|
|---|
| 4775 | (ADD16ri GR16:$src1, imm:$src2)>;
|
|---|
| 4776 | def : Pat<(or_is_add GR32:$src1, imm:$src2),
|
|---|
| 4777 | (ADD32ri GR32:$src1, imm:$src2)>;
|
|---|
| 4778 | def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
|
|---|
| 4779 | (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
|
|---|
| 4780 | def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
|
|---|
| 4781 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|---|
| 4782 | def : Pat<(or_is_add GR16:$src1, GR16:$src2),
|
|---|
| 4783 | (ADD16rr GR16:$src1, GR16:$src2)>;
|
|---|
| 4784 | def : Pat<(or_is_add GR32:$src1, GR32:$src2),
|
|---|
| 4785 | (ADD32rr GR32:$src1, GR32:$src2)>;
|
|---|
| 4786 | } // AddedComplexity
|
|---|
| 4787 |
|
|---|
| 4788 | //===----------------------------------------------------------------------===//
|
|---|
| 4789 | // EFLAGS-defining Patterns
|
|---|
| 4790 | //===----------------------------------------------------------------------===//
|
|---|
| 4791 |
|
|---|
| 4792 | // add reg, reg
|
|---|
| 4793 | def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
|
|---|
| 4794 | def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
|
|---|
| 4795 | def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
|
|---|
| 4796 |
|
|---|
| 4797 | // add reg, mem
|
|---|
| 4798 | def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
|
|---|
| 4799 | (ADD8rm GR8:$src1, addr:$src2)>;
|
|---|
| 4800 | def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
|
|---|
| 4801 | (ADD16rm GR16:$src1, addr:$src2)>;
|
|---|
| 4802 | def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
|
|---|
| 4803 | (ADD32rm GR32:$src1, addr:$src2)>;
|
|---|
| 4804 |
|
|---|
| 4805 | // add reg, imm
|
|---|
| 4806 | def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
|
|---|
| 4807 | def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
|
|---|
| 4808 | def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
|
|---|
| 4809 | def : Pat<(add GR16:$src1, i16immSExt8:$src2),
|
|---|
| 4810 | (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
|
|---|
| 4811 | def : Pat<(add GR32:$src1, i32immSExt8:$src2),
|
|---|
| 4812 | (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|---|
| 4813 |
|
|---|
| 4814 | // sub reg, reg
|
|---|
| 4815 | def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
|
|---|
| 4816 | def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
|
|---|
| 4817 | def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
|
|---|
| 4818 |
|
|---|
| 4819 | // sub reg, mem
|
|---|
| 4820 | def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
|
|---|
| 4821 | (SUB8rm GR8:$src1, addr:$src2)>;
|
|---|
| 4822 | def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
|
|---|
| 4823 | (SUB16rm GR16:$src1, addr:$src2)>;
|
|---|
| 4824 | def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
|
|---|
| 4825 | (SUB32rm GR32:$src1, addr:$src2)>;
|
|---|
| 4826 |
|
|---|
| 4827 | // sub reg, imm
|
|---|
| 4828 | def : Pat<(sub GR8:$src1, imm:$src2),
|
|---|
| 4829 | (SUB8ri GR8:$src1, imm:$src2)>;
|
|---|
| 4830 | def : Pat<(sub GR16:$src1, imm:$src2),
|
|---|
| 4831 | (SUB16ri GR16:$src1, imm:$src2)>;
|
|---|
| 4832 | def : Pat<(sub GR32:$src1, imm:$src2),
|
|---|
| 4833 | (SUB32ri GR32:$src1, imm:$src2)>;
|
|---|
| 4834 | def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
|
|---|
| 4835 | (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
|
|---|
| 4836 | def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
|
|---|
| 4837 | (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|---|
| 4838 |
|
|---|
| 4839 | // mul reg, reg
|
|---|
| 4840 | def : Pat<(mul GR16:$src1, GR16:$src2),
|
|---|
| 4841 | (IMUL16rr GR16:$src1, GR16:$src2)>;
|
|---|
| 4842 | def : Pat<(mul GR32:$src1, GR32:$src2),
|
|---|
| 4843 | (IMUL32rr GR32:$src1, GR32:$src2)>;
|
|---|
| 4844 |
|
|---|
| 4845 | // mul reg, mem
|
|---|
| 4846 | def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
|
|---|
| 4847 | (IMUL16rm GR16:$src1, addr:$src2)>;
|
|---|
| 4848 | def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
|
|---|
| 4849 | (IMUL32rm GR32:$src1, addr:$src2)>;
|
|---|
| 4850 |
|
|---|
| 4851 | // mul reg, imm
|
|---|
| 4852 | def : Pat<(mul GR16:$src1, imm:$src2),
|
|---|
| 4853 | (IMUL16rri GR16:$src1, imm:$src2)>;
|
|---|
| 4854 | def : Pat<(mul GR32:$src1, imm:$src2),
|
|---|
| 4855 | (IMUL32rri GR32:$src1, imm:$src2)>;
|
|---|
| 4856 | def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
|
|---|
| 4857 | (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
|
|---|
| 4858 | def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
|
|---|
| 4859 | (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
|
|---|
| 4860 |
|
|---|
| 4861 | // reg = mul mem, imm
|
|---|
| 4862 | def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
|
|---|
| 4863 | (IMUL16rmi addr:$src1, imm:$src2)>;
|
|---|
| 4864 | def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
|
|---|
| 4865 | (IMUL32rmi addr:$src1, imm:$src2)>;
|
|---|
| 4866 | def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
|
|---|
| 4867 | (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
|
|---|
| 4868 | def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
|
|---|
| 4869 | (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
|
|---|
| 4870 |
|
|---|
| 4871 | // Optimize multiply by 2 with EFLAGS result.
|
|---|
| 4872 | let AddedComplexity = 2 in {
|
|---|
| 4873 | def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
|
|---|
| 4874 | def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
|
|---|
| 4875 | }
|
|---|
| 4876 |
|
|---|
| 4877 | // Patterns for nodes that do not produce flags, for instructions that do.
|
|---|
| 4878 |
|
|---|
| 4879 | // Increment reg.
|
|---|
| 4880 | def : Pat<(add GR8:$src1 , 1), (INC8r GR8:$src1)>;
|
|---|
| 4881 | def : Pat<(add GR16:$src1, 1), (INC16r GR16:$src1)>, Requires<[In32BitMode]>;
|
|---|
| 4882 | def : Pat<(add GR32:$src1, 1), (INC32r GR32:$src1)>, Requires<[In32BitMode]>;
|
|---|
| 4883 |
|
|---|
| 4884 | // Decrement reg.
|
|---|
| 4885 | def : Pat<(add GR8:$src1 , -1), (DEC8r GR8:$src1)>;
|
|---|
| 4886 | def : Pat<(add GR16:$src1, -1), (DEC16r GR16:$src1)>, Requires<[In32BitMode]>;
|
|---|
| 4887 | def : Pat<(add GR32:$src1, -1), (DEC32r GR32:$src1)>, Requires<[In32BitMode]>;
|
|---|
| 4888 |
|
|---|
| 4889 | // or reg/reg.
|
|---|
| 4890 | def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
|
|---|
| 4891 | def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
|
|---|
| 4892 | def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
|
|---|
| 4893 |
|
|---|
| 4894 | // or reg/mem
|
|---|
| 4895 | def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
|
|---|
| 4896 | (OR8rm GR8:$src1, addr:$src2)>;
|
|---|
| 4897 | def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
|
|---|
| 4898 | (OR16rm GR16:$src1, addr:$src2)>;
|
|---|
| 4899 | def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
|
|---|
| 4900 | (OR32rm GR32:$src1, addr:$src2)>;
|
|---|
| 4901 |
|
|---|
| 4902 | // or reg/imm
|
|---|
| 4903 | def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
|
|---|
| 4904 | def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
|
|---|
| 4905 | def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
|
|---|
| 4906 | def : Pat<(or GR16:$src1, i16immSExt8:$src2),
|
|---|
| 4907 | (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
|
|---|
| 4908 | def : Pat<(or GR32:$src1, i32immSExt8:$src2),
|
|---|
| 4909 | (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|---|
| 4910 |
|
|---|
| 4911 | // xor reg/reg
|
|---|
| 4912 | def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
|
|---|
| 4913 | def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
|
|---|
| 4914 | def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
|
|---|
| 4915 |
|
|---|
| 4916 | // xor reg/mem
|
|---|
| 4917 | def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
|
|---|
| 4918 | (XOR8rm GR8:$src1, addr:$src2)>;
|
|---|
| 4919 | def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
|
|---|
| 4920 | (XOR16rm GR16:$src1, addr:$src2)>;
|
|---|
| 4921 | def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
|
|---|
| 4922 | (XOR32rm GR32:$src1, addr:$src2)>;
|
|---|
| 4923 |
|
|---|
| 4924 | // xor reg/imm
|
|---|
| 4925 | def : Pat<(xor GR8:$src1, imm:$src2),
|
|---|
| 4926 | (XOR8ri GR8:$src1, imm:$src2)>;
|
|---|
| 4927 | def : Pat<(xor GR16:$src1, imm:$src2),
|
|---|
| 4928 | (XOR16ri GR16:$src1, imm:$src2)>;
|
|---|
| 4929 | def : Pat<(xor GR32:$src1, imm:$src2),
|
|---|
| 4930 | (XOR32ri GR32:$src1, imm:$src2)>;
|
|---|
| 4931 | def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
|
|---|
| 4932 | (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
|
|---|
| 4933 | def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
|
|---|
| 4934 | (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|---|
| 4935 |
|
|---|
| 4936 | // and reg/reg
|
|---|
| 4937 | def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
|
|---|
| 4938 | def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
|
|---|
| 4939 | def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
|
|---|
| 4940 |
|
|---|
| 4941 | // and reg/mem
|
|---|
| 4942 | def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
|
|---|
| 4943 | (AND8rm GR8:$src1, addr:$src2)>;
|
|---|
| 4944 | def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
|
|---|
| 4945 | (AND16rm GR16:$src1, addr:$src2)>;
|
|---|
| 4946 | def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
|
|---|
| 4947 | (AND32rm GR32:$src1, addr:$src2)>;
|
|---|
| 4948 |
|
|---|
| 4949 | // and reg/imm
|
|---|
| 4950 | def : Pat<(and GR8:$src1, imm:$src2),
|
|---|
| 4951 | (AND8ri GR8:$src1, imm:$src2)>;
|
|---|
| 4952 | def : Pat<(and GR16:$src1, imm:$src2),
|
|---|
| 4953 | (AND16ri GR16:$src1, imm:$src2)>;
|
|---|
| 4954 | def : Pat<(and GR32:$src1, imm:$src2),
|
|---|
| 4955 | (AND32ri GR32:$src1, imm:$src2)>;
|
|---|
| 4956 | def : Pat<(and GR16:$src1, i16immSExt8:$src2),
|
|---|
| 4957 | (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
|
|---|
| 4958 | def : Pat<(and GR32:$src1, i32immSExt8:$src2),
|
|---|
| 4959 | (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
|---|
| 4960 |
|
|---|
| 4961 | //===----------------------------------------------------------------------===//
|
|---|
| 4962 | // Floating Point Stack Support
|
|---|
| 4963 | //===----------------------------------------------------------------------===//
|
|---|
| 4964 |
|
|---|
| 4965 | include "X86InstrFPStack.td"
|
|---|
| 4966 |
|
|---|
| 4967 | //===----------------------------------------------------------------------===//
|
|---|
| 4968 | // X86-64 Support
|
|---|
| 4969 | //===----------------------------------------------------------------------===//
|
|---|
| 4970 |
|
|---|
| 4971 | include "X86Instr64bit.td"
|
|---|
| 4972 |
|
|---|
| 4973 | //===----------------------------------------------------------------------===//
|
|---|
| 4974 | // SIMD support (SSE, MMX and AVX)
|
|---|
| 4975 | //===----------------------------------------------------------------------===//
|
|---|
| 4976 |
|
|---|
| 4977 | include "X86InstrFragmentsSIMD.td"
|
|---|
| 4978 |
|
|---|
| 4979 | //===----------------------------------------------------------------------===//
|
|---|
| 4980 | // FMA - Fused Multiply-Add support (requires FMA)
|
|---|
| 4981 | //===----------------------------------------------------------------------===//
|
|---|
| 4982 |
|
|---|
| 4983 | include "X86InstrFMA.td"
|
|---|
| 4984 |
|
|---|
| 4985 | //===----------------------------------------------------------------------===//
|
|---|
| 4986 | // XMM Floating point support (requires SSE / SSE2)
|
|---|
| 4987 | //===----------------------------------------------------------------------===//
|
|---|
| 4988 |
|
|---|
| 4989 | include "X86InstrSSE.td"
|
|---|
| 4990 |
|
|---|
| 4991 | //===----------------------------------------------------------------------===//
|
|---|
| 4992 | // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
|
|---|
| 4993 | //===----------------------------------------------------------------------===//
|
|---|
| 4994 |
|
|---|
| 4995 | include "X86InstrMMX.td"
|
|---|
