source: binutils/trunk/opcodes/arc-ext-tbl.h@ 1973

Last change on this file since 1973 was 1973, checked in by Silvan Scherrer, 8 years ago

binutils: update trunk to version 2.27
File size: 5.6 KB
Line 
1/* ARC instruction defintions.
2 Copyright (C) 2016 Free Software Foundation, Inc.
3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21
22/* Common combinations of FLAGS. */
23#define FLAGS_NONE { 0 }
24#define FLAGS_F { C_F }
25#define FLAGS_CC { C_CC }
26#define FLAGS_CCF { C_CC, C_F }
27
28/* Common combination of arguments. */
29#define ARG_NONE { 0 }
30#define ARG_32BIT_RARBRC { RA, RB, RC }
31#define ARG_32BIT_ZARBRC { ZA, RB, RC }
32#define ARG_32BIT_RBRBRC { RB, RBdup, RC }
33#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
34#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
35#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
36#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
37#define ARG_32BIT_RALIMMRC { RA, LIMM, RC }
38#define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
39#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC }
40#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
41
42#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM }
43#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 }
44#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 }
45
46#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 }
47#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup }
48#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup }
49
50#define ARG_32BIT_RBRC { RB, RC }
51#define ARG_32BIT_ZARC { ZA, RC }
52#define ARG_32BIT_RBU6 { RB, UIMM6_20 }
53#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 }
54#define ARG_32BIT_RBLIMM { RB, LIMM }
55#define ARG_32BIT_ZALIMM { ZA, LIMM }
56
57/* Macro to generate 2 operand extension instruction. */
58#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
59 { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
60 ARG_32BIT_RBRC, FLAGS_F }, \
61 { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
62 ARG_32BIT_ZARC, FLAGS_F }, \
63 { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
64 ARG_32BIT_RBU6, FLAGS_F }, \
65 { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
66 ARG_32BIT_ZAU6, FLAGS_F }, \
67 { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
68 ARG_32BIT_RBLIMM, FLAGS_F }, \
69 { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
70 ARG_32BIT_ZALIMM, FLAGS_F },
71
72/* Macro to generate 3 operand extesion instruction. */
73#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
74 { NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \
75 ARG_32BIT_RARBRC, FLAGS_F }, \
76 { NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \
77 ARG_32BIT_ZARBRC, FLAGS_F }, \
78 { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \
79 ARG_32BIT_RBRBRC, FLAGS_CCF }, \
80 { NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \
81 ARG_32BIT_RARBU6, FLAGS_F }, \
82 { NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \
83 ARG_32BIT_ZARBU6, FLAGS_F }, \
84 { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \
85 ARG_32BIT_RBRBU6, FLAGS_CCF }, \
86 { NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \
87 ARG_32BIT_RBRBS12, FLAGS_F }, \
88 { NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
89 ARG_32BIT_RALIMMRC, FLAGS_F }, \
90 { NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
91 ARG_32BIT_RARBLIMM, FLAGS_F }, \
92 { NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \
93 ARG_32BIT_ZALIMMRC, FLAGS_F }, \
94 { NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \
95 ARG_32BIT_ZARBLIMM, FLAGS_F }, \
96 { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \
97 ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \
98 { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
99 ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \
100 { NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
101 ARG_32BIT_RALIMMU6, FLAGS_F }, \
102 { NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \
103 ARG_32BIT_ZALIMMU6, FLAGS_F }, \
104 { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \
105 ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \
106 { NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \
107 ARG_32BIT_ZALIMMS12, FLAGS_F }, \
108 { NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \
109 ARG_32BIT_RALIMMLIMM, FLAGS_F }, \
110 { NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \
111 ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \
112 { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \
113 ARG_32BIT_ZALIMMLIMM, FLAGS_CCF },
114
115/* Extension instruction declarations. */
116EXTINSN2OP ("dsp_fp_flt2i", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 43)
117EXTINSN2OP ("dsp_fp_i2flt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 44)
118EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 45)
119
120EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 42)
121EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 43)
122
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