source: binutils/trunk/include/opcode/aarch64.h@ 1973

Last change on this file since 1973 was 1973, checked in by Silvan Scherrer, 8 years ago

binutils: update trunk to version 2.27
File size: 30.5 KB
Line 
1/* AArch64 assembler/disassembler support.
2
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
40#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
41#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
42#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
43#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
44#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
45#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
46#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
47#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
48#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
49#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
50#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
51#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
52#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
53#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
54
55/* Architectures are the sum of the base and extensions. */
56#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
57 AARCH64_FEATURE_FP \
58 | AARCH64_FEATURE_SIMD)
59#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
60 AARCH64_FEATURE_FP \
61 | AARCH64_FEATURE_SIMD \
62 | AARCH64_FEATURE_CRC \
63 | AARCH64_FEATURE_V8_1 \
64 | AARCH64_FEATURE_LSE \
65 | AARCH64_FEATURE_PAN \
66 | AARCH64_FEATURE_LOR \
67 | AARCH64_FEATURE_RDMA)
68#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
69 AARCH64_FEATURE_V8_2 \
70 | AARCH64_FEATURE_F16 \
71 | AARCH64_FEATURE_RAS \
72 | AARCH64_FEATURE_FP \
73 | AARCH64_FEATURE_SIMD \
74 | AARCH64_FEATURE_CRC \
75 | AARCH64_FEATURE_V8_1 \
76 | AARCH64_FEATURE_LSE \
77 | AARCH64_FEATURE_PAN \
78 | AARCH64_FEATURE_LOR \
79 | AARCH64_FEATURE_RDMA)
80
81#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
82#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
83
84/* CPU-specific features. */
85typedef unsigned long aarch64_feature_set;
86
87#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
88 (((CPU) & (FEAT)) != 0)
89
90#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
91 do \
92 { \
93 (TARG) = (F1) | (F2); \
94 } \
95 while (0)
96
97#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
98 do \
99 { \
100 (TARG) = (F1) &~ (F2); \
101 } \
102 while (0)
103
104#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
105
106#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
107 (((OPC) & (FEAT)) != 0)
108
109enum aarch64_operand_class
110{
111 AARCH64_OPND_CLASS_NIL,
112 AARCH64_OPND_CLASS_INT_REG,
113 AARCH64_OPND_CLASS_MODIFIED_REG,
114 AARCH64_OPND_CLASS_FP_REG,
115 AARCH64_OPND_CLASS_SIMD_REG,
116 AARCH64_OPND_CLASS_SIMD_ELEMENT,
117 AARCH64_OPND_CLASS_SISD_REG,
118 AARCH64_OPND_CLASS_SIMD_REGLIST,
119 AARCH64_OPND_CLASS_CP_REG,
120 AARCH64_OPND_CLASS_ADDRESS,
121 AARCH64_OPND_CLASS_IMMEDIATE,
122 AARCH64_OPND_CLASS_SYSTEM,
123 AARCH64_OPND_CLASS_COND,
124};
125
126/* Operand code that helps both parsing and coding.
127 Keep AARCH64_OPERANDS synced. */
128
129enum aarch64_opnd
130{
131 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
132
133 AARCH64_OPND_Rd, /* Integer register as destination. */
134 AARCH64_OPND_Rn, /* Integer register as source. */
135 AARCH64_OPND_Rm, /* Integer register as source. */
136 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
137 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
138 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
139 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
140 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
141
142 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
143 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
144 AARCH64_OPND_PAIRREG, /* Paired register operand. */
145 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
146 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
147
148 AARCH64_OPND_Fd, /* Floating-point Fd. */
149 AARCH64_OPND_Fn, /* Floating-point Fn. */
150 AARCH64_OPND_Fm, /* Floating-point Fm. */
151 AARCH64_OPND_Fa, /* Floating-point Fa. */
152 AARCH64_OPND_Ft, /* Floating-point Ft. */
153 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
154
155 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
156 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
157 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
158
159 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
160 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
161 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
162 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
163 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
164 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
165 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
166 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
167 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
168 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
169 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
170 structure to all lanes. */
171 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
172
173 AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
174 AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
175
176 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
177 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
178 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
179 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
180 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
181 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
182 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
183 (no encoding). */
184 AARCH64_OPND_IMM0, /* Immediate for #0. */
185 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
186 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
187 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
188 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
189 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
190 AARCH64_OPND_IMM, /* Immediate. */
191 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
192 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
193 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
194 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
195 AARCH64_OPND_BIT_NUM, /* Immediate. */
196 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
197 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
198 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
199 each condition flag. */
200
201 AARCH64_OPND_LIMM, /* Logical Immediate. */
202 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
203 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
204 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
205 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
206
207 AARCH64_OPND_COND, /* Standard condition as the last operand. */
208 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
209
210 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
211 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
212 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
213 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
214 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
215
216 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
217 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
218 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
219 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
220 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
221 negative or unaligned and there is
222 no writeback allowed. This operand code
223 is only used to support the programmer-
224 friendly feature of using LDR/STR as the
225 the mnemonic name for LDUR/STUR instructions
226 wherever there is no ambiguity. */
227 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
228 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
229 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
230
231 AARCH64_OPND_SYSREG, /* System register operand. */
232 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
233 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
234 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
235 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
236 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
237 AARCH64_OPND_BARRIER, /* Barrier operand. */
238 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
239 AARCH64_OPND_PRFOP, /* Prefetch operation. */
240 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
241};
242
243/* Qualifier constrains an operand. It either specifies a variant of an
244 operand type or limits values available to an operand type.
245
246 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
247
248enum aarch64_opnd_qualifier
249{
250 /* Indicating no further qualification on an operand. */
251 AARCH64_OPND_QLF_NIL,
252
253 /* Qualifying an operand which is a general purpose (integer) register;
254 indicating the operand data size or a specific register. */
255 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
256 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
257 AARCH64_OPND_QLF_WSP, /* WSP. */
258 AARCH64_OPND_QLF_SP, /* SP. */
259
260 /* Qualifying an operand which is a floating-point register, a SIMD
261 vector element or a SIMD vector element list; indicating operand data
262 size or the size of each SIMD vector element in the case of a SIMD
263 vector element list.
264 These qualifiers are also used to qualify an address operand to
265 indicate the size of data element a load/store instruction is
266 accessing.
267 They are also used for the immediate shift operand in e.g. SSHR. Such
268 a use is only for the ease of operand encoding/decoding and qualifier
269 sequence matching; such a use should not be applied widely; use the value
270 constraint qualifiers for immediate operands wherever possible. */
271 AARCH64_OPND_QLF_S_B,
272 AARCH64_OPND_QLF_S_H,
273 AARCH64_OPND_QLF_S_S,
274 AARCH64_OPND_QLF_S_D,
275 AARCH64_OPND_QLF_S_Q,
276
277 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
278 register list; indicating register shape.
279 They are also used for the immediate shift operand in e.g. SSHR. Such
280 a use is only for the ease of operand encoding/decoding and qualifier
281 sequence matching; such a use should not be applied widely; use the value
282 constraint qualifiers for immediate operands wherever possible. */
283 AARCH64_OPND_QLF_V_8B,
284 AARCH64_OPND_QLF_V_16B,
285 AARCH64_OPND_QLF_V_2H,
286 AARCH64_OPND_QLF_V_4H,
287 AARCH64_OPND_QLF_V_8H,
288 AARCH64_OPND_QLF_V_2S,
289 AARCH64_OPND_QLF_V_4S,
290 AARCH64_OPND_QLF_V_1D,
291 AARCH64_OPND_QLF_V_2D,
292 AARCH64_OPND_QLF_V_1Q,
293
294 /* Constraint on value. */
295 AARCH64_OPND_QLF_imm_0_7,
296 AARCH64_OPND_QLF_imm_0_15,
297 AARCH64_OPND_QLF_imm_0_31,
298 AARCH64_OPND_QLF_imm_0_63,
299 AARCH64_OPND_QLF_imm_1_32,
300 AARCH64_OPND_QLF_imm_1_64,
301
302 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
303 or shift-ones. */
304 AARCH64_OPND_QLF_LSL,
305 AARCH64_OPND_QLF_MSL,
306
307 /* Special qualifier helping retrieve qualifier information during the
308 decoding time (currently not in use). */
309 AARCH64_OPND_QLF_RETRIEVE,
310};
311
312
313/* Instruction class. */
314
315enum aarch64_insn_class
316{
317 addsub_carry,
318 addsub_ext,
319 addsub_imm,
320 addsub_shift,
321 asimdall,
322 asimddiff,
323 asimdelem,
324 asimdext,
325 asimdimm,
326 asimdins,
327 asimdmisc,
328 asimdperm,
329 asimdsame,
330 asimdshf,
331 asimdtbl,
332 asisddiff,
333 asisdelem,
334 asisdlse,
335 asisdlsep,
336 asisdlso,
337 asisdlsop,
338 asisdmisc,
339 asisdone,
340 asisdpair,
341 asisdsame,
342 asisdshf,
343 bitfield,
344 branch_imm,
345 branch_reg,
346 compbranch,
347 condbranch,
348 condcmp_imm,
349 condcmp_reg,
350 condsel,
351 cryptoaes,
352 cryptosha2,
353 cryptosha3,
354 dp_1src,
355 dp_2src,
356 dp_3src,
357 exception,
358 extract,
359 float2fix,
360 float2int,
361 floatccmp,
362 floatcmp,
363 floatdp1,
364 floatdp2,
365 floatdp3,
366 floatimm,
367 floatsel,
368 ldst_immpost,
369 ldst_immpre,
370 ldst_imm9, /* immpost or immpre */
371 ldst_pos,
372 ldst_regoff,
373 ldst_unpriv,
374 ldst_unscaled,
375 ldstexcl,
376 ldstnapair_offs,
377 ldstpair_off,
378 ldstpair_indexed,
379 loadlit,
380 log_imm,
381 log_shift,
382 lse_atomic,
383 movewide,
384 pcreladdr,
385 ic_system,
386 testbranch,
387};
388
389/* Opcode enumerators. */
390
391enum aarch64_op
392{
393 OP_NIL,
394 OP_STRB_POS,
395 OP_LDRB_POS,
396 OP_LDRSB_POS,
397 OP_STRH_POS,
398 OP_LDRH_POS,
399 OP_LDRSH_POS,
400 OP_STR_POS,
401 OP_LDR_POS,
402 OP_STRF_POS,
403 OP_LDRF_POS,
404 OP_LDRSW_POS,
405 OP_PRFM_POS,
406
407 OP_STURB,
408 OP_LDURB,
409 OP_LDURSB,
410 OP_STURH,
411 OP_LDURH,
412 OP_LDURSH,
413 OP_STUR,
414 OP_LDUR,
415 OP_STURV,
416 OP_LDURV,
417 OP_LDURSW,
418 OP_PRFUM,
419
420 OP_LDR_LIT,
421 OP_LDRV_LIT,
422 OP_LDRSW_LIT,
423 OP_PRFM_LIT,
424
425 OP_ADD,
426 OP_B,
427 OP_BL,
428
429 OP_MOVN,
430 OP_MOVZ,
431 OP_MOVK,
432
433 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
434 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
435 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
436
437 OP_MOV_V, /* MOV alias for moving vector register. */
438
439 OP_ASR_IMM,
440 OP_LSR_IMM,
441 OP_LSL_IMM,
442
443 OP_BIC,
444
445 OP_UBFX,
446 OP_BFXIL,
447 OP_SBFX,
448 OP_SBFIZ,
449 OP_BFI,
450 OP_BFC, /* ARMv8.2. */
451 OP_UBFIZ,
452 OP_UXTB,
453 OP_UXTH,
454 OP_UXTW,
455
456 OP_CINC,
457 OP_CINV,
458 OP_CNEG,
459 OP_CSET,
460 OP_CSETM,
461
462 OP_FCVT,
463 OP_FCVTN,
464 OP_FCVTN2,
465 OP_FCVTL,
466 OP_FCVTL2,
467 OP_FCVTXN_S, /* Scalar version. */
468
469 OP_ROR_IMM,
470
471 OP_SXTL,
472 OP_SXTL2,
473 OP_UXTL,
474 OP_UXTL2,
475
476 OP_TOTAL_NUM, /* Pseudo. */
477};
478
479/* Maximum number of operands an instruction can have. */
480#define AARCH64_MAX_OPND_NUM 6
481/* Maximum number of qualifier sequences an instruction can have. */
482#define AARCH64_MAX_QLF_SEQ_NUM 10
483/* Operand qualifier typedef; optimized for the size. */
484typedef unsigned char aarch64_opnd_qualifier_t;
485/* Operand qualifier sequence typedef. */
486typedef aarch64_opnd_qualifier_t \
487 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
488
489/* FIXME: improve the efficiency. */
490static inline bfd_boolean
491empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
492{
493 int i;
494 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
495 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
496 return FALSE;
497 return TRUE;
498}
499
500/* This structure holds information for a particular opcode. */
501
502struct aarch64_opcode
503{
504 /* The name of the mnemonic. */
505 const char *name;
506
507 /* The opcode itself. Those bits which will be filled in with
508 operands are zeroes. */
509 aarch64_insn opcode;
510
511 /* The opcode mask. This is used by the disassembler. This is a
512 mask containing ones indicating those bits which must match the
513 opcode field, and zeroes indicating those bits which need not
514 match (and are presumably filled in by operands). */
515 aarch64_insn mask;
516
517 /* Instruction class. */
518 enum aarch64_insn_class iclass;
519
520 /* Enumerator identifier. */
521 enum aarch64_op op;
522
523 /* Which architecture variant provides this instruction. */
524 const aarch64_feature_set *avariant;
525
526 /* An array of operand codes. Each code is an index into the
527 operand table. They appear in the order which the operands must
528 appear in assembly code, and are terminated by a zero. */
529 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
530
531 /* A list of operand qualifier code sequence. Each operand qualifier
532 code qualifies the corresponding operand code. Each operand
533 qualifier sequence specifies a valid opcode variant and related
534 constraint on operands. */
535 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
536
537 /* Flags providing information about this instruction */
538 uint32_t flags;
539
540 /* If non-NULL, a function to verify that a given instruction is valid. */
541 bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
542};
543
544typedef struct aarch64_opcode aarch64_opcode;
545
546/* Table describing all the AArch64 opcodes. */
547extern aarch64_opcode aarch64_opcode_table[];
548
549/* Opcode flags. */
550#define F_ALIAS (1 << 0)
551#define F_HAS_ALIAS (1 << 1)
552/* Disassembly preference priority 1-3 (the larger the higher). If nothing
553 is specified, it is the priority 0 by default, i.e. the lowest priority. */
554#define F_P1 (1 << 2)
555#define F_P2 (2 << 2)
556#define F_P3 (3 << 2)
557/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
558#define F_COND (1 << 4)
559/* Instruction has the field of 'sf'. */
560#define F_SF (1 << 5)
561/* Instruction has the field of 'size:Q'. */
562#define F_SIZEQ (1 << 6)
563/* Floating-point instruction has the field of 'type'. */
564#define F_FPTYPE (1 << 7)
565/* AdvSIMD scalar instruction has the field of 'size'. */
566#define F_SSIZE (1 << 8)
567/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
568#define F_T (1 << 9)
569/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
570#define F_GPRSIZE_IN_Q (1 << 10)
571/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
572#define F_LDS_SIZE (1 << 11)
573/* Optional operand; assume maximum of 1 operand can be optional. */
574#define F_OPD0_OPT (1 << 12)
575#define F_OPD1_OPT (2 << 12)
576#define F_OPD2_OPT (3 << 12)
577#define F_OPD3_OPT (4 << 12)
578#define F_OPD4_OPT (5 << 12)
579/* Default value for the optional operand when omitted from the assembly. */
580#define F_DEFAULT(X) (((X) & 0x1f) << 15)
581/* Instruction that is an alias of another instruction needs to be
582 encoded/decoded by converting it to/from the real form, followed by
583 the encoding/decoding according to the rules of the real opcode.
584 This compares to the direct coding using the alias's information.
585 N.B. this flag requires F_ALIAS to be used together. */
586#define F_CONV (1 << 20)
587/* Use together with F_ALIAS to indicate an alias opcode is a programmer
588 friendly pseudo instruction available only in the assembly code (thus will
589 not show up in the disassembly). */
590#define F_PSEUDO (1 << 21)
591/* Instruction has miscellaneous encoding/decoding rules. */
592#define F_MISC (1 << 22)
593/* Instruction has the field of 'N'; used in conjunction with F_SF. */
594#define F_N (1 << 23)
595/* Opcode dependent field. */
596#define F_OD(X) (((X) & 0x7) << 24)
597/* Instruction has the field of 'sz'. */
598#define F_LSE_SZ (1 << 27)
599/* Next bit is 28. */
600
601static inline bfd_boolean
602alias_opcode_p (const aarch64_opcode *opcode)
603{
604 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
605}
606
607static inline bfd_boolean
608opcode_has_alias (const aarch64_opcode *opcode)
609{
610 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
611}
612
613/* Priority for disassembling preference. */
614static inline int
615opcode_priority (const aarch64_opcode *opcode)
616{
617 return (opcode->flags >> 2) & 0x3;
618}
619
620static inline bfd_boolean
621pseudo_opcode_p (const aarch64_opcode *opcode)
622{
623 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
624}
625
626static inline bfd_boolean
627optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
628{
629 return (((opcode->flags >> 12) & 0x7) == idx + 1)
630 ? TRUE : FALSE;
631}
632
633static inline aarch64_insn
634get_optional_operand_default_value (const aarch64_opcode *opcode)
635{
636 return (opcode->flags >> 15) & 0x1f;
637}
638
639static inline unsigned int
640get_opcode_dependent_value (const aarch64_opcode *opcode)
641{
642 return (opcode->flags >> 24) & 0x7;
643}
644
645static inline bfd_boolean
646opcode_has_special_coder (const aarch64_opcode *opcode)
647{
648 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
649 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
650 : FALSE;
651}
652
653
654struct aarch64_name_value_pair
655{
656 const char * name;
657 aarch64_insn value;
658};
659
660extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
661extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
662extern const struct aarch64_name_value_pair aarch64_prfops [32];
663extern const struct aarch64_name_value_pair aarch64_hint_options [];
664
665typedef struct
666{
667 const char * name;
668 aarch64_insn value;
669 uint32_t flags;
670} aarch64_sys_reg;
671
672extern const aarch64_sys_reg aarch64_sys_regs [];
673extern const aarch64_sys_reg aarch64_pstatefields [];
674extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
675extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
676 const aarch64_sys_reg *);
677extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
678 const aarch64_sys_reg *);
679
680typedef struct
681{
682 const char *name;
683 uint32_t value;
684 uint32_t flags ;
685} aarch64_sys_ins_reg;
686
687extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
688extern bfd_boolean
689aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
690 const aarch64_sys_ins_reg *);
691
692extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
693extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
694extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
695extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
696
697/* Shift/extending operator kinds.
698 N.B. order is important; keep aarch64_operand_modifiers synced. */
699enum aarch64_modifier_kind
700{
701 AARCH64_MOD_NONE,
702 AARCH64_MOD_MSL,
703 AARCH64_MOD_ROR,
704 AARCH64_MOD_ASR,
705 AARCH64_MOD_LSR,
706 AARCH64_MOD_LSL,
707 AARCH64_MOD_UXTB,
708 AARCH64_MOD_UXTH,
709 AARCH64_MOD_UXTW,
710 AARCH64_MOD_UXTX,
711 AARCH64_MOD_SXTB,
712 AARCH64_MOD_SXTH,
713 AARCH64_MOD_SXTW,
714 AARCH64_MOD_SXTX,
715};
716
717bfd_boolean
718aarch64_extend_operator_p (enum aarch64_modifier_kind);
719
720enum aarch64_modifier_kind
721aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
722/* Condition. */
723
724typedef struct
725{
726 /* A list of names with the first one as the disassembly preference;
727 terminated by NULL if fewer than 3. */
728 const char *names[3];
729 aarch64_insn value;
730} aarch64_cond;
731
732extern const aarch64_cond aarch64_conds[16];
733
734const aarch64_cond* get_cond_from_value (aarch64_insn value);
735const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
736
737
738/* Structure representing an operand. */
739
740struct aarch64_opnd_info
741{
742 enum aarch64_opnd type;
743 aarch64_opnd_qualifier_t qualifier;
744 int idx;
745
746 union
747 {
748 struct
749 {
750 unsigned regno;
751 } reg;
752 struct
753 {
754 unsigned int regno;
755 int64_t index;
756 } reglane;
757 /* e.g. LVn. */
758 struct
759 {
760 unsigned first_regno : 5;
761 unsigned num_regs : 3;
762 /* 1 if it is a list of reg element. */
763 unsigned has_index : 1;
764 /* Lane index; valid only when has_index is 1. */
765 int64_t index;
766 } reglist;
767 /* e.g. immediate or pc relative address offset. */
768 struct
769 {
770 int64_t value;
771 unsigned is_fp : 1;
772 } imm;
773 /* e.g. address in STR (register offset). */
774 struct
775 {
776 unsigned base_regno;
777 struct
778 {
779 union
780 {
781 int imm;
782 unsigned regno;
783 };
784 unsigned is_reg;
785 } offset;
786 unsigned pcrel : 1; /* PC-relative. */
787 unsigned writeback : 1;
788 unsigned preind : 1; /* Pre-indexed. */
789 unsigned postind : 1; /* Post-indexed. */
790 } addr;
791 const aarch64_cond *cond;
792 /* The encoding of the system register. */
793 aarch64_insn sysreg;
794 /* The encoding of the PSTATE field. */
795 aarch64_insn pstatefield;
796 const aarch64_sys_ins_reg *sysins_op;
797 const struct aarch64_name_value_pair *barrier;
798 const struct aarch64_name_value_pair *hint_option;
799 const struct aarch64_name_value_pair *prfop;
800 };
801
802 /* Operand shifter; in use when the operand is a register offset address,
803 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
804 struct
805 {
806 enum aarch64_modifier_kind kind;
807 int amount;
808 unsigned operator_present: 1; /* Only valid during encoding. */
809 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
810 unsigned amount_present: 1;
811 } shifter;
812
813 unsigned skip:1; /* Operand is not completed if there is a fixup needed
814 to be done on it. In some (but not all) of these
815 cases, we need to tell libopcodes to skip the
816 constraint checking and the encoding for this
817 operand, so that the libopcodes can pick up the
818 right opcode before the operand is fixed-up. This
819 flag should only be used during the
820 assembling/encoding. */
821 unsigned present:1; /* Whether this operand is present in the assembly
822 line; not used during the disassembly. */
823};
824
825typedef struct aarch64_opnd_info aarch64_opnd_info;
826
827/* Structure representing an instruction.
828
829 It is used during both the assembling and disassembling. The assembler
830 fills an aarch64_inst after a successful parsing and then passes it to the
831 encoding routine to do the encoding. During the disassembling, the
832 disassembler calls the decoding routine to decode a binary instruction; on a
833 successful return, such a structure will be filled with information of the
834 instruction; then the disassembler uses the information to print out the
835 instruction. */
836
837struct aarch64_inst
838{
839 /* The value of the binary instruction. */
840 aarch64_insn value;
841
842 /* Corresponding opcode entry. */
843 const aarch64_opcode *opcode;
844
845 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
846 const aarch64_cond *cond;
847
848 /* Operands information. */
849 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
850};
851
852typedef struct aarch64_inst aarch64_inst;
853
854
855/* Diagnosis related declaration and interface. */
856
857/* Operand error kind enumerators.
858
859 AARCH64_OPDE_RECOVERABLE
860 Less severe error found during the parsing, very possibly because that
861 GAS has picked up a wrong instruction template for the parsing.
862
863 AARCH64_OPDE_SYNTAX_ERROR
864 General syntax error; it can be either a user error, or simply because
865 that GAS is trying a wrong instruction template.
866
867 AARCH64_OPDE_FATAL_SYNTAX_ERROR
868 Definitely a user syntax error.
869
870 AARCH64_OPDE_INVALID_VARIANT
871 No syntax error, but the operands are not a valid combination, e.g.
872 FMOV D0,S0
873
874 AARCH64_OPDE_OUT_OF_RANGE
875 Error about some immediate value out of a valid range.
876
877 AARCH64_OPDE_UNALIGNED
878 Error about some immediate value not properly aligned (i.e. not being a
879 multiple times of a certain value).
880
881 AARCH64_OPDE_REG_LIST
882 Error about the register list operand having unexpected number of
883 registers.
884
885 AARCH64_OPDE_OTHER_ERROR
886 Error of the highest severity and used for any severe issue that does not
887 fall into any of the above categories.
888
889 The enumerators are only interesting to GAS. They are declared here (in
890 libopcodes) because that some errors are detected (and then notified to GAS)
891 by libopcodes (rather than by GAS solely).
892
893 The first three errors are only deteced by GAS while the
894 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
895 only libopcodes has the information about the valid variants of each
896 instruction.
897
898 The enumerators have an increasing severity. This is helpful when there are
899 multiple instruction templates available for a given mnemonic name (e.g.
900 FMOV); this mechanism will help choose the most suitable template from which
901 the generated diagnostics can most closely describe the issues, if any. */
902
903enum aarch64_operand_error_kind
904{
905 AARCH64_OPDE_NIL,
906 AARCH64_OPDE_RECOVERABLE,
907 AARCH64_OPDE_SYNTAX_ERROR,
908 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
909 AARCH64_OPDE_INVALID_VARIANT,
910 AARCH64_OPDE_OUT_OF_RANGE,
911 AARCH64_OPDE_UNALIGNED,
912 AARCH64_OPDE_REG_LIST,
913 AARCH64_OPDE_OTHER_ERROR
914};
915
916/* N.B. GAS assumes that this structure work well with shallow copy. */
917struct aarch64_operand_error
918{
919 enum aarch64_operand_error_kind kind;
920 int index;
921 const char *error;
922 int data[3]; /* Some data for extra information. */
923};
924
925typedef struct aarch64_operand_error aarch64_operand_error;
926
927/* Encoding entrypoint. */
928
929extern int
930aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
931 aarch64_insn *, aarch64_opnd_qualifier_t *,
932 aarch64_operand_error *);
933
934extern const aarch64_opcode *
935aarch64_replace_opcode (struct aarch64_inst *,
936 const aarch64_opcode *);
937
938/* Given the opcode enumerator OP, return the pointer to the corresponding
939 opcode entry. */
940
941extern const aarch64_opcode *
942aarch64_get_opcode (enum aarch64_op);
943
944/* Generate the string representation of an operand. */
945extern void
946aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
947 const aarch64_opnd_info *, int, int *, bfd_vma *);
948
949/* Miscellaneous interface. */
950
951extern int
952aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
953
954extern aarch64_opnd_qualifier_t
955aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
956 const aarch64_opnd_qualifier_t, int);
957
958extern int
959aarch64_num_of_operands (const aarch64_opcode *);
960
961extern int
962aarch64_stack_pointer_p (const aarch64_opnd_info *);
963
964extern int
965aarch64_zero_register_p (const aarch64_opnd_info *);
966
967extern int
968aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
969
970/* Given an operand qualifier, return the expected data element size
971 of a qualified operand. */
972extern unsigned char
973aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
974
975extern enum aarch64_operand_class
976aarch64_get_operand_class (enum aarch64_opnd);
977
978extern const char *
979aarch64_get_operand_name (enum aarch64_opnd);
980
981extern const char *
982aarch64_get_operand_desc (enum aarch64_opnd);
983
984#ifdef DEBUG_AARCH64
985extern int debug_dump;
986
987extern void
988aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
989
990#define DEBUG_TRACE(M, ...) \
991 { \
992 if (debug_dump) \
993 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
994 }
995
996#define DEBUG_TRACE_IF(C, M, ...) \
997 { \
998 if (debug_dump && (C)) \
999 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1000 }
1001#else /* !DEBUG_AARCH64 */
1002#define DEBUG_TRACE(M, ...) ;
1003#define DEBUG_TRACE_IF(C, M, ...) ;
1004#endif /* DEBUG_AARCH64 */
1005
1006#ifdef __cplusplus
1007}
1008#endif
1009
1010#endif /* OPCODE_AARCH64_H */
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