source: GPL/trunk/alsa-kernel/pci/hda/hda_intel.c@ 598

Last change on this file since 598 was 598, checked in by David Azarewicz, 8 years ago

Merged/reintegrated v2 branch into trunk. Trunk is now v2
File size: 79.7 KB
RevLine 
[399]1/*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
[520]34 *
[399]35 */
36
37#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/dma-mapping.h>
43#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
47#include <linux/mutex.h>
[402]48#include <linux/reboot.h>
[399]49#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
[426]53
[399]54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
59#ifndef TARGET_OS2
60static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
62#else
[426]63static int bdl_pos_adj[SNDRV_CARDS] = {-1,-1,-1,-1,-1,-1,-1,-1};
64static int probe_mask[SNDRV_CARDS] = {-1,-1,-1,-1,-1,-1,-1,-1};
[399]65#endif
[426]66static int probe_only[SNDRV_CARDS];
[399]67static int single_cmd;
[598]68static int enable_msi = -1;
[464]69#ifdef CONFIG_SND_HDA_PATCH_LOADER
70static char *patch[SNDRV_CARDS];
71#endif
[598]72#ifdef CONFIG_SND_HDA_INPUT_BEEP
73static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
74 CONFIG_SND_HDA_INPUT_BEEP_MODE};
75#endif
[399]76
77module_param_array(index, int, NULL, 0444);
78MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
79module_param_array(id, charp, NULL, 0444);
80MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
81module_param_array(enable, bool, NULL, 0444);
82MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
83module_param_array(model, charp, NULL, 0444);
84MODULE_PARM_DESC(model, "Use the given board model.");
85module_param_array(position_fix, int, NULL, 0444);
[598]86MODULE_PARM_DESC(position_fix, "DMA pointer read method."
87 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
[399]88module_param_array(bdl_pos_adj, int, NULL, 0644);
89MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
90module_param_array(probe_mask, int, NULL, 0444);
91MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
[598]92module_param_array(probe_only, int, NULL, 0444);
[426]93MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
[399]94module_param(single_cmd, bool, 0444);
95MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
96 "(for debugging only).");
97module_param(enable_msi, int, 0444);
98MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
[464]99#ifdef CONFIG_SND_HDA_PATCH_LOADER
100module_param_array(patch, charp, NULL, 0444);
101MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
102#endif
[598]103#ifdef CONFIG_SND_HDA_INPUT_BEEP
104module_param_array(beep_mode, int, NULL, 0444);
105MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
106 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
107#endif
[399]108
109#ifdef CONFIG_SND_HDA_POWER_SAVE
[426]110static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
111module_param(power_save, int, 0644);
112MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
113 "(in second, 0 = disable).");
[399]114
115/* reset the HD-audio controller in power save mode.
116 * this may give more power-saving, but will take longer time to
117 * wake up.
118 */
119static int power_save_controller = 1;
120module_param(power_save_controller, bool, 0644);
121MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
122#endif
123
124MODULE_LICENSE("GPL");
125MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
126 "{Intel, ICH6M},"
127 "{Intel, ICH7},"
128 "{Intel, ESB2},"
129 "{Intel, ICH8},"
130 "{Intel, ICH9},"
131 "{Intel, ICH10},"
132 "{Intel, PCH},"
[598]133 "{Intel, CPT},"
134 "{Intel, PBG},"
[399]135 "{Intel, SCH},"
136 "{ATI, SB450},"
137 "{ATI, SB600},"
138 "{ATI, RS600},"
139 "{ATI, RS690},"
140 "{ATI, RS780},"
141 "{ATI, R600},"
142 "{ATI, RV630},"
143 "{ATI, RV610},"
144 "{ATI, RV670},"
145 "{ATI, RV635},"
146 "{ATI, RV620},"
147 "{ATI, RV770},"
148 "{VIA, VT8251},"
149 "{VIA, VT8237A},"
150 "{SiS, SIS966},"
151 "{ULI, M5461}}");
152MODULE_DESCRIPTION("Intel HDA driver");
153
[464]154#ifdef CONFIG_SND_VERBOSE_PRINTK
155#define SFX /* nop */
156#else
[399]157#define SFX "hda-intel: "
[464]158#endif
[399]159
160/*
161 * registers
162 */
163#define ICH6_REG_GCAP 0x00
[464]164#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
165#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
166#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
167#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
168#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
[399]169#define ICH6_REG_VMIN 0x02
170#define ICH6_REG_VMAJ 0x03
171#define ICH6_REG_OUTPAY 0x04
172#define ICH6_REG_INPAY 0x06
173#define ICH6_REG_GCTL 0x08
[464]174#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
175#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
176#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
[399]177#define ICH6_REG_WAKEEN 0x0c
178#define ICH6_REG_STATESTS 0x0e
179#define ICH6_REG_GSTS 0x10
[464]180#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
[399]181#define ICH6_REG_INTCTL 0x20
182#define ICH6_REG_INTSTS 0x24
[598]183#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
[399]184#define ICH6_REG_SYNC 0x34
185#define ICH6_REG_CORBLBASE 0x40
186#define ICH6_REG_CORBUBASE 0x44
187#define ICH6_REG_CORBWP 0x48
[464]188#define ICH6_REG_CORBRP 0x4a
189#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
[399]190#define ICH6_REG_CORBCTL 0x4c
[464]191#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
192#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
[399]193#define ICH6_REG_CORBSTS 0x4d
[464]194#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
[399]195#define ICH6_REG_CORBSIZE 0x4e
196
197#define ICH6_REG_RIRBLBASE 0x50
198#define ICH6_REG_RIRBUBASE 0x54
199#define ICH6_REG_RIRBWP 0x58
[464]200#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
[399]201#define ICH6_REG_RINTCNT 0x5a
202#define ICH6_REG_RIRBCTL 0x5c
[464]203#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
204#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
205#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
[399]206#define ICH6_REG_RIRBSTS 0x5d
[464]207#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
208#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
[399]209#define ICH6_REG_RIRBSIZE 0x5e
210
211#define ICH6_REG_IC 0x60
212#define ICH6_REG_IR 0x64
213#define ICH6_REG_IRS 0x68
214#define ICH6_IRS_VALID (1<<1)
215#define ICH6_IRS_BUSY (1<<0)
216
217#define ICH6_REG_DPLBASE 0x70
218#define ICH6_REG_DPUBASE 0x74
219#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
220
221/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
222enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
223
224/* stream register offsets from stream base */
225#define ICH6_REG_SD_CTL 0x00
226#define ICH6_REG_SD_STS 0x03
227#define ICH6_REG_SD_LPIB 0x04
228#define ICH6_REG_SD_CBL 0x08
229#define ICH6_REG_SD_LVI 0x0c
230#define ICH6_REG_SD_FIFOW 0x0e
231#define ICH6_REG_SD_FIFOSIZE 0x10
232#define ICH6_REG_SD_FORMAT 0x12
233#define ICH6_REG_SD_BDLPL 0x18
234#define ICH6_REG_SD_BDLPU 0x1c
235
236/* PCI space */
237#define ICH6_PCIREG_TCSEL 0x44
238
239/*
240 * other constants
241 */
242
243/* max number of SDs */
244/* ICH, ATI and VIA have 4 playback and 4 capture */
245#define ICH6_NUM_CAPTURE 4
246#define ICH6_NUM_PLAYBACK 4
247
248/* ULI has 6 playback and 5 capture */
249#define ULI_NUM_CAPTURE 5
250#define ULI_NUM_PLAYBACK 6
251
252/* ATI HDMI has 1 playback and 0 capture */
253#define ATIHDMI_NUM_CAPTURE 0
254#define ATIHDMI_NUM_PLAYBACK 1
255
256/* TERA has 4 playback and 3 capture */
257#define TERA_NUM_CAPTURE 3
258#define TERA_NUM_PLAYBACK 4
259
260/* this number is statically defined for simplicity */
261#define MAX_AZX_DEV 16
262
263/* max number of fragments - we may use more if allocating more pages for BDL */
264#define BDL_SIZE 4096
265#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
266#define AZX_MAX_FRAG 32
267/* max buffer size - no h/w limit, you can increase as you like */
268#define AZX_MAX_BUF_SIZE (1024*1024*1024)
269
270/* RIRB int mask: overrun[2], response[0] */
271#define RIRB_INT_RESPONSE 0x01
272#define RIRB_INT_OVERRUN 0x04
273#define RIRB_INT_MASK 0x05
274
275/* STATESTS int mask: S3,SD2,SD1,SD0 */
[598]276#define AZX_MAX_CODECS 8
277#define AZX_DEFAULT_CODECS 4
[464]278#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
[399]279
280/* SD_CTL bits */
281#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
282#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
283#define SD_CTL_STRIPE (3 << 16) /* stripe control */
284#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
285#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
286#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
287#define SD_CTL_STREAM_TAG_SHIFT 20
288
289/* SD_CTL and SD_STS */
290#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
291#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
292#define SD_INT_COMPLETE 0x04 /* completion interrupt */
293#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
294 SD_INT_COMPLETE)
295
296/* SD_STS */
297#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
298
299/* INTCTL and INTSTS */
300#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
301#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
302#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
303
304/* below are so far hardcoded - should read registers in future */
305#define ICH6_MAX_CORB_ENTRIES 256
306#define ICH6_MAX_RIRB_ENTRIES 256
307
308/* position fix mode */
309enum {
310 POS_FIX_AUTO,
311 POS_FIX_LPIB,
312 POS_FIX_POSBUF,
[598]313 POS_FIX_VIACOMBO,
[399]314};
315
316/* Defines for ATI HD Audio support in SB450 south bridge */
317#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
318#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
319
320/* Defines for Nvidia HDA support */
321#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
322#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
323#define NVIDIA_HDA_ISTRM_COH 0x4d
324#define NVIDIA_HDA_OSTRM_COH 0x4c
325#define NVIDIA_HDA_ENABLE_COHBIT 0x01
326
327/* Defines for Intel SCH HDA snoop control */
328#define INTEL_SCH_HDA_DEVC 0x78
329#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
330
331/* Define IN stream 0 FIFO size offset in VIA controller */
332#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
333/* Define VIA HD Audio Device ID*/
334#define VIA_HDAC_DEVICE_ID 0x3288
335
[426]336/* HD Audio class code */
337#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
[399]338
339/*
340 */
341
342struct azx_dev {
343 struct snd_dma_buffer bdl; /* BDL buffer */
344#ifdef TARGET_OS2
345 volatile u32 *posbuf; /* position buffer pointer */
346#else
347 u32 *posbuf; /* position buffer pointer */
348#endif
[426]349
[399]350 unsigned int bufsize; /* size of the play buffer in bytes */
351 unsigned int period_bytes; /* size of the period in bytes */
352 unsigned int frags; /* number for period in the play buffer */
353 unsigned int fifo_size; /* FIFO size */
[598]354 unsigned long start_wallclk; /* start + minimum wallclk */
355 unsigned long period_wallclk; /* wallclk for period */
[399]356
357#ifdef TARGET_OS2
358 volatile void __iomem *sd_addr; /* stream descriptor pointer */
[520]359#else
[399]360 void __iomem *sd_addr; /* stream descriptor pointer */
361#endif
362
363 u32 sd_int_sta_mask; /* stream int status mask */
364
365 /* pcm support */
366 struct snd_pcm_substream *substream; /* assigned substream,
367 * set in PCM open
368 */
369 unsigned int format_val; /* format value to be set in the
370 * controller and the codec
371 */
372 unsigned char stream_tag; /* assigned stream */
373 unsigned char index; /* stream index */
[598]374 int device; /* last device number assigned to */
[399]375
376 unsigned int opened :1;
377 unsigned int running :1;
378 unsigned int irq_pending :1;
379 /*
380 * For VIA:
381 * A flag to ensure DMA position is 0
382 * when link position is not greater than FIFO size
383 */
384 unsigned int insufficient :1;
385};
386
387/* CORB/RIRB */
388struct azx_rb {
389#ifdef TARGET_OS2
390 volatile u32 *buf; /* CORB/RIRB buffer */
391#else
392 u32 *buf; /* CORB/RIRB buffer */
393#endif
394 /* Each CORB entry is 4byte, RIRB is 8byte
395 */
396 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
397 /* for RIRB */
398 unsigned short rp, wp; /* read/write pointers */
[464]399 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
400 u32 res[AZX_MAX_CODECS]; /* last read value */
[399]401};
402
403struct azx {
404 struct snd_card *card;
405 struct pci_dev *pci;
406 int dev_index;
407
408 /* chip type specific */
409 int driver_type;
410 int playback_streams;
411 int playback_index_offset;
412 int capture_streams;
413 int capture_index_offset;
414 int num_streams;
415
416 /* pci resources */
417 unsigned long addr;
418#ifdef TARGET_OS2
419 volatile void __iomem *remap_addr;
420#else /* !TARGET_OS2 */
421 void __iomem *remap_addr;
422#endif /* !TARGET_OS2 */
423 int irq;
424
425 /* locks */
426 spinlock_t reg_lock;
427 struct mutex open_mutex;
428
429 /* streams (x num_streams) */
430 struct azx_dev *azx_dev;
431
432 /* PCM */
[598]433 struct snd_pcm *pcm[HDA_MAX_PCMS];
[399]434
435 /* HD codec */
436 unsigned short codec_mask;
[426]437 int codec_probe_mask; /* copied from probe_mask option */
[399]438 struct hda_bus *bus;
[598]439 unsigned int beep_mode;
[399]440
441 /* CORB/RIRB */
442 struct azx_rb corb;
443 struct azx_rb rirb;
444
445 /* CORB/RIRB and position buffers */
446 struct snd_dma_buffer rb;
447 struct snd_dma_buffer posbuf;
448
449 /* flags */
[598]450 int position_fix[2]; /* for both playback/capture streams */
451 int poll_count;
[399]452 unsigned int running :1;
453 unsigned int initialized :1;
454 unsigned int single_cmd :1;
455 unsigned int polling_mode :1;
456 unsigned int msi :1;
457 unsigned int irq_pending_warned :1;
[402]458 unsigned int probing :1; /* codec probing phase */
[399]459
460 /* for debugging */
[464]461 unsigned int last_cmd[AZX_MAX_CODECS];
[399]462
463 /* for pending irqs */
464 struct work_struct irq_pending_work;
[402]465
466 /* reboot notifier (for mysterious hangup problem at power-down) */
467 struct notifier_block reboot_notifier;
[399]468};
469
470/* driver types */
471enum {
472 AZX_DRIVER_ICH,
[598]473 AZX_DRIVER_PCH,
[399]474 AZX_DRIVER_SCH,
475 AZX_DRIVER_ATI,
476 AZX_DRIVER_ATIHDMI,
477 AZX_DRIVER_VIA,
478 AZX_DRIVER_SIS,
479 AZX_DRIVER_ULI,
480 AZX_DRIVER_NVIDIA,
481 AZX_DRIVER_TERA,
[598]482 AZX_DRIVER_CTX,
[426]483 AZX_DRIVER_GENERIC,
[399]484 AZX_NUM_DRIVERS, /* keep this as last entry */
485};
486
487static char *driver_short_names[] __devinitdata = {
488 [AZX_DRIVER_ICH] = "HDA Intel",
[598]489 [AZX_DRIVER_PCH] = "HDA Intel PCH",
[399]490 [AZX_DRIVER_SCH] = "HDA Intel MID",
491 [AZX_DRIVER_ATI] = "HDA ATI SB",
492 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
493 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
494 [AZX_DRIVER_SIS] = "HDA SIS966",
495 [AZX_DRIVER_ULI] = "HDA ULI M5461",
496 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
[520]497 [AZX_DRIVER_TERA] = "HDA Teradici",
[598]498 [AZX_DRIVER_CTX] = "HDA Creative",
[426]499 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
[399]500};
501
502/*
503 * macros for easy use
504 */
505#define azx_writel(chip,reg,value) \
506 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
507#define azx_readl(chip,reg) \
508 readl((chip)->remap_addr + ICH6_REG_##reg)
509#define azx_writew(chip,reg,value) \
510 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
511#define azx_readw(chip,reg) \
512 readw((chip)->remap_addr + ICH6_REG_##reg)
513#define azx_writeb(chip,reg,value) \
514 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
515#define azx_readb(chip,reg) \
516 readb((chip)->remap_addr + ICH6_REG_##reg)
517
518#define azx_sd_writel(dev,reg,value) \
519 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
520#define azx_sd_readl(dev,reg) \
521 readl((dev)->sd_addr + ICH6_REG_##reg)
522#define azx_sd_writew(dev,reg,value) \
523 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
524#define azx_sd_readw(dev,reg) \
525 readw((dev)->sd_addr + ICH6_REG_##reg)
526#define azx_sd_writeb(dev,reg,value) \
527 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
528#define azx_sd_readb(dev,reg) \
529 readb((dev)->sd_addr + ICH6_REG_##reg)
530
531/* for pcm support */
532#define get_azx_dev(substream) (substream->runtime->private_data)
533
534static int azx_acquire_irq(struct azx *chip, int do_disconnect);
[598]535static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
[399]536/*
537 * Interface for HD codec
538 */
539
540/*
541 * CORB / RIRB interface
542 */
543static int azx_alloc_cmd_io(struct azx *chip)
544{
545 int err;
546
547 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
548 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
549 snd_dma_pci_data(chip->pci),
550 PAGE_SIZE, &chip->rb);
551 if (err < 0) {
552 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
553 return err;
554 }
555 return 0;
556}
557
558static void azx_init_cmd_io(struct azx *chip)
559{
[464]560 spin_lock_irq(&chip->reg_lock);
[399]561 /* CORB set up */
562 chip->corb.addr = chip->rb.addr;
563 chip->corb.buf = (u32 *)chip->rb.area;
564 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
565 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
566
567 /* set the corb size to 256 entries (ULI requires explicitly) */
568 azx_writeb(chip, CORBSIZE, 0x02);
569 /* set the corb write pointer to 0 */
570 azx_writew(chip, CORBWP, 0);
571 /* reset the corb hw read pointer */
[464]572 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
[399]573 /* enable corb dma */
[464]574 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
[399]575
576 /* RIRB set up */
577 chip->rirb.addr = chip->rb.addr + 2048;
578 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
[464]579 chip->rirb.wp = chip->rirb.rp = 0;
580 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
[399]581 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
582 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
583
584 /* set the rirb size to 256 entries (ULI requires explicitly) */
585 azx_writeb(chip, RIRBSIZE, 0x02);
586 /* reset the rirb hw write pointer */
[464]587 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
[399]588 /* set N=1, get RIRB response interrupt for new entry */
[598]589 if (chip->driver_type == AZX_DRIVER_CTX)
590 azx_writew(chip, RINTCNT, 0xc0);
591 else
592 azx_writew(chip, RINTCNT, 1);
[399]593 /* enable rirb dma and response irq */
594 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
[464]595 spin_unlock_irq(&chip->reg_lock);
[399]596}
597
598static void azx_free_cmd_io(struct azx *chip)
599{
[464]600 spin_lock_irq(&chip->reg_lock);
[399]601 /* disable ringbuffer DMAs */
602 azx_writeb(chip, RIRBCTL, 0);
603 azx_writeb(chip, CORBCTL, 0);
[464]604 spin_unlock_irq(&chip->reg_lock);
[399]605}
606
[464]607static unsigned int azx_command_addr(u32 cmd)
608{
609 unsigned int addr = cmd >> 28;
610
611 if (addr >= AZX_MAX_CODECS) {
612 snd_BUG();
613 addr = 0;
614 }
615
616 return addr;
617}
618
619static unsigned int azx_response_addr(u32 res)
620{
621 unsigned int addr = res & 0xf;
622
623 if (addr >= AZX_MAX_CODECS) {
624 snd_BUG();
625 addr = 0;
626 }
627
628 return addr;
629}
630
[399]631/* send a command */
[402]632static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
[399]633{
[402]634 struct azx *chip = bus->private_data;
[464]635 unsigned int addr = azx_command_addr(val);
[399]636 unsigned int wp;
637
[464]638 spin_lock_irq(&chip->reg_lock);
639
[399]640 /* add command to corb */
641 wp = azx_readb(chip, CORBWP);
642 wp++;
643 wp %= ICH6_MAX_CORB_ENTRIES;
644
[464]645 chip->rirb.cmds[addr]++;
[399]646 chip->corb.buf[wp] = cpu_to_le32(val);
647 azx_writel(chip, CORBWP, wp);
[464]648
[399]649 spin_unlock_irq(&chip->reg_lock);
650
651 return 0;
652}
653
654#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
655
656/* retrieve RIRB entry - called from interrupt handler */
657static void azx_update_rirb(struct azx *chip)
658{
659 unsigned int rp, wp;
[464]660 unsigned int addr;
[399]661 u32 res, res_ex;
662
663 wp = azx_readb(chip, RIRBWP);
664 if (wp == chip->rirb.wp)
665 return;
666 chip->rirb.wp = wp;
[464]667
[399]668 while (chip->rirb.rp != wp) {
669 chip->rirb.rp++;
670 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
671
672 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
673 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
674 res = le32_to_cpu(chip->rirb.buf[rp]);
[464]675 addr = azx_response_addr(res_ex);
[399]676 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
677 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
[464]678 else if (chip->rirb.cmds[addr]) {
679 chip->rirb.res[addr] = res;
[399]680 smp_wmb();
[464]681 chip->rirb.cmds[addr]--;
682 } else
683 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
684 "last cmd=%#08x\n",
685 res, res_ex,
686 chip->last_cmd[addr]);
[399]687 }
688}
689
690/* receive a response */
[464]691static unsigned int azx_rirb_get_response(struct hda_bus *bus,
692 unsigned int addr)
[399]693{
[402]694 struct azx *chip = bus->private_data;
[399]695 unsigned long timeout;
[434]696#ifdef TARGET_OS2
697 int count = 0;
698#endif
[598]699 int do_poll = 0;
[399]700
701 again:
702 timeout = jiffies + msecs_to_jiffies(1000);
[551]703 for ( ; ; ) {
[598]704 if (chip->polling_mode || do_poll) {
[399]705 spin_lock_irq(&chip->reg_lock);
706 azx_update_rirb(chip);
707 spin_unlock_irq(&chip->reg_lock);
708 }
[464]709 if (!chip->rirb.cmds[addr]) {
[399]710 smp_rmb();
[464]711 bus->rirb_error = 0;
[598]712
713 if (!do_poll)
714 chip->poll_count = 0;
[464]715 return chip->rirb.res[addr]; /* the last value */
[399]716 }
717 if (time_after(jiffies, timeout))
718 break;
[434]719#ifdef TARGET_OS2
720 if (count >= 5000) /* Hack on OS/2 to stop infinite loop as jiffies sometimes don't increment */
721 break;
722#endif
[402]723 if (bus->needs_damn_long_delay)
[399]724 msleep(2); /* temporary workaround */
725 else {
726 udelay(10);
727 cond_resched();
728 }
[434]729#ifdef TARGET_OS2
730 count++;
731#endif
[399]732 }
[598]733
734 if (!chip->polling_mode && chip->poll_count < 2) {
735 snd_printdd(SFX "azx_get_response timeout, "
736 "polling the codec once: last cmd=0x%08x\n",
737 chip->last_cmd[addr]);
738 do_poll = 1;
739 chip->poll_count++;
740 goto again;
741 }
742
743
744 if (!chip->polling_mode) {
745 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
746 "switching to polling mode: last cmd=0x%08x\n",
747 chip->last_cmd[addr]);
748 chip->polling_mode = 1;
749 goto again;
750 }
[434]751#ifdef TARGET_OS2
[551]752 if (count >= 5000) {
[434]753 snd_printk(KERN_WARNING "hda_intel: count >= 5000, aborting loop in azx_rirb_get_response\n");
[551]754 }
[434]755#endif
[399]756 if (chip->msi) {
[464]757 snd_printk(KERN_WARNING SFX "No response from codec, "
758 "disabling MSI: last cmd=0x%08x\n",
759 chip->last_cmd[addr]);
[399]760 free_irq(chip->irq, chip);
761 chip->irq = -1;
762 pci_disable_msi(chip->pci);
763 chip->msi = 0;
[464]764 if (azx_acquire_irq(chip, 1) < 0) {
765 bus->rirb_error = 1;
[399]766 return -1;
[464]767 }
[399]768 goto again;
769 }
770
[402]771 if (chip->probing) {
772 /* If this critical timeout happens during the codec probing
773 * phase, this is likely an access to a non-existing codec
774 * slot. Better to return an error and reset the system.
775 */
776 return -1;
777 }
778
[464]779 /* a fatal communication error; need either to reset or to fallback
780 * to the single_cmd mode
781 */
782 bus->rirb_error = 1;
783 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
784 bus->response_reset = 1;
785 return -1; /* give a chance to retry */
786 }
787
[399]788 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
789 "switching to single_cmd mode: last cmd=0x%08x\n",
[464]790 chip->last_cmd[addr]);
[399]791 chip->single_cmd = 1;
[464]792 bus->response_reset = 0;
[598]793 /* release CORB/RIRB */
[399]794 azx_free_cmd_io(chip);
[598]795 /* disable unsolicited responses */
796 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
[399]797 return -1;
798}
799
800/*
801 * Use the single immediate command instead of CORB/RIRB for simplicity
802 *
803 * Note: according to Intel, this is not preferred use. The command was
804 * intended for the BIOS only, and may get confused with unsolicited
805 * responses. So, we shouldn't use it for normal operation from the
806 * driver.
807 * I left the codes, however, for debugging/testing purposes.
808 */
809
[464]810/* receive a response */
811static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
812{
813 int timeout = 50;
814
815 while (timeout--) {
816 /* check IRV busy bit */
817 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
818 /* reuse rirb.res as the response return value */
819 chip->rirb.res[addr] = azx_readl(chip, IR);
820 return 0;
821 }
822 udelay(1);
823 }
824 if (printk_ratelimit())
825 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
826 azx_readw(chip, IRS));
827 chip->rirb.res[addr] = -1;
828 return -EIO;
829}
830
[399]831/* send a command */
[402]832static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
[399]833{
[402]834 struct azx *chip = bus->private_data;
[464]835 unsigned int addr = azx_command_addr(val);
[399]836 int timeout = 50;
837
[464]838 bus->rirb_error = 0;
[399]839 while (timeout--) {
840 /* check ICB busy bit */
841 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
842 /* Clear IRV valid bit */
843 azx_writew(chip, IRS, azx_readw(chip, IRS) |
844 ICH6_IRS_VALID);
845 azx_writel(chip, IC, val);
846 azx_writew(chip, IRS, azx_readw(chip, IRS) |
847 ICH6_IRS_BUSY);
[464]848 return azx_single_wait_for_response(chip, addr);
[399]849 }
850 udelay(1);
851 }
852 if (printk_ratelimit())
853 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
854 azx_readw(chip, IRS), val);
855 return -EIO;
856}
857
858/* receive a response */
[464]859static unsigned int azx_single_get_response(struct hda_bus *bus,
860 unsigned int addr)
[399]861{
[402]862 struct azx *chip = bus->private_data;
[464]863 return chip->rirb.res[addr];
[399]864}
865
866/*
867 * The below are the main callbacks from hda_codec.
868 *
869 * They are just the skeleton to call sub-callbacks according to the
870 * current setting of chip->single_cmd.
871 */
872
873/* send a command */
[402]874static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
[399]875{
[402]876 struct azx *chip = bus->private_data;
[399]877
[464]878 chip->last_cmd[azx_command_addr(val)] = val;
[399]879 if (chip->single_cmd)
[402]880 return azx_single_send_cmd(bus, val);
[399]881 else
[402]882 return azx_corb_send_cmd(bus, val);
[399]883}
884
885/* get a response */
[464]886static unsigned int azx_get_response(struct hda_bus *bus,
887 unsigned int addr)
[399]888{
[402]889 struct azx *chip = bus->private_data;
[399]890 if (chip->single_cmd)
[464]891 return azx_single_get_response(bus, addr);
[399]892 else
[464]893 return azx_rirb_get_response(bus, addr);
[399]894}
895
896#ifdef CONFIG_SND_HDA_POWER_SAVE
[402]897static void azx_power_notify(struct hda_bus *bus);
[399]898#endif
899
900/* reset codec link */
[598]901static int azx_reset(struct azx *chip, int full_reset)
[399]902{
903 int count;
904
[598]905 if (!full_reset)
906 goto __skip;
907
[399]908 /* clear STATESTS */
909 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
910
911 /* reset controller */
912 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
913
914 count = 50;
915 while (azx_readb(chip, GCTL) && --count)
916 msleep(1);
917
918 /* delay for >= 100us for codec PLL to settle per spec
919 * Rev 0.9 section 5.5.1
920 */
921 msleep(1);
922
923 /* Bring controller out of reset */
924 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
925
926 count = 50;
927 while (!azx_readb(chip, GCTL) && --count)
928 msleep(1);
929
930 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
931 msleep(1);
932
[598]933 __skip:
[399]934 /* check to see if controller is ready */
935 if (!azx_readb(chip, GCTL)) {
[464]936 snd_printd(SFX "azx_reset: controller not ready!\n");
[399]937 return -EBUSY;
938 }
939
940 /* Accept unsolicited responses */
[598]941 if (!chip->single_cmd)
942 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
943 ICH6_GCTL_UNSOL);
[399]944
945 /* detect codecs */
946 if (!chip->codec_mask) {
947 chip->codec_mask = azx_readw(chip, STATESTS);
[464]948 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
[399]949 }
950
951 return 0;
952}
953
954
955/*
956 * Lowlevel interface
[520]957 */
[399]958
959/* enable interrupts */
960static void azx_int_enable(struct azx *chip)
961{
962 /* enable controller CIE and GIE */
963 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
964 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
965}
966
967/* disable interrupts */
968static void azx_int_disable(struct azx *chip)
969{
970 int i;
971
972 /* disable interrupts in stream descriptor */
973 for (i = 0; i < chip->num_streams; i++) {
974 struct azx_dev *azx_dev = &chip->azx_dev[i];
975 azx_sd_writeb(azx_dev, SD_CTL,
976 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
977 }
978
979 /* disable SIE for all streams */
980 azx_writeb(chip, INTCTL, 0);
981
982 /* disable controller CIE and GIE */
983 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
984 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
985}
986
987/* clear interrupts */
988static void azx_int_clear(struct azx *chip)
989{
990 int i;
991
992 /* clear stream status */
993 for (i = 0; i < chip->num_streams; i++) {
994 struct azx_dev *azx_dev = &chip->azx_dev[i];
995 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
996 }
997
998 /* clear STATESTS */
999 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1000
1001 /* clear rirb status */
1002 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1003
1004 /* clear int status */
1005 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1006}
1007
1008/* start a stream */
1009static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1010{
1011 /*
1012 * Before stream start, initialize parameter
1013 */
1014 azx_dev->insufficient = 1;
1015
1016 /* enable SIE */
[598]1017 azx_writel(chip, INTCTL,
1018 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
[399]1019 /* set DMA start and interrupt mask */
1020 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1021 SD_CTL_DMA_START | SD_INT_MASK);
1022}
1023
[426]1024/* stop DMA */
1025static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
[399]1026{
1027 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1028 ~(SD_CTL_DMA_START | SD_INT_MASK));
1029 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
[426]1030}
1031
1032/* stop a stream */
1033static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1034{
1035 azx_stream_clear(chip, azx_dev);
[399]1036 /* disable SIE */
[598]1037 azx_writel(chip, INTCTL,
1038 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
[399]1039}
1040
1041
1042/*
1043 * reset and start the controller registers
1044 */
[598]1045static void azx_init_chip(struct azx *chip, int full_reset)
[399]1046{
1047 if (chip->initialized)
1048 return;
1049
1050 /* reset controller */
[598]1051 azx_reset(chip, full_reset);
[399]1052
1053 /* initialize interrupts */
1054 azx_int_clear(chip);
1055 azx_int_enable(chip);
1056
1057 /* initialize the codec command I/O */
[598]1058 if (!chip->single_cmd)
1059 azx_init_cmd_io(chip);
[399]1060
1061 /* program the position buffer */
1062 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1063 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1064
1065 chip->initialized = 1;
1066}
1067
1068/*
1069 * initialize the PCI registers
1070 */
1071/* update bits in a PCI register byte */
1072static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1073 unsigned char mask, unsigned char val)
1074{
1075 unsigned char data;
1076
1077 pci_read_config_byte(pci, reg, &data);
1078 data &= ~mask;
1079 data |= (val & mask);
1080 pci_write_config_byte(pci, reg, data);
1081}
1082
1083static void azx_init_pci(struct azx *chip)
1084{
1085 unsigned short snoop;
1086
1087 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1088 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1089 * Ensuring these bits are 0 clears playback static on some HD Audio
1090 * codecs
1091 */
1092 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1093
1094 switch (chip->driver_type) {
1095 case AZX_DRIVER_ATI:
1096 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1097 update_pci_byte(chip->pci,
[520]1098 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
[399]1099 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1100 break;
1101 case AZX_DRIVER_NVIDIA:
1102 /* For NVIDIA HDA, enable snoop */
1103 update_pci_byte(chip->pci,
1104 NVIDIA_HDA_TRANSREG_ADDR,
1105 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1106 update_pci_byte(chip->pci,
1107 NVIDIA_HDA_ISTRM_COH,
1108 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1109 update_pci_byte(chip->pci,
1110 NVIDIA_HDA_OSTRM_COH,
1111 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1112 break;
1113 case AZX_DRIVER_SCH:
[598]1114 case AZX_DRIVER_PCH:
[399]1115 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1116 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
[464]1117 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
[399]1118 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1119 pci_read_config_word(chip->pci,
1120 INTEL_SCH_HDA_DEVC, &snoop);
[464]1121 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1122 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
[399]1123 ? "Failed" : "OK");
1124 }
1125 break;
1126
1127 }
1128}
1129
1130
1131static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1132
1133/*
1134 * interrupt handler
1135 */
1136static irqreturn_t azx_interrupt(int irq, void *dev_id)
1137{
1138 struct azx *chip = dev_id;
1139 struct azx_dev *azx_dev;
1140 u32 status;
[598]1141 u8 sd_status;
[426]1142 int i, ok;
[399]1143
1144 spin_lock(&chip->reg_lock);
1145
1146 status = azx_readl(chip, INTSTS);
1147 if (status == 0) {
1148 spin_unlock(&chip->reg_lock);
1149 return IRQ_NONE;
1150 }
1151
1152 for (i = 0; i < chip->num_streams; i++) {
1153 azx_dev = &chip->azx_dev[i];
1154 if (status & azx_dev->sd_int_sta_mask) {
[598]1155 sd_status = azx_sd_readb(azx_dev, SD_STS);
[399]1156 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
[598]1157 if (!azx_dev->substream || !azx_dev->running ||
1158 !(sd_status & SD_INT_COMPLETE))
[399]1159 continue;
1160 /* check whether this IRQ is really acceptable */
[426]1161 ok = azx_position_ok(chip, azx_dev);
1162 if (ok == 1) {
[399]1163 azx_dev->irq_pending = 0;
1164 spin_unlock(&chip->reg_lock);
1165 snd_pcm_period_elapsed(azx_dev->substream);
1166 spin_lock(&chip->reg_lock);
[426]1167 } else if (ok == 0 && chip->bus && chip->bus->workq) {
[399]1168 /* bogus IRQ, process it later */
1169 azx_dev->irq_pending = 1;
[426]1170 queue_work(chip->bus->workq,
1171 &chip->irq_pending_work);
[399]1172 }
1173 }
1174 }
1175
1176 /* clear rirb int */
1177 status = azx_readb(chip, RIRBSTS);
1178 if (status & RIRB_INT_MASK) {
[598]1179 if (status & RIRB_INT_RESPONSE) {
1180 if (chip->driver_type == AZX_DRIVER_CTX)
1181 udelay(80);
[399]1182 azx_update_rirb(chip);
[598]1183 }
[399]1184 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1185 }
1186
1187#if 0
1188 /* clear state status int */
1189 if (azx_readb(chip, STATESTS) & 0x04)
1190 azx_writeb(chip, STATESTS, 0x04);
1191#endif
1192 spin_unlock(&chip->reg_lock);
1193
[434]1194#ifdef TARGET_OS2
1195 if (status & RIRB_INT_MASK) {
[376]1196 return 2;
1197 }
[434]1198#endif
[399]1199
1200 return IRQ_HANDLED;
1201}
1202
1203
1204/*
1205 * set up a BDL entry
1206 */
1207static int setup_bdle(struct snd_pcm_substream *substream,
1208 struct azx_dev *azx_dev, u32 **bdlp,
1209 int ofs, int size, int with_ioc)
1210{
1211 u32 *bdl = *bdlp;
1212
1213 while (size > 0) {
1214 dma_addr_t addr;
1215 int chunk;
1216
1217 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1218 return -EINVAL;
1219
1220 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1221 /* program the address field of the BDL entry */
1222 bdl[0] = cpu_to_le32((u32)addr);
1223 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1224 /* program the size field of the BDL entry */
1225 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1226 bdl[2] = cpu_to_le32(chunk);
1227 /* program the IOC to enable interrupt
1228 * only when the whole fragment is processed
1229 */
1230 size -= chunk;
1231 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1232 bdl += 4;
1233 azx_dev->frags++;
1234 ofs += chunk;
1235 }
1236 *bdlp = bdl;
1237 return ofs;
1238}
1239
1240/*
1241 * set up BDL entries
1242 */
1243static int azx_setup_periods(struct azx *chip,
1244 struct snd_pcm_substream *substream,
1245 struct azx_dev *azx_dev)
1246{
1247 u32 *bdl;
1248 int i, ofs, periods, period_bytes;
1249 int pos_adj;
1250
1251 /* reset BDL address */
1252 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1253 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1254
[426]1255 period_bytes = azx_dev->period_bytes;
[399]1256 periods = azx_dev->bufsize / period_bytes;
1257
1258 /* program the initial BDL entries */
1259 bdl = (u32 *)azx_dev->bdl.area;
1260 ofs = 0;
1261 azx_dev->frags = 0;
1262 pos_adj = bdl_pos_adj[chip->dev_index];
1263 if (pos_adj > 0) {
1264 struct snd_pcm_runtime *runtime = substream->runtime;
1265 int pos_align = pos_adj;
1266 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1267 if (!pos_adj)
1268 pos_adj = pos_align;
1269 else
1270 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1271 pos_align;
1272 pos_adj = frames_to_bytes(runtime, pos_adj);
1273 if (pos_adj >= period_bytes) {
[464]1274 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
[399]1275 bdl_pos_adj[chip->dev_index]);
1276 pos_adj = 0;
1277 } else {
1278 ofs = setup_bdle(substream, azx_dev,
[598]1279 &bdl, ofs, pos_adj,
1280 !substream->runtime->no_period_wakeup);
[399]1281 if (ofs < 0)
1282 goto error;
1283 }
1284 } else
1285 pos_adj = 0;
1286 for (i = 0; i < periods; i++) {
1287 if (i == periods - 1 && pos_adj)
1288 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1289 period_bytes - pos_adj, 0);
1290 else
1291 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
[598]1292 period_bytes,
1293 !substream->runtime->no_period_wakeup);
[399]1294 if (ofs < 0)
1295 goto error;
1296 }
1297 return 0;
1298
1299 error:
[464]1300 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
[399]1301 azx_dev->bufsize, period_bytes);
1302 return -EINVAL;
1303}
1304
[426]1305/* reset stream */
1306static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
[399]1307{
1308 unsigned char val;
1309 int timeout;
1310
[426]1311 azx_stream_clear(chip, azx_dev);
1312
[399]1313 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1314 SD_CTL_STREAM_RESET);
1315 udelay(3);
1316 timeout = 300;
1317 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1318 --timeout)
1319 ;
1320 val &= ~SD_CTL_STREAM_RESET;
1321 azx_sd_writeb(azx_dev, SD_CTL, val);
1322 udelay(3);
1323
1324 timeout = 300;
1325 /* waiting for hardware to report that the stream is out of reset */
1326 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1327 --timeout)
1328 ;
1329
[426]1330 /* reset first position - may not be synced with hw at this time */
1331 *azx_dev->posbuf = 0;
1332}
1333
1334/*
1335 * set up the SD for streaming
1336 */
1337static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1338{
1339 /* make sure the run bit is zero for SD */
1340 azx_stream_clear(chip, azx_dev);
[399]1341 /* program the stream_tag */
1342 azx_sd_writel(azx_dev, SD_CTL,
1343 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1344 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1345
1346 /* program the length of samples in cyclic buffer */
1347 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1348
1349 /* program the stream format */
1350 /* this value needs to be the same as the one programmed */
1351 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1352
1353 /* program the stream LVI (last valid index) of the BDL */
1354 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1355
1356 /* program the BDL address */
1357 /* lower BDL address */
1358 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1359 /* upper BDL address */
1360 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1361
1362 /* enable the position buffer */
[598]1363 if (chip->position_fix[0] != POS_FIX_LPIB ||
1364 chip->position_fix[1] != POS_FIX_LPIB) {
[399]1365 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1366 azx_writel(chip, DPLBASE,
1367 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1368 }
1369
1370 /* set the interrupt enable bits in the descriptor control register */
1371 azx_sd_writel(azx_dev, SD_CTL,
1372 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1373
1374 return 0;
1375}
1376
[402]1377/*
1378 * Probe the given codec address
1379 */
1380static int probe_codec(struct azx *chip, int addr)
1381{
1382 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1383 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1384 unsigned int res;
[399]1385
[464]1386 mutex_lock(&chip->bus->cmd_mutex);
[402]1387 chip->probing = 1;
1388 azx_send_cmd(chip->bus, cmd);
[464]1389 res = azx_get_response(chip->bus, addr);
[402]1390 chip->probing = 0;
[464]1391 mutex_unlock(&chip->bus->cmd_mutex);
[402]1392 if (res == -1)
1393 return -EIO;
[464]1394 snd_printdd(SFX "codec #%d probed OK\n", addr);
[402]1395 return 0;
1396}
1397
1398static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1399 struct hda_pcm *cpcm);
1400static void azx_stop_chip(struct azx *chip);
1401
[464]1402static void azx_bus_reset(struct hda_bus *bus)
1403{
1404 struct azx *chip = bus->private_data;
1405
1406 bus->in_reset = 1;
1407 azx_stop_chip(chip);
[598]1408 azx_init_chip(chip, 1);
[464]1409#ifdef CONFIG_PM
1410 if (chip->initialized) {
1411 int i;
1412
[598]1413 for (i = 0; i < HDA_MAX_PCMS; i++)
[464]1414 snd_pcm_suspend_all(chip->pcm[i]);
1415 snd_hda_suspend(chip->bus);
1416 snd_hda_resume(chip->bus);
1417 }
1418#endif
1419 bus->in_reset = 0;
1420}
1421
[399]1422/*
1423 * Codec initialization
1424 */
1425
1426/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1427static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
[598]1428 [AZX_DRIVER_NVIDIA] = 8,
[399]1429 [AZX_DRIVER_TERA] = 1,
1430};
1431
[464]1432static int __devinit azx_codec_create(struct azx *chip, const char *model)
[399]1433{
1434 struct hda_bus_template bus_temp;
[402]1435 int c, codecs, err;
1436 int max_slots;
[399]1437
1438 memset(&bus_temp, 0, sizeof(bus_temp));
1439 bus_temp.private_data = chip;
1440 bus_temp.modelname = model;
1441 bus_temp.pci = chip->pci;
1442 bus_temp.ops.command = azx_send_cmd;
1443 bus_temp.ops.get_response = azx_get_response;
1444 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
[464]1445 bus_temp.ops.bus_reset = azx_bus_reset;
[399]1446#ifdef CONFIG_SND_HDA_POWER_SAVE
[426]1447 bus_temp.power_save = &power_save;
[399]1448 bus_temp.ops.pm_notify = azx_power_notify;
1449#endif
1450
1451 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1452 if (err < 0)
1453 return err;
1454
1455 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1456 chip->bus->needs_damn_long_delay = 1;
1457
[402]1458 codecs = 0;
[399]1459 max_slots = azx_max_codecs[chip->driver_type];
1460 if (!max_slots)
[598]1461 max_slots = AZX_DEFAULT_CODECS;
[402]1462
1463 /* First try to probe all given codec slots */
1464 for (c = 0; c < max_slots; c++) {
[426]1465 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
[402]1466 if (probe_codec(chip, c) < 0) {
1467 /* Some BIOSen give you wrong codec addresses
1468 * that don't exist
1469 */
[464]1470 snd_printk(KERN_WARNING SFX
1471 "Codec #%d probe error; "
[402]1472 "disabling it...\n", c);
1473 chip->codec_mask &= ~(1 << c);
1474 /* More badly, accessing to a non-existing
1475 * codec often screws up the controller chip,
[598]1476 * and disturbs the further communications.
[402]1477 * Thus if an error occurs during probing,
1478 * better to reset the controller chip to
1479 * get back to the sanity state.
1480 */
1481 azx_stop_chip(chip);
[598]1482 azx_init_chip(chip, 1);
[402]1483 }
1484 }
1485 }
1486
1487 /* Then create codec instances */
1488 for (c = 0; c < max_slots; c++) {
[426]1489 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
[399]1490 struct hda_codec *codec;
[464]1491 err = snd_hda_codec_new(chip->bus, c, &codec);
[399]1492 if (err < 0)
1493 continue;
[598]1494 codec->beep_mode = chip->beep_mode;
[399]1495 codecs++;
1496 }
1497 }
1498 if (!codecs) {
1499 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1500 return -ENXIO;
1501 }
[464]1502 return 0;
1503}
[399]1504
[464]1505/* configure each codec instance */
1506static int __devinit azx_codec_configure(struct azx *chip)
1507{
1508 struct hda_codec *codec;
1509 list_for_each_entry(codec, &chip->bus->codec_list, list, struct hda_codec) {
1510 snd_hda_codec_configure(codec);
1511 }
[399]1512 return 0;
1513}
1514
1515
1516/*
1517 * PCM support
1518 */
1519
1520/* assign a stream for the PCM */
[598]1521static inline struct azx_dev *
1522azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
[399]1523{
1524 int dev, i, nums;
[598]1525 struct azx_dev *res = NULL;
1526
1527 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
[399]1528 dev = chip->playback_index_offset;
1529 nums = chip->playback_streams;
1530 } else {
1531 dev = chip->capture_index_offset;
1532 nums = chip->capture_streams;
1533 }
1534 for (i = 0; i < nums; i++, dev++)
1535 if (!chip->azx_dev[dev].opened) {
[598]1536 res = &chip->azx_dev[dev];
1537 if (res->device == substream->pcm->device)
1538 break;
[399]1539 }
[598]1540 if (res) {
1541 res->opened = 1;
1542 res->device = substream->pcm->device;
1543 }
1544 return res;
[399]1545}
1546
1547/* release the assigned stream */
1548static inline void azx_release_device(struct azx_dev *azx_dev)
1549{
1550 azx_dev->opened = 0;
1551}
1552
1553static struct snd_pcm_hardware azx_pcm_hw = {
1554 .info = (SNDRV_PCM_INFO_MMAP |
1555 SNDRV_PCM_INFO_INTERLEAVED |
1556 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1557 SNDRV_PCM_INFO_MMAP_VALID |
1558 /* No full-resume yet implemented */
1559 /* SNDRV_PCM_INFO_RESUME |*/
1560 SNDRV_PCM_INFO_PAUSE |
[598]1561 SNDRV_PCM_INFO_SYNC_START |
1562 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
[399]1563 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1564 .rates = SNDRV_PCM_RATE_48000,
1565 .rate_min = 48000,
1566 .rate_max = 48000,
1567 .channels_min = 2,
1568 .channels_max = 2,
1569 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1570 .period_bytes_min = 128,
1571 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1572 .periods_min = 2,
1573 .periods_max = AZX_MAX_FRAG,
1574 .fifo_size = 0,
1575};
1576
1577struct azx_pcm {
1578 struct azx *chip;
1579 struct hda_codec *codec;
1580 struct hda_pcm_stream *hinfo[2];
1581};
1582
1583static int azx_pcm_open(struct snd_pcm_substream *substream)
1584{
1585 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1586 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1587 struct azx *chip = apcm->chip;
1588 struct azx_dev *azx_dev;
1589 struct snd_pcm_runtime *runtime = substream->runtime;
1590 unsigned long flags;
1591 int err;
1592
1593 mutex_lock(&chip->open_mutex);
[598]1594 azx_dev = azx_assign_device(chip, substream);
[399]1595 if (azx_dev == NULL) {
1596 mutex_unlock(&chip->open_mutex);
1597 return -EBUSY;
1598 }
1599 runtime->hw = azx_pcm_hw;
1600 runtime->hw.channels_min = hinfo->channels_min;
1601 runtime->hw.channels_max = hinfo->channels_max;
1602 runtime->hw.formats = hinfo->formats;
1603 runtime->hw.rates = hinfo->rates;
1604 snd_pcm_limit_hw_rates(runtime);
1605 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1606 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1607 128);
1608 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1609 128);
1610 snd_hda_power_up(apcm->codec);
1611 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1612 if (err < 0) {
1613 azx_release_device(azx_dev);
1614 snd_hda_power_down(apcm->codec);
1615 mutex_unlock(&chip->open_mutex);
1616 return err;
1617 }
[464]1618 snd_pcm_limit_hw_rates(runtime);
1619 /* sanity check */
1620 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1621 snd_BUG_ON(!runtime->hw.channels_max) ||
1622 snd_BUG_ON(!runtime->hw.formats) ||
1623 snd_BUG_ON(!runtime->hw.rates)) {
1624 azx_release_device(azx_dev);
1625 hinfo->ops.close(hinfo, apcm->codec, substream);
1626 snd_hda_power_down(apcm->codec);
1627 mutex_unlock(&chip->open_mutex);
1628 return -EINVAL;
1629 }
[399]1630 spin_lock_irqsave(&chip->reg_lock, flags);
1631 azx_dev->substream = substream;
1632 azx_dev->running = 0;
1633 spin_unlock_irqrestore(&chip->reg_lock, flags);
1634
1635 runtime->private_data = azx_dev;
1636 snd_pcm_set_sync(substream);
1637 mutex_unlock(&chip->open_mutex);
1638 return 0;
1639}
1640
1641static int azx_pcm_close(struct snd_pcm_substream *substream)
1642{
1643 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1644 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1645 struct azx *chip = apcm->chip;
1646 struct azx_dev *azx_dev = get_azx_dev(substream);
1647 unsigned long flags;
1648
1649 mutex_lock(&chip->open_mutex);
1650 spin_lock_irqsave(&chip->reg_lock, flags);
1651 azx_dev->substream = NULL;
1652 azx_dev->running = 0;
1653 spin_unlock_irqrestore(&chip->reg_lock, flags);
1654 azx_release_device(azx_dev);
1655 hinfo->ops.close(hinfo, apcm->codec, substream);
1656 snd_hda_power_down(apcm->codec);
1657 mutex_unlock(&chip->open_mutex);
1658 return 0;
1659}
1660
1661static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1662 struct snd_pcm_hw_params *hw_params)
1663{
[426]1664 struct azx_dev *azx_dev = get_azx_dev(substream);
1665
1666 azx_dev->bufsize = 0;
1667 azx_dev->period_bytes = 0;
1668 azx_dev->format_val = 0;
[399]1669 return snd_pcm_lib_malloc_pages(substream,
1670 params_buffer_bytes(hw_params));
1671}
1672
1673static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1674{
1675 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1676 struct azx_dev *azx_dev = get_azx_dev(substream);
1677 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1678
1679 /* reset BDL address */
1680 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1681 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1682 azx_sd_writel(azx_dev, SD_CTL, 0);
[426]1683 azx_dev->bufsize = 0;
1684 azx_dev->period_bytes = 0;
1685 azx_dev->format_val = 0;
[399]1686
[598]1687 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
[399]1688
1689 return snd_pcm_lib_free_pages(substream);
1690}
1691
1692static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1693{
1694 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1695 struct azx *chip = apcm->chip;
1696 struct azx_dev *azx_dev = get_azx_dev(substream);
1697 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1698 struct snd_pcm_runtime *runtime = substream->runtime;
[598]1699 unsigned int bufsize, period_bytes, format_val, stream_tag;
[426]1700 int err;
[399]1701
[426]1702 azx_stream_reset(chip, azx_dev);
1703 format_val = snd_hda_calc_stream_format(runtime->rate,
1704 runtime->channels,
1705 runtime->format,
[598]1706 hinfo->maxbps,
1707 apcm->codec->spdif_ctls);
[426]1708 if (!format_val) {
[399]1709 snd_printk(KERN_ERR SFX
1710 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1711 runtime->rate, runtime->channels, runtime->format);
1712 return -EINVAL;
1713 }
1714
[426]1715 bufsize = snd_pcm_lib_buffer_bytes(substream);
1716 period_bytes = snd_pcm_lib_period_bytes(substream);
1717
[464]1718 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
[426]1719 bufsize, format_val);
1720
1721 if (bufsize != azx_dev->bufsize ||
1722 period_bytes != azx_dev->period_bytes ||
1723 format_val != azx_dev->format_val) {
1724 azx_dev->bufsize = bufsize;
1725 azx_dev->period_bytes = period_bytes;
1726 azx_dev->format_val = format_val;
1727 err = azx_setup_periods(chip, substream, azx_dev);
1728 if (err < 0)
1729 return err;
1730 }
1731
[598]1732 /* wallclk has 24Mhz clock source */
1733 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1734 runtime->rate) * 1000);
[399]1735 azx_setup_controller(chip, azx_dev);
1736 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1737 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1738 else
1739 azx_dev->fifo_size = 0;
1740
[598]1741 stream_tag = azx_dev->stream_tag;
1742 /* CA-IBG chips need the playback stream starting from 1 */
1743 if (chip->driver_type == AZX_DRIVER_CTX &&
1744 stream_tag > chip->capture_streams)
1745 stream_tag -= chip->capture_streams;
1746 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1747 azx_dev->format_val, substream);
[399]1748}
1749
1750static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1751{
1752 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1753 struct azx *chip = apcm->chip;
1754 struct azx_dev *azx_dev;
1755 struct snd_pcm_substream *s;
[426]1756 int rstart = 0, start, nsync = 0, sbits = 0;
[399]1757 int nwait, timeout;
1758
1759 switch (cmd) {
[426]1760 case SNDRV_PCM_TRIGGER_START:
1761 rstart = 1;
[399]1762 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1763 case SNDRV_PCM_TRIGGER_RESUME:
1764 start = 1;
1765 break;
1766 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1767 case SNDRV_PCM_TRIGGER_SUSPEND:
1768 case SNDRV_PCM_TRIGGER_STOP:
1769 start = 0;
1770 break;
1771 default:
1772 return -EINVAL;
1773 }
1774
1775 snd_pcm_group_for_each_entry(s, substream) {
1776 if (s->pcm->card != substream->pcm->card)
1777 continue;
1778 azx_dev = get_azx_dev(s);
1779 sbits |= 1 << azx_dev->index;
1780 nsync++;
1781 snd_pcm_trigger_done(s, substream);
1782 }
1783
1784 spin_lock(&chip->reg_lock);
1785 if (nsync > 1) {
1786 /* first, set SYNC bits of corresponding streams */
1787 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1788 }
1789 snd_pcm_group_for_each_entry(s, substream) {
1790 if (s->pcm->card != substream->pcm->card)
1791 continue;
1792 azx_dev = get_azx_dev(s);
[598]1793 if (start) {
1794 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1795 if (!rstart)
1796 azx_dev->start_wallclk -=
1797 azx_dev->period_wallclk;
[399]1798 azx_stream_start(chip, azx_dev);
[598]1799 } else {
[399]1800 azx_stream_stop(chip, azx_dev);
[598]1801 }
[399]1802 azx_dev->running = start;
1803 }
1804 spin_unlock(&chip->reg_lock);
1805 if (start) {
1806 if (nsync == 1)
1807 return 0;
1808 /* wait until all FIFOs get ready */
1809 for (timeout = 5000; timeout; timeout--) {
1810 nwait = 0;
1811 snd_pcm_group_for_each_entry(s, substream) {
1812 if (s->pcm->card != substream->pcm->card)
1813 continue;
1814 azx_dev = get_azx_dev(s);
1815 if (!(azx_sd_readb(azx_dev, SD_STS) &
1816 SD_STS_FIFO_READY))
1817 nwait++;
1818 }
1819 if (!nwait)
1820 break;
1821 cpu_relax();
1822 }
1823 } else {
1824 /* wait until all RUN bits are cleared */
1825 for (timeout = 5000; timeout; timeout--) {
1826 nwait = 0;
1827 snd_pcm_group_for_each_entry(s, substream) {
1828 if (s->pcm->card != substream->pcm->card)
1829 continue;
1830 azx_dev = get_azx_dev(s);
1831 if (azx_sd_readb(azx_dev, SD_CTL) &
1832 SD_CTL_DMA_START)
1833 nwait++;
1834 }
1835 if (!nwait)
1836 break;
1837 cpu_relax();
1838 }
1839 }
1840 if (nsync > 1) {
1841 spin_lock(&chip->reg_lock);
1842 /* reset SYNC bits */
1843 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1844 spin_unlock(&chip->reg_lock);
1845 }
1846 return 0;
1847}
1848
1849/* get the current DMA position with correction on VIA chips */
1850static unsigned int azx_via_get_position(struct azx *chip,
1851 struct azx_dev *azx_dev)
1852{
1853 unsigned int link_pos, mini_pos, bound_pos;
1854 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1855 unsigned int fifo_size;
1856
1857 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1858 if (azx_dev->index >= 4) {
1859 /* Playback, no problem using link position */
1860 return link_pos;
1861 }
1862
1863 /* Capture */
1864 /* For new chipset,
1865 * use mod to get the DMA position just like old chipset
1866 */
1867 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1868 mod_dma_pos %= azx_dev->period_bytes;
1869
1870 /* azx_dev->fifo_size can't get FIFO size of in stream.
1871 * Get from base address + offset.
1872 */
1873 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1874
1875 if (azx_dev->insufficient) {
1876 /* Link position never gather than FIFO size */
1877 if (link_pos <= fifo_size)
1878 return 0;
1879
1880 azx_dev->insufficient = 0;
1881 }
1882
1883 if (link_pos <= fifo_size)
1884 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1885 else
1886 mini_pos = link_pos - fifo_size;
1887
1888 /* Find nearest previous boudary */
1889 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1890 mod_link_pos = link_pos % azx_dev->period_bytes;
1891 if (mod_link_pos >= fifo_size)
1892 bound_pos = link_pos - mod_link_pos;
1893 else if (mod_dma_pos >= mod_mini_pos)
1894 bound_pos = mini_pos - mod_mini_pos;
1895 else {
1896 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1897 if (bound_pos >= azx_dev->bufsize)
1898 bound_pos = 0;
1899 }
1900
1901 /* Calculate real DMA position we want */
1902 return bound_pos + mod_dma_pos;
1903}
1904
1905static unsigned int azx_get_position(struct azx *chip,
1906 struct azx_dev *azx_dev)
1907{
1908 unsigned int pos;
[598]1909 int stream = azx_dev->substream->stream;
[399]1910
[598]1911 switch (chip->position_fix[stream]) {
1912 case POS_FIX_LPIB:
1913 /* read LPIB */
1914 pos = azx_sd_readl(azx_dev, SD_LPIB);
1915 break;
1916 case POS_FIX_VIACOMBO:
[399]1917 pos = azx_via_get_position(chip, azx_dev);
[598]1918 break;
1919 default:
[399]1920 /* use the position buffer */
1921 pos = le32_to_cpu(*azx_dev->posbuf);
1922 }
[598]1923
[399]1924 if (pos >= azx_dev->bufsize)
1925 pos = 0;
1926 return pos;
1927}
1928
1929static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1930{
1931 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1932 struct azx *chip = apcm->chip;
1933 struct azx_dev *azx_dev = get_azx_dev(substream);
1934 return bytes_to_frames(substream->runtime,
1935 azx_get_position(chip, azx_dev));
1936}
1937
1938/*
1939 * Check whether the current DMA position is acceptable for updating
1940 * periods. Returns non-zero if it's OK.
1941 *
1942 * Many HD-audio controllers appear pretty inaccurate about
1943 * the update-IRQ timing. The IRQ is issued before actually the
1944 * data is processed. So, we need to process it afterwords in a
1945 * workqueue.
1946 */
1947static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1948{
[598]1949 u32 wallclk;
[399]1950 unsigned int pos;
[598]1951 int stream;
[399]1952
[598]1953 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1954 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
[426]1955 return -1; /* bogus (too early) interrupt */
1956
[598]1957 stream = azx_dev->substream->stream;
[399]1958 pos = azx_get_position(chip, azx_dev);
[598]1959 if (chip->position_fix[stream] == POS_FIX_AUTO) {
[399]1960 if (!pos) {
1961 printk(KERN_WARNING
1962 "hda-intel: Invalid position buffer, "
1963 "using LPIB read method instead.\n");
[598]1964 chip->position_fix[stream] = POS_FIX_LPIB;
[399]1965 pos = azx_get_position(chip, azx_dev);
1966 } else
[598]1967 chip->position_fix[stream] = POS_FIX_POSBUF;
[399]1968 }
1969
[598]1970#ifndef TARGET_OS2
1971 if (WARN_ONCE(!azx_dev->period_bytes,
1972 "hda-intel: zero azx_dev->period_bytes"))
1973 return -1; /* this shouldn't happen! */
1974#endif
1975 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1976 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1977 /* NG - it's below the first next period boundary */
1978 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
1979 azx_dev->start_wallclk += wallclk;
[399]1980 return 1; /* OK, it's fine */
1981}
1982
1983/*
1984 * The work for pending PCM period updates.
1985 */
1986static void azx_irq_pending_work(struct work_struct *work)
1987{
1988 struct azx *chip = container_of(work, struct azx, irq_pending_work);
[598]1989 int i, pending, ok;
[399]1990
1991 if (!chip->irq_pending_warned) {
1992 printk(KERN_WARNING
1993 "hda-intel: IRQ timing workaround is activated "
1994 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1995 chip->card->number);
1996 chip->irq_pending_warned = 1;
1997 }
1998
1999 for (;;) {
2000 pending = 0;
2001 spin_lock_irq(&chip->reg_lock);
2002 for (i = 0; i < chip->num_streams; i++) {
2003 struct azx_dev *azx_dev = &chip->azx_dev[i];
2004 if (!azx_dev->irq_pending ||
2005 !azx_dev->substream ||
2006 !azx_dev->running)
2007 continue;
[598]2008 ok = azx_position_ok(chip, azx_dev);
2009 if (ok > 0) {
[399]2010 azx_dev->irq_pending = 0;
2011 spin_unlock(&chip->reg_lock);
2012 snd_pcm_period_elapsed(azx_dev->substream);
2013 spin_lock(&chip->reg_lock);
[598]2014 } else if (ok < 0) {
2015 pending = 0; /* too early */
[399]2016 } else
2017 pending++;
2018 }
2019 spin_unlock_irq(&chip->reg_lock);
2020 if (!pending)
2021 return;
[598]2022 msleep(1);
[399]2023 }
2024}
2025
2026/* clear irq_pending flags and assure no on-going workq */
2027static void azx_clear_irq_pending(struct azx *chip)
2028{
2029 int i;
2030
2031 spin_lock_irq(&chip->reg_lock);
2032 for (i = 0; i < chip->num_streams; i++)
2033 chip->azx_dev[i].irq_pending = 0;
2034 spin_unlock_irq(&chip->reg_lock);
2035}
2036
2037static struct snd_pcm_ops azx_pcm_ops = {
2038 .open = azx_pcm_open,
2039 .close = azx_pcm_close,
2040 .ioctl = snd_pcm_lib_ioctl,
2041 .hw_params = azx_pcm_hw_params,
2042 .hw_free = azx_pcm_hw_free,
2043 .prepare = azx_pcm_prepare,
2044 .trigger = azx_pcm_trigger,
2045 .pointer = azx_pcm_pointer,
2046 .page = snd_pcm_sgbuf_ops_page,
2047};
2048
2049static void azx_pcm_free(struct snd_pcm *pcm)
2050{
2051 struct azx_pcm *apcm = pcm->private_data;
2052 if (apcm) {
2053 apcm->chip->pcm[pcm->device] = NULL;
2054 kfree(apcm);
2055 }
2056}
2057
2058static int
[402]2059azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2060 struct hda_pcm *cpcm)
[399]2061{
[402]2062 struct azx *chip = bus->private_data;
[399]2063 struct snd_pcm *pcm;
2064 struct azx_pcm *apcm;
2065 int pcm_dev = cpcm->device;
2066 int s, err;
2067
[598]2068 if (pcm_dev >= HDA_MAX_PCMS) {
[399]2069 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2070 pcm_dev);
2071 return -EINVAL;
2072 }
2073 if (chip->pcm[pcm_dev]) {
2074 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2075 return -EBUSY;
2076 }
2077 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2078 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2079 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2080 &pcm);
2081 if (err < 0)
2082 return err;
[464]2083 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
[399]2084 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2085 if (apcm == NULL)
2086 return -ENOMEM;
2087 apcm->chip = chip;
2088 apcm->codec = codec;
2089 pcm->private_data = apcm;
2090 pcm->private_free = azx_pcm_free;
2091 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2092 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2093 chip->pcm[pcm_dev] = pcm;
2094 cpcm->pcm = pcm;
2095 for (s = 0; s < 2; s++) {
2096 apcm->hinfo[s] = &cpcm->stream[s];
2097 if (cpcm->stream[s].substreams)
2098 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2099 }
2100 /* buffer pre-allocation */
2101 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2102 snd_dma_pci_data(chip->pci),
2103 1024 * 64, 32 * 1024 * 1024);
2104 return 0;
2105}
2106
2107/*
2108 * mixer creation - all stuff is implemented in hda module
2109 */
2110static int __devinit azx_mixer_create(struct azx *chip)
2111{
2112 return snd_hda_build_controls(chip->bus);
2113}
2114
2115
2116/*
2117 * initialize SD streams
2118 */
2119static int __devinit azx_init_stream(struct azx *chip)
2120{
2121 int i;
2122
2123 /* initialize each stream (aka device)
2124 * assign the starting bdl address to each stream (device)
2125 * and initialize
2126 */
2127 for (i = 0; i < chip->num_streams; i++) {
2128 struct azx_dev *azx_dev = &chip->azx_dev[i];
2129 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2130 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2131 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2132 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2133 azx_dev->sd_int_sta_mask = 1 << i;
2134 /* stream tag: must be non-zero and unique */
2135 azx_dev->index = i;
2136 azx_dev->stream_tag = i + 1;
2137 }
2138
2139 return 0;
2140}
2141
2142static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2143{
2144 if (request_irq(chip->pci->irq, azx_interrupt,
2145 chip->msi ? 0 : IRQF_SHARED,
[598]2146 "hda_intel", chip)) {
[399]2147 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2148 "disabling device\n", chip->pci->irq);
[445]2149#ifndef TARGET_OS2
[399]2150 if (do_disconnect)
2151 snd_card_disconnect(chip->card);
2152#endif
2153 return -1;
2154 }
2155 chip->irq = chip->pci->irq;
2156 pci_intx(chip->pci, !chip->msi);
2157 return 0;
2158}
2159
2160
2161static void azx_stop_chip(struct azx *chip)
2162{
2163 if (!chip->initialized)
2164 return;
2165
2166 /* disable interrupts */
2167 azx_int_disable(chip);
2168 azx_int_clear(chip);
2169
2170 /* disable CORB/RIRB */
2171 azx_free_cmd_io(chip);
2172
2173 /* disable position buffer */
2174 azx_writel(chip, DPLBASE, 0);
2175 azx_writel(chip, DPUBASE, 0);
2176
2177 chip->initialized = 0;
2178}
2179
2180#ifdef CONFIG_SND_HDA_POWER_SAVE
2181/* power-up/down the controller */
[402]2182static void azx_power_notify(struct hda_bus *bus)
[399]2183{
[402]2184 struct azx *chip = bus->private_data;
[399]2185 struct hda_codec *c;
2186 int power_on = 0;
2187
[402]2188 list_for_each_entry(c, &bus->codec_list, list, struct hda_codec) {
[399]2189 if (c->power_on) {
2190 power_on = 1;
2191 break;
2192 }
2193 }
2194 if (power_on)
[598]2195 azx_init_chip(chip, 1);
2196 else if (chip->running && power_save_controller &&
2197 !bus->power_keep_link_on)
[399]2198 azx_stop_chip(chip);
2199}
2200#endif /* CONFIG_SND_HDA_POWER_SAVE */
2201
2202#ifdef CONFIG_PM
2203/*
2204 * power management
2205 */
[426]2206
2207static int snd_hda_codecs_inuse(struct hda_bus *bus)
2208{
2209 struct hda_codec *codec;
2210
2211 list_for_each_entry(codec, &bus->codec_list, list, struct hda_codec) {
2212 if (snd_hda_codec_needs_resume(codec))
2213 return 1;
2214 }
2215 return 0;
2216}
2217
[399]2218static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2219{
2220 struct snd_card *card = pci_get_drvdata(pci);
2221 struct azx *chip = card->private_data;
2222 int i;
2223
2224 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2225 azx_clear_irq_pending(chip);
[598]2226 for (i = 0; i < HDA_MAX_PCMS; i++)
[399]2227 snd_pcm_suspend_all(chip->pcm[i]);
2228 if (chip->initialized)
[464]2229 snd_hda_suspend(chip->bus);
[399]2230 azx_stop_chip(chip);
2231 if (chip->irq >= 0) {
2232 free_irq(chip->irq, chip);
2233 chip->irq = -1;
2234 }
2235 if (chip->msi)
2236 pci_disable_msi(chip->pci);
2237 pci_disable_device(pci);
2238 pci_save_state(pci);
2239 pci_set_power_state(pci, pci_choose_state(pci, state));
2240 return 0;
2241}
2242
2243static int azx_resume(struct pci_dev *pci)
2244{
2245 struct snd_card *card = pci_get_drvdata(pci);
2246 struct azx *chip = card->private_data;
2247
[417]2248 pci_set_power_state(pci, PCI_D0);
[399]2249 pci_restore_state(pci);
2250 if (pci_enable_device(pci) < 0) {
2251 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2252 "disabling device\n");
2253 snd_card_disconnect(card);
2254 return -EIO;
2255 }
2256 pci_set_master(pci);
2257 if (chip->msi)
2258 if (pci_enable_msi(pci) < 0)
2259 chip->msi = 0;
2260 if (azx_acquire_irq(chip, 1) < 0)
2261 return -EIO;
2262 azx_init_pci(chip);
2263
2264 if (snd_hda_codecs_inuse(chip->bus))
[598]2265 azx_init_chip(chip, 1);
[399]2266
2267 snd_hda_resume(chip->bus);
2268 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2269 return 0;
2270}
2271#endif /* CONFIG_PM */
2272
2273
2274/*
[402]2275 * reboot notifier for hang-up problem at power-down
2276 */
2277static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2278{
2279 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
[598]2280 snd_hda_bus_reboot_notify(chip->bus);
[402]2281 azx_stop_chip(chip);
2282 return NOTIFY_OK;
2283}
2284
2285static void azx_notifier_register(struct azx *chip)
2286{
2287 chip->reboot_notifier.notifier_call = azx_halt;
2288 register_reboot_notifier(&chip->reboot_notifier);
2289}
2290
2291static void azx_notifier_unregister(struct azx *chip)
2292{
2293 if (chip->reboot_notifier.notifier_call)
2294 unregister_reboot_notifier(&chip->reboot_notifier);
2295}
2296
2297/*
[399]2298 * destructor
2299 */
2300static int azx_free(struct azx *chip)
2301{
2302 int i;
2303
[402]2304 azx_notifier_unregister(chip);
2305
[399]2306 if (chip->initialized) {
2307 azx_clear_irq_pending(chip);
2308 for (i = 0; i < chip->num_streams; i++)
2309 azx_stream_stop(chip, &chip->azx_dev[i]);
2310 azx_stop_chip(chip);
2311 }
2312
2313 if (chip->irq >= 0)
2314 free_irq(chip->irq, (void*)chip);
2315 if (chip->msi)
2316 pci_disable_msi(chip->pci);
2317 if (chip->remap_addr)
2318#ifdef TARGET_OS2
2319 iounmap((void *)chip->remap_addr);
2320#else
2321 iounmap(chip->remap_addr);
2322#endif
2323 if (chip->azx_dev) {
2324 for (i = 0; i < chip->num_streams; i++)
2325 if (chip->azx_dev[i].bdl.area)
2326 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2327 }
2328 if (chip->rb.area)
2329 snd_dma_free_pages(&chip->rb);
2330 if (chip->posbuf.area)
2331 snd_dma_free_pages(&chip->posbuf);
2332 pci_release_regions(chip->pci);
2333 pci_disable_device(chip->pci);
2334 kfree(chip->azx_dev);
2335 kfree(chip);
2336
2337 return 0;
2338}
2339
2340static int azx_dev_free(struct snd_device *device)
2341{
2342 return azx_free(device->device_data);
2343}
2344
2345/*
2346 * white/black-listing for position_fix
2347 */
2348static struct snd_pci_quirk position_fix_list[] __devinitdata = {
[598]2349 SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB),
2350 SND_PCI_QUIRK(0x1025, 0x026f, "Acer Aspire 5538", POS_FIX_LPIB),
[399]2351 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2352 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
[598]2353 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2354 SND_PCI_QUIRK(0x1028, 0x0470, "Dell Inspiron 1120", POS_FIX_LPIB),
2355 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
[399]2356 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
[598]2357 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2358 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2359 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2360 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2361 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
2362 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2363 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2364 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2365 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2366 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2367 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2368 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2369 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
[399]2370 {0}
2371};
2372
2373static int __devinit check_position_fix(struct azx *chip, int fix)
2374{
2375 const struct snd_pci_quirk *q;
2376
[426]2377 switch (fix) {
2378 case POS_FIX_LPIB:
2379 case POS_FIX_POSBUF:
[598]2380 case POS_FIX_VIACOMBO:
[426]2381 return fix;
2382 }
2383
2384 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2385 if (q) {
2386 printk(KERN_INFO
2387 "hda_intel: position_fix set to %d "
2388 "for device %04x:%04x\n",
2389 q->value, q->subvendor, q->subdevice);
2390 return q->value;
[399]2391 }
[598]2392
2393 /* Check VIA/ATI HD Audio Controller exist */
2394 switch (chip->driver_type) {
2395 case AZX_DRIVER_VIA:
2396 case AZX_DRIVER_ATI:
2397 /* Use link position directly, avoid any transfer problem. */
2398 return POS_FIX_VIACOMBO;
2399 }
2400
[426]2401 return POS_FIX_AUTO;
[399]2402}
2403
2404/*
2405 * black-lists for probe_mask
2406 */
2407static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2408 /* Thinkpad often breaks the controller communication when accessing
2409 * to the non-working (or non-existing) modem codec slot.
2410 */
2411 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2412 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2413 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
[426]2414 /* broken BIOS */
2415 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2416 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2417 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2418 /* forced codec slots */
[464]2419 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
[426]2420 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
[399]2421 {0}
2422};
2423
[426]2424#define AZX_FORCE_CODEC_MASK 0x100
2425
[399]2426static void __devinit check_probe_mask(struct azx *chip, int dev)
2427{
2428 const struct snd_pci_quirk *q;
2429
[426]2430 chip->codec_probe_mask = probe_mask[dev];
2431 if (chip->codec_probe_mask == -1) {
[399]2432 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2433 if (q) {
2434 printk(KERN_INFO
2435 "hda_intel: probe_mask set to 0x%x "
2436 "for device %04x:%04x\n",
2437 q->value, q->subvendor, q->subdevice);
[426]2438 chip->codec_probe_mask = q->value;
[399]2439 }
2440 }
[426]2441
2442 /* check forced option */
2443 if (chip->codec_probe_mask != -1 &&
2444 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2445 chip->codec_mask = chip->codec_probe_mask & 0xff;
2446 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2447 chip->codec_mask);
2448 }
[399]2449}
2450
[464]2451/*
[598]2452 * white/black-list for enable_msi
[464]2453 */
[598]2454static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2455 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2456 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2457 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2458 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2459 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
[464]2460 {0}
2461};
[399]2462
[464]2463static void __devinit check_msi(struct azx *chip)
2464{
2465 const struct snd_pci_quirk *q;
2466
[598]2467 if (enable_msi >= 0) {
2468 chip->msi = !!enable_msi;
[464]2469 return;
[598]2470 }
2471 chip->msi = 1; /* enable MSI as default */
2472 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
[464]2473 if (q) {
2474 printk(KERN_INFO
2475 "hda_intel: msi for device %04x:%04x set to %d\n",
2476 q->subvendor, q->subdevice, q->value);
2477 chip->msi = q->value;
[598]2478 return;
[464]2479 }
[598]2480
2481 /* NVidia chipsets seem to cause troubles with MSI */
2482 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2483 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2484 chip->msi = 0;
2485 }
[464]2486}
2487
2488
[399]2489/*
2490 * constructor
2491 */
2492static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2493 int dev, int driver_type,
2494 struct azx **rchip)
2495{
2496 struct azx *chip;
2497 int i, err;
2498 unsigned short gcap;
2499 static struct snd_device_ops ops = {
2500 .dev_free = azx_dev_free,
2501 };
2502
2503 *rchip = NULL;
2504
2505 err = pci_enable_device(pci);
2506 if (err < 0)
2507 return err;
2508
2509 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2510 if (!chip) {
2511 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2512 pci_disable_device(pci);
2513 return -ENOMEM;
2514 }
2515
2516 spin_lock_init(&chip->reg_lock);
2517 mutex_init(&chip->open_mutex);
2518 chip->card = card;
2519 chip->pci = pci;
2520 chip->irq = -1;
2521 chip->driver_type = driver_type;
[464]2522 check_msi(chip);
[399]2523 chip->dev_index = dev;
2524 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2525
[598]2526 chip->position_fix[0] = chip->position_fix[1] =
2527 check_position_fix(chip, position_fix[dev]);
[399]2528 check_probe_mask(chip, dev);
2529
2530 chip->single_cmd = single_cmd;
2531
2532 if (bdl_pos_adj[dev] < 0) {
2533 switch (chip->driver_type) {
2534 case AZX_DRIVER_ICH:
[598]2535 case AZX_DRIVER_PCH:
[399]2536 bdl_pos_adj[dev] = 1;
2537 break;
2538 default:
2539 bdl_pos_adj[dev] = 32;
2540 break;
2541 }
2542 }
2543
2544#if BITS_PER_LONG != 64
2545 /* Fix up base address on ULI M5461 */
2546 if (chip->driver_type == AZX_DRIVER_ULI) {
2547 u16 tmp3;
2548 pci_read_config_word(pci, 0x40, &tmp3);
2549 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2550 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2551 }
2552#endif
2553
2554 err = pci_request_regions(pci, "ICH HD audio");
2555 if (err < 0) {
2556 kfree(chip);
2557 pci_disable_device(pci);
2558 return err;
2559 }
2560
2561 chip->addr = pci_resource_start(pci, 0);
2562 chip->remap_addr = pci_ioremap_bar(pci, 0);
2563 if (chip->remap_addr == NULL) {
2564 snd_printk(KERN_ERR SFX "ioremap error\n");
2565 err = -ENXIO;
2566 goto errout;
2567 }
2568
2569 if (chip->msi)
2570 if (pci_enable_msi(pci) < 0)
2571 chip->msi = 0;
2572
2573 if (azx_acquire_irq(chip, 0) < 0) {
2574 err = -EBUSY;
2575 goto errout;
2576 }
2577
2578 pci_set_master(pci);
2579 synchronize_irq(chip->irq);
2580
2581 gcap = azx_readw(chip, GCAP);
[464]2582 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
[399]2583
[464]2584 /* disable SB600 64bit support for safety */
2585 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2586 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2587 struct pci_dev *p_smbus;
2588 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2589 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2590 NULL);
2591 if (p_smbus) {
2592 if (snd_pci_revision(p_smbus) < 0x30)
2593 gcap &= ~ICH6_GCAP_64OK;
2594 pci_dev_put(p_smbus);
2595 }
2596 }
[426]2597
[598]2598 /* disable 64bit DMA address for Teradici */
2599 /* it does not work with device 6549:1200 subsys e4a2:040b */
2600 if (chip->driver_type == AZX_DRIVER_TERA)
2601 gcap &= ~ICH6_GCAP_64OK;
2602
[522]2603#pragma disable_message (135,302)
[399]2604 /* allow 64bit DMA address if supported by H/W */
[464]2605 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
[426]2606 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2607 else {
2608 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2609 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2610 }
[522]2611#pragma enable_message (135,302)
[399]2612
2613 /* read number of streams from GCAP register instead of using
2614 * hardcoded value
2615 */
2616 chip->capture_streams = (gcap >> 8) & 0x0f;
2617 chip->playback_streams = (gcap >> 12) & 0x0f;
2618 if (!chip->playback_streams && !chip->capture_streams) {
2619 /* gcap didn't give any info, switching to old method */
2620
2621 switch (chip->driver_type) {
2622 case AZX_DRIVER_ULI:
2623 chip->playback_streams = ULI_NUM_PLAYBACK;
2624 chip->capture_streams = ULI_NUM_CAPTURE;
2625 break;
2626 case AZX_DRIVER_ATIHDMI:
2627 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2628 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2629 break;
[426]2630 case AZX_DRIVER_GENERIC:
[399]2631 default:
2632 chip->playback_streams = ICH6_NUM_PLAYBACK;
2633 chip->capture_streams = ICH6_NUM_CAPTURE;
2634 break;
2635 }
2636 }
2637 chip->capture_index_offset = 0;
2638 chip->playback_index_offset = chip->capture_streams;
2639 chip->num_streams = chip->playback_streams + chip->capture_streams;
2640 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2641 GFP_KERNEL);
2642 if (!chip->azx_dev) {
[464]2643 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
[399]2644 goto errout;
2645 }
2646
2647 for (i = 0; i < chip->num_streams; i++) {
2648 /* allocate memory for the BDL for each stream */
2649 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2650 snd_dma_pci_data(chip->pci),
2651 BDL_SIZE, &chip->azx_dev[i].bdl);
2652 if (err < 0) {
2653 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2654 goto errout;
2655 }
2656 }
2657 /* allocate memory for the position buffer */
2658 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2659 snd_dma_pci_data(chip->pci),
2660 chip->num_streams * 8, &chip->posbuf);
2661 if (err < 0) {
2662 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2663 goto errout;
2664 }
2665 /* allocate CORB/RIRB */
[464]2666 err = azx_alloc_cmd_io(chip);
2667 if (err < 0)
2668 goto errout;
[399]2669
2670 /* initialize streams */
2671 azx_init_stream(chip);
2672
2673 /* initialize chip */
2674 azx_init_pci(chip);
[598]2675 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
[399]2676
2677 /* codec detection */
2678 if (!chip->codec_mask) {
2679 snd_printk(KERN_ERR SFX "no codecs found!\n");
2680 err = -ENODEV;
2681 goto errout;
2682 }
2683
2684 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2685 if (err <0) {
2686 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2687 goto errout;
2688 }
2689
2690 strcpy(card->driver, "HDA-Intel");
[464]2691 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2692 sizeof(card->shortname));
2693 snprintf(card->longname, sizeof(card->longname),
2694 "%s at 0x%lx irq %i",
2695 card->shortname, chip->addr, chip->irq);
[399]2696
2697 *rchip = chip;
2698 return 0;
2699
2700 errout:
2701 azx_free(chip);
2702 return err;
2703}
2704
2705static void power_down_all_codecs(struct azx *chip)
2706{
2707#ifdef CONFIG_SND_HDA_POWER_SAVE
2708 /* The codecs were powered up in snd_hda_codec_new().
2709 * Now all initialization done, so turn them down if possible
2710 */
2711 struct hda_codec *codec;
2712 list_for_each_entry(codec, &chip->bus->codec_list, list, struct hda_codec) {
2713 snd_hda_power_down(codec);
2714 }
2715#endif
2716}
2717
2718static int __devinit azx_probe(struct pci_dev *pci,
2719 const struct pci_device_id *pci_id)
2720{
2721 static int dev;
2722 struct snd_card *card;
2723 struct azx *chip;
2724 int err;
2725
2726 if (dev >= SNDRV_CARDS)
2727 return -ENODEV;
2728 if (!enable[dev]) {
2729 dev++;
2730 return -ENOENT;
2731 }
2732
[426]2733 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2734 if (err < 0) {
[399]2735 snd_printk(KERN_ERR SFX "Error creating card!\n");
[426]2736 return err;
[399]2737 }
2738
[464]2739 /* set this here since it's referred in snd_hda_load_patch() */
2740 snd_card_set_dev(card, &pci->dev);
2741
[399]2742 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
[426]2743 if (err < 0)
2744 goto out_free;
[399]2745 card->private_data = chip;
2746
[598]2747#ifdef CONFIG_SND_HDA_INPUT_BEEP
2748 chip->beep_mode = beep_mode[dev];
2749#endif
2750
[399]2751 /* create codec instances */
[464]2752 err = azx_codec_create(chip, model[dev]);
[426]2753 if (err < 0)
2754 goto out_free;
[464]2755#ifdef CONFIG_SND_HDA_PATCH_LOADER
2756 if (patch[dev]) {
2757 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2758 patch[dev]);
2759 err = snd_hda_load_patch(chip->bus, patch[dev]);
2760 if (err < 0)
2761 goto out_free;
2762 }
2763#endif
[598]2764 if ((probe_only[dev] & 1) == 0) {
[464]2765 err = azx_codec_configure(chip);
2766 if (err < 0)
2767 goto out_free;
2768 }
[399]2769
2770 /* create PCM streams */
2771 err = snd_hda_build_pcms(chip->bus);
[426]2772 if (err < 0)
2773 goto out_free;
[598]2774
[399]2775 /* create mixer controls */
2776 err = azx_mixer_create(chip);
[426]2777 if (err < 0)
2778 goto out_free;
[399]2779
2780 err = snd_card_register(card);
[426]2781 if (err < 0)
2782 goto out_free;
[399]2783
2784 pci_set_drvdata(pci, card);
2785 chip->running = 1;
2786 power_down_all_codecs(chip);
[402]2787 azx_notifier_register(chip);
[399]2788
2789 dev++;
2790 return err;
[426]2791out_free:
2792 snd_card_free(card);
2793 return err;
[399]2794}
2795
2796static void __devexit azx_remove(struct pci_dev *pci)
2797{
2798 snd_card_free(pci_get_drvdata(pci));
2799 pci_set_drvdata(pci, NULL);
2800}
2801
2802/* PCI IDs */
[598]2803static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2804 /* CPT */
2805 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
2806 /* PBG */
2807 { PCI_DEVICE(0x8086, 0x1d20), .driver_data = AZX_DRIVER_PCH },
[399]2808 /* SCH */
2809 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
[598]2810 /* Generic Intel */
2811 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2812 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2813 .class_mask = 0xffffff,
2814 .driver_data = AZX_DRIVER_ICH },
[399]2815 /* ATI SB 450/600 */
2816 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2817 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2818 /* ATI HDMI */
2819 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2820 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2821 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2822 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2823 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2824 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2825 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2826 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2827 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2828 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2829 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2830 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2831 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2832 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2833 /* VIA VT8251/VT8237A */
2834 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2835 /* SIS966 */
2836 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2837 /* ULI M5461 */
2838 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2839 /* NVIDIA MCP */
[520]2840 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2841 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2842 .class_mask = 0xffffff,
2843 .driver_data = AZX_DRIVER_NVIDIA },
[399]2844 /* Teradici */
2845 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
[464]2846 /* Creative X-Fi (CA0110-IBG) */
2847#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2848 /* the following entry conflicts with snd-ctxfi driver,
2849 * as ctxfi driver mutates from HD-audio to native mode with
2850 * a special command sequence.
2851 */
2852 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2853 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2854 .class_mask = 0xffffff,
[598]2855 .driver_data = AZX_DRIVER_CTX },
[464]2856#else
2857 /* this entry seems still valid -- i.e. without emu20kx chip */
[598]2858 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_CTX },
[464]2859#endif
[598]2860 /* Vortex86MX */
2861 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2862 /* VMware HDAudio */
2863 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
[464]2864 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
[426]2865 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2866 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2867 .class_mask = 0xffffff,
2868 .driver_data = AZX_DRIVER_GENERIC },
[464]2869 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2870 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2871 .class_mask = 0xffffff,
2872 .driver_data = AZX_DRIVER_GENERIC },
[399]2873 { 0, }
2874};
2875MODULE_DEVICE_TABLE(pci, azx_ids);
2876
2877/* pci_driver definition */
2878static struct pci_driver driver = {
2879 .name = "HDA Intel",
2880 .id_table = azx_ids,
2881 .probe = azx_probe,
2882 .remove = __devexit_p(azx_remove),
2883#ifdef CONFIG_PM
2884 .suspend = azx_suspend,
2885 .resume = azx_resume,
2886#endif
2887};
2888
2889static int __init alsa_card_azx_init(void)
2890{
2891 return pci_register_driver(&driver);
2892}
2893
2894static void __exit alsa_card_azx_exit(void)
2895{
2896 pci_unregister_driver(&driver);
2897}
2898
2899module_init(alsa_card_azx_init)
2900module_exit(alsa_card_azx_exit)
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