source: GPL/branches/alsa-resync1/alsa-kernel/pci/rme9652/hdsp.c@ 215

Last change on this file since 215 was 215, checked in by Brendan Oakley, 18 years ago

Merged to Alsa 0.9.0rc6
  • Property svn:eol-style set to native
File size: 88.2 KB
Line 
1/*
2 * ALSA driver for RME Hammerfall DSP audio interface(s)
3 *
4 * Copyright (c) 2002 Paul Davis
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <sound/driver.h>
23#include <asm/io.h>
24#include <asm/byteorder.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/slab.h>
28#include <linux/pci.h>
29#include <sound/core.h>
30#include <sound/control.h>
31#include <sound/pcm.h>
32#include <sound/info.h>
33#include <sound/asoundef.h>
34#include <sound/rawmidi.h>
35#define SNDRV_GET_ID
36#include <sound/initval.h>
37
38#include "multiface_firmware.dat"
39#include "digiface_firmware.dat"
40
41static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
42static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
43static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
44static int precise_ptr[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 }; /* Enable precise pointer */
45static int line_outs_monitor[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0}; /* Send all inputs/playback to line outs */
46static int force_firmware[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0}; /* Force firmware reload */
47
48MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
49MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
50MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
51MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
52MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
53MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
54MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
55MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
56MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
57MODULE_PARM(precise_ptr, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
58MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
59MODULE_PARM_SYNTAX(precise_ptr, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
60MODULE_PARM(line_outs_monitor,"1-" __MODULE_STRING(SNDRV_CARDS) "i");
61MODULE_PARM_DESC(line_outs_monitor, "Send all input and playback streams to line outs by default.");
62MODULE_PARM_SYNTAX(line_outs_monitor, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
63MODULE_PARM(force_firmware,"1-" __MODULE_STRING(SNDRV_CARDS) "i");
64MODULE_PARM_DESC(force_firmware, "Force a reload of the I/O box firmware");
65MODULE_PARM_SYNTAX(force_firmware, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
66MODULE_AUTHOR("Paul Davis <pbd@op.net>");
67MODULE_DESCRIPTION("RME Hammerfall DSP");
68MODULE_LICENSE("GPL");
69MODULE_CLASSES("{sound}");
70MODULE_DEVICES("{{RME,Hammerfall-DSP},");
71
72typedef enum {
73 Digiface,
74 Multiface
75} HDSP_Type;
76
77#define HDSP_MAX_CHANNELS 26
78#define DIGIFACE_SS_CHANNELS 26
79#define DIGIFACE_DS_CHANNELS 14
80#define MULTIFACE_SS_CHANNELS 18
81#define MULTIFACE_DS_CHANNELS 10
82
83/* Write registers. These are defined as byte-offsets from the iobase value.
84 */
85#define HDSP_resetPointer 0
86#define HDSP_outputBufferAddress 32
87#define HDSP_inputBufferAddress 36
88#define HDSP_controlRegister 64
89#define HDSP_interruptConfirmation 96
90#define HDSP_outputEnable 128
91#define HDSP_jtagReg 256
92#define HDSP_midiDataOut0 352
93#define HDSP_midiDataOut1 356
94#define HDSP_fifoData 368
95#define HDSP_inputEnable 384
96
97/* Read registers. These are defined as byte-offsets from the iobase value
98 */
99
100#define HDSP_statusRegister 0
101#define HDSP_timecode 128
102#define HDSP_status2Register 192
103#define HDSP_midiDataOut0 352
104#define HDSP_midiDataOut1 356
105#define HDSP_midiDataIn0 360
106#define HDSP_midiDataIn1 364
107#define HDSP_midiStatusOut0 384
108#define HDSP_midiStatusOut1 388
109#define HDSP_midiStatusIn0 392
110#define HDSP_midiStatusIn1 396
111#define HDSP_fifoStatus 400
112
113/* the meters are regular i/o-mapped registers, but offset
114 considerably from the rest. the peak registers are reset
115 when read; the least-significant 4 bits are full-scale counters;
116 the actual peak value is in the most-significant 24 bits.
117*/
118
119#define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
120#define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
121#define HDSP_outputPeakLevel 4100 /* 26 * 32 bit values */
122#define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
123#define HDSP_inputRmsLevel 4884 /* 26 * 64 bit values */
124
125#define HDSP_IO_EXTENT 5192
126
127/* jtag register bits */
128
129#define HDSP_TMS 0x01
130#define HDSP_TCK 0x02
131#define HDSP_TDI 0x04
132#define HDSP_JTAG 0x08
133#define HDSP_PWDN 0x10
134#define HDSP_PROGRAM 0x020
135#define HDSP_CONFIG_MODE_0 0x040
136#define HDSP_CONFIG_MODE_1 0x080
137#define HDSP_VERSION_BIT 0x100
138#define HDSP_BIGENDIAN_MODE 0x200
139#define HDSP_RD_MULTIPLE 0x400
140
141#define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
142#define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
143
144/* Control Register bits */
145
146#define HDSP_Start (1<<0) // start engine
147#define HDSP_Latency0 (1<<1) // buffer size = 2^n where n is defined by Latency{2,1,0}
148#define HDSP_Latency1 (1<<2) // [ see above ]
149#define HDSP_Latency2 (1<<3) // ] see above ]
150#define HDSP_ClockModeMaster (1<<4) // 1=Master, 0=Slave/Autosync
151#define HDSP_AudioInterruptEnable (1<<5) // what do you think ?
152#define HDSP_Frequency0 (1<<6) // 0=44.1kHz/88.2kHz 1=48kHz/96kHz
153#define HDSP_Frequency1 (1<<7) // 0=32kHz/64kHz
154#define HDSP_DoubleSpeed (1<<8) // 0=normal speed, 1=double speed
155#define HDSP_SPDIFProfessional (1<<9) // 0=consumer, 1=professional
156#define HDSP_SPDIFEmphasis (1<<10) // 0=none, 1=on
157#define HDSP_SPDIFNonAudio (1<<11) // 0=off, 1=on
158#define HDSP_SPDIFOpticalOut (1<<12) // 1=use 1st ADAT connector for SPDIF, 0=do not
159#define HDSP_SyncRef2 (1<<13)
160#define HDSP_SPDIFInputSelect0 (1<<14)
161#define HDSP_SPDIFInputSelect1 (1<<15)
162#define HDSP_SyncRef0 (1<<16)
163#define HDSP_SyncRef1 (1<<17)
164#define HDSP_Midi0InterruptEnable (1<<22)
165#define HDSP_Midi1InterruptEnable (1<<23)
166#define HDSP_LineOut (1<<24)
167
168#define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
169#define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed)
170
171#define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
172#define HDSP_SPDIFInputADAT1 0
173#define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect1)
174#define HDSP_SPDIFInputCDROM (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
175
176#define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
177#define HDSP_SyncRef_ADAT1 0
178#define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
179#define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
180#define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
181#define HDSP_SyncRef_WORD (HDSP_SyncRef2)
182#define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
183
184/* Preferred sync source choices - used by "sync_pref" control switch */
185
186#define HDSP_SYNC_FROM_SELF 0
187#define HDSP_SYNC_FROM_WORD 1
188#define HDSP_SYNC_FROM_ADAT_SYNC 2
189#define HDSP_SYNC_FROM_SPDIF 3
190#define HDSP_SYNC_FROM_ADAT1 4
191#define HDSP_SYNC_FROM_ADAT2 5
192#define HDSP_SYNC_FROM_ADAT3 6
193
194/* Possible sources of S/PDIF input */
195
196#define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
197#define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
198#define HDSP_SPDIFIN_INTERN 2 /* internal (CDROM) */
199
200#define HDSP_Frequency32KHz HDSP_Frequency0
201#define HDSP_Frequency44_1KHz HDSP_Frequency1
202#define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
203#define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
204#define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
205#define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
206
207#define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
208#define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
209
210#define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
211#define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
212
213/* Status Register bits */
214
215#define HDSP_audioIRQPending (1<<0)
216#define HDSP_Lock2 (1<<1)
217#define HDSP_Lock1 (1<<2)
218#define HDSP_Lock0 (1<<3)
219#define HDSP_SPDIFSync (1<<4)
220#define HDSP_TimecodeLock (1<<5)
221#define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
222#define HDSP_Sync2 (1<<16)
223#define HDSP_Sync1 (1<<17)
224#define HDSP_Sync0 (1<<18)
225#define HDSP_DoubleSpeedStatus (1<<19)
226#define HDSP_ConfigError (1<<20)
227#define HDSP_DllError (1<<21)
228#define HDSP_spdifFrequency0 (1<<22)
229#define HDSP_spdifFrequency1 (1<<23)
230#define HDSP_spdifFrequency2 (1<<24)
231#define HDSP_SPDIFErrorFlag (1<<25)
232#define HDSP_BufferID (1<<26)
233#define HDSP_TimecodeSync (1<<27)
234#define HDSP_CIN (1<<28)
235#define HDSP_midi0IRQPending (1<<30) /* notice the gap at bit 29 */
236#define HDSP_midi1IRQPending (1<<31)
237
238#define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
239
240#define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
241#define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
242#define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
243
244#define HDSP_spdifFrequency64KHz 0
245#define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency2)
246#define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
247
248/* Status2 Register bits */
249
250#define HDSP_version0 (1<<0)
251#define HDSP_version1 (1<<1)
252#define HDSP_version2 (1<<2)
253#define HDSP_wc_lock (1<<3)
254#define HDSP_wc_sync (1<<4)
255#define HDSP_inp_freq0 (1<<5)
256#define HDSP_inp_freq1 (1<<6)
257#define HDSP_inp_freq2 (1<<7)
258#define HDSP_SelSyncRef0 (1<<8)
259#define HDSP_SelSyncRef1 (1<<9)
260#define HDSP_SelSyncRef2 (1<<10)
261
262#define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
263
264#define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
265#define HDSP_systemFrequency32 (HDSP_inp_freq0)
266#define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
267#define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
268#define HDSP_systemFrequency64 (HDSP_inp_freq2)
269#define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
270#define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
271
272#define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
273#define HDSP_SelSyncRef_ADAT1 0
274#define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
275#define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
276#define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
277#define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
278#define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
279
280/* FIFO wait times, defined in terms of loops on readl() */
281
282#define HDSP_LONG_WAIT 40000
283#define HDSP_SHORT_WAIT 100
284
285/* Computing addresses for adjusting gains */
286
287#define INPUT_TO_OUTPUT_KEY(in,out) ((64 * (out)) + (in))
288#define PLAYBACK_TO_OUTPUT_KEY(chn,out) ((64 * (out)) + 32 + (chn))
289#define UNITY_GAIN 32768
290#define MINUS_INFINITY_GAIN 0
291
292#ifndef PCI_VENDOR_ID_XILINX
293#define PCI_VENDOR_ID_XILINX 0x10ee
294#endif
295#ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
296#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
297#endif
298
299/* the size of a substream (1 mono data stream) */
300
301#define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
302#define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
303
304/* the size of the area we need to allocate for DMA transfers. the
305 size is the same regardless of the number of channels - the
306 Multiface still uses the same memory area.
307
308 Note that we allocate 1 more channel than is apparently needed
309 because the h/w seems to write 1 byte beyond the end of the last
310 page. Sigh.
311*/
312
313#define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
314#define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
315
316#define HDSP_MATRIX_MIXER_SIZE 2048
317
318typedef struct _hdsp hdsp_t;
319typedef struct _hdsp_midi hdsp_midi_t;
320
321struct _hdsp_midi {
322 hdsp_t *hdsp;
323 int id;
324 snd_rawmidi_t *rmidi;
325 snd_rawmidi_substream_t *input;
326 snd_rawmidi_substream_t *output;
327 char istimer; /* timer in use */
328 struct timer_list timer;
329 spinlock_t lock;
330};
331
332struct _hdsp {
333 spinlock_t lock;
334 snd_pcm_substream_t *capture_substream;
335 snd_pcm_substream_t *playback_substream;
336 hdsp_midi_t midi[2];
337 int precise_ptr;
338 u32 control_register; /* cached value */
339 u32 creg_spdif;
340 u32 creg_spdif_stream;
341 char *card_name; /* digiface/multiface */
342 HDSP_Type type; /* ditto, but for code use */
343 size_t period_bytes; /* guess what this is */
344 unsigned char ds_channels;
345 unsigned char ss_channels; /* different for multiface/digiface */
346 void *capture_buffer_unaligned; /* original buffer addresses */
347 void *playback_buffer_unaligned; /* original buffer addresses */
348 unsigned char *capture_buffer; /* suitably aligned address */
349 unsigned char *playback_buffer; /* suitably aligned address */
350 dma_addr_t capture_buffer_addr;
351 dma_addr_t playback_buffer_addr;
352 pid_t capture_pid;
353 pid_t playback_pid;
354 int running;
355 int passthru; /* non-zero if doing pass-thru */
356 int last_spdif_sample_rate; /* so that we can catch externally ... */
357 int last_adat_sample_rate; /* ... induced rate changes */
358 char *channel_map;
359 int dev;
360 int irq;
361 unsigned long port;
362 struct resource *res_port;
363 unsigned long iobase;
364 snd_card_t *card;
365 snd_pcm_t *pcm;
366 struct pci_dev *pci;
367 snd_info_entry_t *proc_entry;
368 snd_kcontrol_t *spdif_ctl;
369 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
370};
371
372/* These tables map the ALSA channels 1..N to the channels that we
373 need to use in order to find the relevant channel buffer. RME
374 refer to this kind of mapping as between "the ADAT channel and
375 the DMA channel." We index it using the logical audio channel,
376 and the value is the DMA channel (i.e. channel buffer number)
377 where the data for that channel can be read/written from/to.
378*/
379
380static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
381 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
382 18, 19, 20, 21, 22, 23, 24, 25
383};
384
385static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
386 /* ADAT 0 */
387 0, 1, 2, 3, 4, 5, 6, 7,
388 /* ADAT 2 */
389 16, 17, 18, 19, 20, 21, 22, 23,
390 /* SPDIF */
391 24, 25,
392 -1, -1, -1, -1, -1, -1, -1, -1,
393};
394
395static char channel_map_ds[HDSP_MAX_CHANNELS] = {
396 /* ADAT channels are remapped */
397 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
398 /* channels 12 and 13 are S/PDIF */
399 24, 25,
400 /* others don't exist */
401 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
402};
403
404#define HDSP_PREALLOCATE_MEMORY /* via module snd-hdsp_mem */
405
406#ifdef HDSP_PREALLOCATE_MEMORY
407extern void *snd_hammerfall_get_buffer(struct pci_dev *, dma_addr_t *dmaaddr);
408extern void snd_hammerfall_free_buffer(struct pci_dev *, void *ptr);
409#endif
410
411static struct pci_device_id snd_hdsp_ids[] __devinitdata = {
412 {PCI_VENDOR_ID_XILINX,
413 PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, /* RME Hammerfall-DSP */
415 {0,}
416};
417
418MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
419
420static inline void hdsp_write(hdsp_t *hdsp, int reg, int val)
421{
422 writel(val, hdsp->iobase + reg);
423}
424
425static inline unsigned int hdsp_read(hdsp_t *hdsp, int reg)
426{
427 return readl (hdsp->iobase + reg);
428}
429
430static inline unsigned long long hdsp_read64 (hdsp_t *hdsp, int reg)
431{
432 unsigned long long val;
433 val = hdsp_read(hdsp, reg);
434 val = (val<<32)|hdsp_read(hdsp, reg + 4);
435
436 return val;
437}
438
439static inline int hdsp_check_for_iobox (hdsp_t *hdsp)
440{
441 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
442 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
443 return -EIO;
444 }
445 return 0;
446}
447
448static inline int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout)
449{
450 int i;
451
452 /* the fifoStatus registers reports on how many words
453 are available in the command FIFO.
454 */
455
456 for (i = 0; i < timeout; i++)
457 if ((hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
458 return 0;
459
460 snd_printk ("wait for FIFO status <= %d failed after %d iterations\n",
461 count, timeout);
462 return -1;
463}
464
465static inline int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr)
466{
467 if (addr >= HDSP_MATRIX_MIXER_SIZE) {
468 return 0;
469 }
470 return hdsp->mixer_matrix[addr];
471}
472
473static inline int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data)
474{
475 unsigned int ad;
476
477 if (addr >= HDSP_MATRIX_MIXER_SIZE)
478 return -1;
479
480 ad = data + addr * 65536;
481
482 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) {
483 return -1;
484 }
485 hdsp_write (hdsp, HDSP_fifoData, ad);
486 hdsp->mixer_matrix[addr] = data;
487
488 return 0;
489}
490
491static inline int snd_hdsp_use_is_exclusive(hdsp_t *hdsp)
492{
493 unsigned long flags;
494 int ret = 1;
495
496 spin_lock_irqsave(&hdsp->lock, flags);
497 if ((hdsp->playback_pid != hdsp->capture_pid) &&
498 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) {
499 ret = 0;
500 }
501 spin_unlock_irqrestore(&hdsp->lock, flags);
502 return ret;
503}
504
505static inline int hdsp_system_sample_rate (hdsp_t *hdsp)
506{
507 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
508 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
509
510 switch (rate_bits) {
511 case HDSP_systemFrequency32: return 32000;
512 case HDSP_systemFrequency44_1: return 44100;
513 case HDSP_systemFrequency48: return 48000;
514 case HDSP_systemFrequency64: return 64000;
515 case HDSP_systemFrequency88_2: return 88200;
516 case HDSP_systemFrequency96: return 96000;
517 default: return 0;
518 }
519}
520
521static inline int hdsp_spdif_sample_rate(hdsp_t *hdsp)
522{
523 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
524 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
525
526 if (status & HDSP_SPDIFErrorFlag) {
527 return 0;
528 }
529
530 switch (rate_bits) {
531 case HDSP_spdifFrequency32KHz: return 32000;
532 case HDSP_spdifFrequency44_1KHz: return 44100;
533 case HDSP_spdifFrequency48KHz: return 48000;
534 case HDSP_spdifFrequency64KHz: return 64000;
535 case HDSP_spdifFrequency88_2KHz: return 88200;
536 case HDSP_spdifFrequency96KHz: return 96000;
537 default:
538 snd_printk ("unknown frequency status; bits = 0x%x, status = 0x%x", rate_bits, status);
539 return 0;
540 }
541}
542
543static inline void hdsp_compute_period_size(hdsp_t *hdsp)
544{
545 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
546}
547
548static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp)
549{
550 int position;
551
552 position = hdsp_read(hdsp, HDSP_statusRegister);
553
554 if (!hdsp->precise_ptr) {
555 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
556 }
557
558 position &= HDSP_BufferPositionMask;
559 position /= 4;
560 position -= 32;
561 position &= (HDSP_CHANNEL_BUFFER_SAMPLES-1);
562 return position;
563}
564
565static inline void hdsp_reset_hw_pointer(hdsp_t *hdsp)
566{
567#if 0
568 /* reset the hw pointer to zero. We do this by writing to 8
569 registers, each of which is a 32bit wide register, and set
570 them all to zero.
571 */
572
573 for (i = 0; i < 8; ++i) {
574 hdsp_write(hdsp, i, 0);
575 udelay(10);
576 }
577#endif
578}
579
580static inline void hdsp_start_audio(hdsp_t *s)
581{
582 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
583 hdsp_write(s, HDSP_controlRegister, s->control_register);
584}
585
586static inline void hdsp_stop_audio(hdsp_t *s)
587{
588 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
589 hdsp_write(s, HDSP_controlRegister, s->control_register);
590}
591
592static inline void hdsp_silence_playback(hdsp_t *hdsp)
593{
594 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
595}
596
597static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames)
598{
599 int n;
600
601 spin_lock_irq(&s->lock);
602
603 frames >>= 7;
604 n = 0;
605 while (frames) {
606 n++;
607 frames >>= 1;
608 }
609
610 s->control_register &= ~HDSP_LatencyMask;
611 s->control_register |= hdsp_encode_latency(n);
612
613 hdsp_write(s, HDSP_controlRegister, s->control_register);
614
615 hdsp_compute_period_size(s);
616
617 spin_unlock_irq(&s->lock);
618
619 return 0;
620}
621
622static int hdsp_set_rate(hdsp_t *hdsp, int rate)
623{
624 int reject_if_open = 0;
625 int current_rate;
626
627 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
628 snd_printk ("device is not running as a clock master: cannot set sample rate.\n");
629 return -1;
630 }
631
632 /* Changing from a "single speed" to a "double speed" rate is
633 not allowed if any substreams are open. This is because
634 such a change causes a shift in the location of
635 the DMA buffers and a reduction in the number of available
636 buffers.
637
638 Note that a similar but essentially insoluble problem
639 exists for externally-driven rate changes. All we can do
640 is to flag rate changes in the read/write routines.
641 */
642
643 spin_lock_irq(&hdsp->lock);
644 current_rate = hdsp_system_sample_rate(hdsp);
645
646 switch (rate) {
647 case 32000:
648 if (current_rate > 48000) {
649 reject_if_open = 1;
650 }
651 rate = HDSP_Frequency32KHz;
652 break;
653 case 44100:
654 if (current_rate > 48000) {
655 reject_if_open = 1;
656 }
657 rate = HDSP_Frequency44_1KHz;
658 break;
659 case 48000:
660 if (current_rate > 48000) {
661 reject_if_open = 1;
662 }
663 rate = HDSP_Frequency48KHz;
664 break;
665 case 64000:
666 if (current_rate < 48000) {
667 reject_if_open = 1;
668 }
669 rate = HDSP_Frequency64KHz;
670 break;
671 case 88200:
672 if (current_rate < 48000) {
673 reject_if_open = 1;
674 }
675 rate = HDSP_Frequency88_2KHz;
676 break;
677 case 96000:
678 if (current_rate < 48000) {
679 reject_if_open = 1;
680 }
681 rate = HDSP_Frequency96KHz;
682 break;
683 default:
684 return -EINVAL;
685 }
686
687 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
688 snd_printk ("cannot change between single- and double-speed mode (capture PID = %d, playback PID = %d)\n",
689 hdsp->capture_pid,
690 hdsp->playback_pid);
691 spin_unlock_irq(&hdsp->lock);
692 return -EBUSY;
693 }
694
695 hdsp->control_register &= ~HDSP_FrequencyMask;
696 hdsp->control_register |= rate;
697 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
698
699 if (rate > 48000) {
700 hdsp->channel_map = channel_map_ds;
701 } else {
702 switch (hdsp->type) {
703 case Multiface:
704 hdsp->channel_map = channel_map_mf_ss;
705 break;
706 case Digiface:
707 hdsp->channel_map = channel_map_df_ss;
708 break;
709 }
710 }
711
712 spin_unlock_irq(&hdsp->lock);
713 return 0;
714}
715
716static void hdsp_set_thru(hdsp_t *hdsp, int channel, int enable)
717{
718
719 hdsp->passthru = 0;
720
721 if (channel < 0) {
722
723 int i;
724
725 /* set thru for all channels */
726
727 if (enable) {
728 for (i = 0; i < 26; i++) {
729 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY(i,i), UNITY_GAIN);
730 }
731 } else {
732 for (i = 0; i < 26; i++) {
733 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY(i,i), MINUS_INFINITY_GAIN);
734 }
735 }
736
737 } else {
738 int mapped_channel;
739
740 snd_assert(channel < HDSP_MAX_CHANNELS, return);
741
742 mapped_channel = hdsp->channel_map[channel];
743
744 if (enable) {
745 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY(channel,channel), UNITY_GAIN);
746 } else {
747 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY(channel,channel), MINUS_INFINITY_GAIN);
748 }
749 }
750}
751
752static int hdsp_set_passthru(hdsp_t *hdsp, int onoff)
753{
754 if (onoff) {
755 hdsp_set_thru(hdsp, -1, 1);
756 hdsp_reset_hw_pointer(hdsp);
757 hdsp_silence_playback(hdsp);
758
759 /* we don't want interrupts, so do a
760 custom version of hdsp_start_audio().
761 */
762
763 hdsp->control_register |= (HDSP_Start|HDSP_AudioInterruptEnable|hdsp_encode_latency(7));
764
765 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
766 hdsp->passthru = 1;
767 } else {
768 hdsp_set_thru(hdsp, -1, 0);
769 hdsp_stop_audio(hdsp);
770 hdsp->passthru = 0;
771 }
772
773 return 0;
774}
775
776/*----------------------------------------------------------------------------
777 MIDI
778 ----------------------------------------------------------------------------*/
779
780static inline unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id)
781{
782 /* the hardware already does the relevant bit-mask with 0xff */
783 if (id) {
784 return hdsp_read(hdsp, HDSP_midiDataIn1);
785 } else {
786 return hdsp_read(hdsp, HDSP_midiDataIn0);
787 }
788}
789
790static inline void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val)
791{
792 /* the hardware already does the relevant bit-mask with 0xff */
793 if (id) {
794 return hdsp_write(hdsp, HDSP_midiDataOut1, val);
795 } else {
796 return hdsp_write(hdsp, HDSP_midiDataOut0, val);
797 }
798}
799
800static inline int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id)
801{
802 if (id) {
803 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
804 } else {
805 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
806 }
807}
808
809static inline int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id)
810{
811 if (id) {
812 return (hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff) < 128;
813 } else {
814 return (hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff)< 128;
815 }
816}
817
818static inline void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id)
819{
820 while (snd_hdsp_midi_input_available (hdsp, id)) {
821 snd_hdsp_midi_read_byte (hdsp, id);
822 }
823}
824
825static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi)
826{
827 unsigned long flags;
828 int n_pending;
829 int clear_timer = 0;
830 int to_write;
831 int i;
832 unsigned char buf[128];
833
834 /* Output is not interrupt driven */
835
836 spin_lock_irqsave (&hmidi->lock, flags);
837
838 if (hmidi->output) {
839 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
840 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
841 if (n_pending > sizeof (buf))
842 n_pending = sizeof (buf);
843
844 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
845 for (i = 0; i < to_write; ++i)
846 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
847 } else {
848 clear_timer = 1;
849 }
850 }
851 } else {
852 clear_timer = 1;
853 }
854
855 if (clear_timer && hmidi->istimer && --hmidi->istimer <= 0) {
856 del_timer(&hmidi->timer);
857 }
858 }
859
860 spin_unlock_irqrestore (&hmidi->lock, flags);
861 return 0;
862}
863
864static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi)
865{
866 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
867 unsigned long flags;
868 int n_pending;
869 int i;
870
871 spin_lock_irqsave (&hmidi->lock, flags);
872
873 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
874 if (hmidi->input) {
875 if (n_pending > sizeof (buf)) {
876 n_pending = sizeof (buf);
877 }
878 for (i = 0; i < n_pending; ++i) {
879 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
880 }
881 if (n_pending) {
882 snd_rawmidi_receive (hmidi->input, buf, n_pending);
883 }
884 } else {
885 /* flush the MIDI input FIFO */
886 while (--n_pending) {
887 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
888 }
889 }
890 }
891 spin_unlock_irqrestore (&hmidi->lock, flags);
892 return snd_hdsp_midi_output_write (hmidi);
893}
894
895static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
896{
897 hdsp_t *hdsp;
898 hdsp_midi_t *hmidi;
899 unsigned long flags;
900
901 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
902 hdsp = hmidi->hdsp;
903 spin_lock_irqsave (&hdsp->lock, flags);
904 if (up) {
905 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
906 if (hmidi->id)
907 hdsp->control_register |= HDSP_Midi1InterruptEnable;
908 else
909 hdsp->control_register |= HDSP_Midi0InterruptEnable;
910 } else {
911 if (hmidi->id)
912 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
913 else
914 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
915 }
916
917 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
918 spin_unlock_irqrestore (&hdsp->lock, flags);
919}
920
921static void snd_hdsp_midi_output_timer(unsigned long data)
922{
923 hdsp_midi_t *hmidi = (hdsp_midi_t *) data;
924 unsigned long flags;
925
926 snd_hdsp_midi_output_write(hmidi);
927 spin_lock_irqsave (&hmidi->lock, flags);
928
929 /* this does not bump hmidi->istimer, because the
930 kernel automatically removed the timer when it
931 expired, and we are now adding it back, thus
932 leaving istimer wherever it was set before.
933 */
934
935 if (hmidi->istimer) {
936 hmidi->timer.expires = 1 + jiffies;
937 add_timer(&hmidi->timer);
938 }
939
940 spin_unlock_irqrestore (&hmidi->lock, flags);
941}
942
943static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
944{
945 hdsp_midi_t *hmidi;
946 unsigned long flags;
947
948 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
949 spin_lock_irqsave (&hmidi->lock, flags);
950 if (up) {
951 if (!hmidi->istimer) {
952 init_timer(&hmidi->timer);
953 hmidi->timer.function = snd_hdsp_midi_output_timer;
954 hmidi->timer.data = (unsigned long) hmidi;
955 hmidi->timer.expires = 1 + jiffies;
956 add_timer(&hmidi->timer);
957 hmidi->istimer++;
958 }
959 } else {
960 if (hmidi->istimer && --hmidi->istimer <= 0) {
961 del_timer (&hmidi->timer);
962 }
963 }
964 spin_unlock_irqrestore (&hmidi->lock, flags);
965}
966
967static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream)
968{
969 hdsp_midi_t *hmidi;
970 unsigned long flags;
971
972 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
973 spin_lock_irqsave (&hmidi->lock, flags);
974 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
975 hmidi->input = substream;
976 spin_unlock_irqrestore (&hmidi->lock, flags);
977
978 return 0;
979}
980
981static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream)
982{
983 hdsp_midi_t *hmidi;
984 unsigned long flags;
985
986 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
987 spin_lock_irqsave (&hmidi->lock, flags);
988 hmidi->output = substream;
989 spin_unlock_irqrestore (&hmidi->lock, flags);
990
991 return 0;
992}
993
994static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream)
995{
996 hdsp_midi_t *hmidi;
997 unsigned long flags;
998
999 snd_hdsp_midi_input_trigger (substream, 0);
1000
1001 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1002 spin_lock_irqsave (&hmidi->lock, flags);
1003 hmidi->input = NULL;
1004 spin_unlock_irqrestore (&hmidi->lock, flags);
1005
1006 return 0;
1007}
1008
1009static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream)
1010{
1011 hdsp_midi_t *hmidi;
1012 unsigned long flags;
1013
1014 snd_hdsp_midi_output_trigger (substream, 0);
1015
1016 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1017 spin_lock_irqsave (&hmidi->lock, flags);
1018 hmidi->output = NULL;
1019 spin_unlock_irqrestore (&hmidi->lock, flags);
1020
1021 return 0;
1022}
1023
1024snd_rawmidi_ops_t snd_hdsp_midi_output =
1025{
1026 .open = snd_hdsp_midi_output_open,
1027 .close = snd_hdsp_midi_output_close,
1028 .trigger = snd_hdsp_midi_output_trigger,
1029};
1030
1031snd_rawmidi_ops_t snd_hdsp_midi_input =
1032{
1033 .open = snd_hdsp_midi_input_open,
1034 .close = snd_hdsp_midi_input_close,
1035 .trigger = snd_hdsp_midi_input_trigger,
1036};
1037
1038static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id)
1039{
1040 char buf[32];
1041
1042 hdsp->midi[id].id = id;
1043 hdsp->midi[id].rmidi = NULL;
1044 hdsp->midi[id].input = NULL;
1045 hdsp->midi[id].output = NULL;
1046 hdsp->midi[id].hdsp = hdsp;
1047 hdsp->midi[id].istimer = 0;
1048 spin_lock_init (&hdsp->midi[id].lock);
1049
1050 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1051 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) {
1052 return -1;
1053 }
1054
1055 sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1056 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1057
1058 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1059 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1060
1061 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1062 SNDRV_RAWMIDI_INFO_INPUT |
1063 SNDRV_RAWMIDI_INFO_DUPLEX;
1064
1065 return 0;
1066}
1067
1068/*-----------------------------------------------------------------------------
1069 Control Interface
1070 ----------------------------------------------------------------------------*/
1071
1072static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes)
1073{
1074 u32 val = 0;
1075 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1076 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1077 if (val & HDSP_SPDIFProfessional)
1078 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1079 else
1080 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1081 return val;
1082}
1083
1084static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
1085{
1086 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1087 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1088 if (val & HDSP_SPDIFProfessional)
1089 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1090 else
1091 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1092}
1093
1094static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1095{
1096 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1097 uinfo->count = 1;
1098 return 0;
1099}
1100
1101static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1102{
1103 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1104
1105 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1106 return 0;
1107}
1108
1109static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1110{
1111 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1112 unsigned long flags;
1113 int change;
1114 u32 val;
1115
1116 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1117 spin_lock_irqsave(&hdsp->lock, flags);
1118 change = val != hdsp->creg_spdif;
1119 hdsp->creg_spdif = val;
1120 spin_unlock_irqrestore(&hdsp->lock, flags);
1121 return change;
1122}
1123
1124static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1125{
1126 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1127 uinfo->count = 1;
1128 return 0;
1129}
1130
1131static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1132{
1133 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1134
1135 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1136 return 0;
1137}
1138
1139static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1140{
1141 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1142 unsigned long flags;
1143 int change;
1144 u32 val;
1145
1146 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1147 spin_lock_irqsave(&hdsp->lock, flags);
1148 change = val != hdsp->creg_spdif_stream;
1149 hdsp->creg_spdif_stream = val;
1150 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1151 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1152 spin_unlock_irqrestore(&hdsp->lock, flags);
1153 return change;
1154}
1155
1156static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1157{
1158 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1159 uinfo->count = 1;
1160 return 0;
1161}
1162
1163static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1164{
1165 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1166 return 0;
1167}
1168
1169#define HDSP_SPDIF_IN(xname, xindex) \
1170{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1171 .info = snd_hdsp_info_spdif_in, \
1172 .get = snd_hdsp_get_spdif_in, .put = snd_hdsp_put_spdif_in }
1173
1174static unsigned int hdsp_spdif_in(hdsp_t *hdsp)
1175{
1176 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1177}
1178
1179static int hdsp_set_spdif_input(hdsp_t *hdsp, int in)
1180{
1181 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1182 hdsp->control_register |= hdsp_encode_spdif_in(in);
1183 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1184 return 0;
1185}
1186
1187static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1188{
1189 static char *texts[3] = {"ADAT1", "Coaxial", "Internal"};
1190
1191 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1192 uinfo->count = 1;
1193 uinfo->value.enumerated.items = 3;
1194 if (uinfo->value.enumerated.item > 2)
1195 uinfo->value.enumerated.item = 2;
1196 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1197 return 0;
1198}
1199
1200static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1201{
1202 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1203 unsigned long flags;
1204
1205 spin_lock_irqsave(&hdsp->lock, flags);
1206 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1207 spin_unlock_irqrestore(&hdsp->lock, flags);
1208 return 0;
1209}
1210
1211static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1212{
1213 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1214 unsigned long flags;
1215 int change;
1216 unsigned int val;
1217
1218 if (!snd_hdsp_use_is_exclusive(hdsp))
1219 return -EBUSY;
1220 val = ucontrol->value.enumerated.item[0] % 3;
1221 spin_lock_irqsave(&hdsp->lock, flags);
1222 change = val != hdsp_spdif_in(hdsp);
1223 if (change)
1224 hdsp_set_spdif_input(hdsp, val);
1225 spin_unlock_irqrestore(&hdsp->lock, flags);
1226 return change;
1227}
1228
1229#define HDSP_SPDIF_OUT(xname, xindex) \
1230{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1231 .info = snd_hdsp_info_spdif_out, \
1232 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1233
1234static int hdsp_spdif_out(hdsp_t *hdsp)
1235{
1236 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1237}
1238
1239static int hdsp_set_spdif_output(hdsp_t *hdsp, int out)
1240{
1241 if (out) {
1242 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1243 } else {
1244 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1245 }
1246 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1247 return 0;
1248}
1249
1250static int snd_hdsp_info_spdif_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1251{
1252 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1253 uinfo->count = 1;
1254 uinfo->value.integer.min = 0;
1255 uinfo->value.integer.max = 1;
1256 return 0;
1257}
1258
1259static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1260{
1261 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1262 unsigned long flags;
1263
1264 spin_lock_irqsave(&hdsp->lock, flags);
1265 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1266 spin_unlock_irqrestore(&hdsp->lock, flags);
1267 return 0;
1268}
1269
1270static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1271{
1272 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1273 unsigned long flags;
1274 int change;
1275 unsigned int val;
1276
1277 if (!snd_hdsp_use_is_exclusive(hdsp))
1278 return -EBUSY;
1279 val = ucontrol->value.integer.value[0] & 1;
1280 spin_lock_irqsave(&hdsp->lock, flags);
1281 change = val != hdsp_spdif_out(hdsp);
1282 hdsp_set_spdif_output(hdsp, val);
1283 spin_unlock_irqrestore(&hdsp->lock, flags);
1284 return change;
1285}
1286
1287#define HDSP_SYNC_PREF(xname, xindex) \
1288{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1289 .info = snd_hdsp_info_sync_pref, \
1290 .get = snd_hdsp_get_sync_pref, .put = snd_hdsp_put_sync_pref }
1291
1292static int hdsp_sync_pref(hdsp_t *hdsp)
1293{
1294 /* Notice that this looks at the requested sync source,
1295 not the one actually in use.
1296 */
1297
1298 if (hdsp->control_register & HDSP_ClockModeMaster) {
1299 return HDSP_SYNC_FROM_SELF;
1300 }
1301
1302 switch (hdsp->control_register & HDSP_SyncRefMask) {
1303 case HDSP_SyncRef_ADAT1:
1304 return HDSP_SYNC_FROM_ADAT1;
1305 case HDSP_SyncRef_ADAT2:
1306 return HDSP_SYNC_FROM_ADAT2;
1307 case HDSP_SyncRef_ADAT3:
1308 return HDSP_SYNC_FROM_ADAT3;
1309 case HDSP_SyncRef_SPDIF:
1310 return HDSP_SYNC_FROM_SPDIF;
1311 case HDSP_SyncRef_WORD:
1312 return HDSP_SYNC_FROM_WORD;
1313 case HDSP_SyncRef_ADAT_SYNC:
1314 return HDSP_SYNC_FROM_ADAT_SYNC;
1315 default:
1316 return HDSP_SYNC_FROM_SELF;
1317 }
1318 return 0;
1319}
1320
1321static int hdsp_set_sync_pref(hdsp_t *hdsp, int pref)
1322{
1323 hdsp->control_register &= ~HDSP_SyncRefMask;
1324 switch (pref) {
1325 case HDSP_SYNC_FROM_ADAT1:
1326 hdsp->control_register &= ~HDSP_ClockModeMaster;
1327 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
1328 break;
1329 case HDSP_SYNC_FROM_ADAT2:
1330 hdsp->control_register &= ~HDSP_ClockModeMaster;
1331 hdsp->control_register |= HDSP_SyncRef_ADAT2;
1332 break;
1333 case HDSP_SYNC_FROM_ADAT3:
1334 hdsp->control_register &= ~HDSP_ClockModeMaster;
1335 hdsp->control_register |= HDSP_SyncRef_ADAT3;
1336 break;
1337 case HDSP_SYNC_FROM_SPDIF:
1338 hdsp->control_register &= ~HDSP_ClockModeMaster;
1339 hdsp->control_register |= HDSP_SyncRef_SPDIF;
1340 break;
1341 case HDSP_SYNC_FROM_WORD:
1342 hdsp->control_register &= ~HDSP_ClockModeMaster;
1343 hdsp->control_register |= HDSP_SyncRef_WORD;
1344 break;
1345 case HDSP_SYNC_FROM_ADAT_SYNC:
1346 hdsp->control_register &= ~HDSP_ClockModeMaster;
1347 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
1348 break;
1349 case HDSP_SYNC_FROM_SELF:
1350 hdsp->control_register |= HDSP_ClockModeMaster;
1351 break;
1352 default:
1353 return -1;
1354 }
1355 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1356 return 0;
1357}
1358
1359static int snd_hdsp_info_sync_pref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1360{
1361 static char *texts[] = {"Internal", "Word", "ADAT Sync", "IEC958", "ADAT1", "ADAT2", "ADAT3" };
1362 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1363
1364 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1365 uinfo->count = 1;
1366 uinfo->value.enumerated.items = (hdsp->type == Digiface) ? 7 : 6;
1367 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1368 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1369 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1370 return 0;
1371}
1372
1373static int snd_hdsp_get_sync_pref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1374{
1375 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1376 unsigned long flags;
1377
1378 spin_lock_irqsave(&hdsp->lock, flags);
1379 ucontrol->value.enumerated.item[0] = hdsp_sync_pref(hdsp);
1380 spin_unlock_irqrestore(&hdsp->lock, flags);
1381 return 0;
1382}
1383
1384static int snd_hdsp_put_sync_pref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1385{
1386 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1387 unsigned long flags;
1388 int change, max;
1389 unsigned int val;
1390
1391 if (!snd_hdsp_use_is_exclusive(hdsp))
1392 return -EBUSY;
1393 max = hdsp->ss_channels == (hdsp->type == Digiface) ? 7 : 6;
1394 val = ucontrol->value.enumerated.item[0] % max;
1395 spin_lock_irqsave(&hdsp->lock, flags);
1396 change = val != hdsp_sync_pref(hdsp);
1397 hdsp_set_sync_pref(hdsp, val);
1398 spin_unlock_irqrestore(&hdsp->lock, flags);
1399 return change;
1400}
1401
1402#define HDSP_PASSTHRU(xname, xindex) \
1403{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1404 .info = snd_hdsp_info_passthru, \
1405 .put = snd_hdsp_put_passthru, \
1406 .get = snd_hdsp_get_passthru }
1407
1408static int snd_hdsp_info_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1409{
1410 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1411 uinfo->count = 1;
1412 uinfo->value.integer.min = 0;
1413 uinfo->value.integer.max = 1;
1414 return 0;
1415}
1416
1417static int snd_hdsp_get_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1418{
1419 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1420 unsigned long flags;
1421
1422 spin_lock_irqsave(&hdsp->lock, flags);
1423 ucontrol->value.integer.value[0] = hdsp->passthru;
1424 spin_unlock_irqrestore(&hdsp->lock, flags);
1425 return 0;
1426}
1427
1428static int snd_hdsp_put_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1429{
1430 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1431 unsigned long flags;
1432 int change;
1433 unsigned int val;
1434 int err = 0;
1435
1436 if (!snd_hdsp_use_is_exclusive(hdsp))
1437 return -EBUSY;
1438
1439 val = ucontrol->value.integer.value[0] & 1;
1440 spin_lock_irqsave(&hdsp->lock, flags);
1441 change = (ucontrol->value.integer.value[0] != hdsp->passthru);
1442 if (change)
1443 err = hdsp_set_passthru(hdsp, val);
1444 spin_unlock_irqrestore(&hdsp->lock, flags);
1445 return err ? err : change;
1446}
1447
1448#define HDSP_LINE_OUT(xname, xindex) \
1449{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1450 .info = snd_hdsp_info_line_out, \
1451 .get = snd_hdsp_get_line_out, .put = snd_hdsp_put_line_out }
1452
1453static int hdsp_line_out(hdsp_t *hdsp)
1454{
1455 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
1456}
1457
1458static int hdsp_set_line_output(hdsp_t *hdsp, int out)
1459{
1460 if (out) {
1461 hdsp->control_register |= HDSP_LineOut;
1462 } else {
1463 hdsp->control_register &= ~HDSP_LineOut;
1464 }
1465 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1466 return 0;
1467}
1468
1469static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1470{
1471 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1472 uinfo->count = 1;
1473 uinfo->value.integer.min = 0;
1474 uinfo->value.integer.max = 1;
1475 return 0;
1476}
1477
1478static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1479{
1480 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1481 unsigned long flags;
1482
1483 spin_lock_irqsave(&hdsp->lock, flags);
1484 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
1485 spin_unlock_irqrestore(&hdsp->lock, flags);
1486 return 0;
1487}
1488
1489static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1490{
1491 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1492 unsigned long flags;
1493 int change;
1494 unsigned int val;
1495
1496 if (!snd_hdsp_use_is_exclusive(hdsp))
1497 return -EBUSY;
1498 val = ucontrol->value.integer.value[0] & 1;
1499 spin_lock_irqsave(&hdsp->lock, flags);
1500 change = val != hdsp_line_out(hdsp);
1501 hdsp_set_line_output(hdsp, val);
1502 spin_unlock_irqrestore(&hdsp->lock, flags);
1503 return change;
1504}
1505
1506#define HDSP_MIXER(xname, xindex) \
1507{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, .index = xindex, \
1508 .info = snd_hdsp_info_mixer, \
1509 .get = snd_hdsp_get_mixer, .put = snd_hdsp_put_mixer }
1510
1511static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1512{
1513 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1514 uinfo->count = 3;
1515 uinfo->value.integer.min = 0;
1516 uinfo->value.integer.max = 65536;
1517 uinfo->value.integer.step = 1;
1518 return 0;
1519}
1520
1521static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1522{
1523 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1524 unsigned long flags;
1525 int source;
1526 int destination;
1527 int addr;
1528
1529 source = ucontrol->value.integer.value[0];
1530 destination = ucontrol->value.integer.value[1];
1531
1532 if (source > 25) {
1533 addr = PLAYBACK_TO_OUTPUT_KEY(source-26,destination);
1534 } else {
1535 addr = INPUT_TO_OUTPUT_KEY(source, destination);
1536 }
1537
1538 spin_lock_irqsave(&hdsp->lock, flags);
1539 ucontrol->value.integer.value[0] = hdsp_read_gain (hdsp, addr);
1540 spin_unlock_irqrestore(&hdsp->lock, flags);
1541 return 0;
1542}
1543
1544static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1545{
1546 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1547 unsigned long flags;
1548 int change;
1549 int source;
1550 int destination;
1551 int gain;
1552 int addr;
1553
1554 if (!snd_hdsp_use_is_exclusive(hdsp))
1555 return -EBUSY;
1556
1557 source = ucontrol->value.integer.value[0];
1558 destination = ucontrol->value.integer.value[1];
1559
1560 if (source > 25) {
1561 addr = PLAYBACK_TO_OUTPUT_KEY(source-26, destination);
1562 } else {
1563 addr = INPUT_TO_OUTPUT_KEY(source, destination);
1564 }
1565
1566 gain = ucontrol->value.integer.value[2];
1567
1568 spin_lock_irqsave(&hdsp->lock, flags);
1569 if ((change = gain != hdsp_read_gain(hdsp, addr)))
1570 hdsp_write_gain(hdsp, addr, gain);
1571 spin_unlock_irqrestore(&hdsp->lock, flags);
1572 return change;
1573}
1574
1575/* The simple mixer control(s) provide gain control for the
1576 basic 1:1 mappings of playback streams to output
1577 streams.
1578*/
1579
1580#define HDSP_PLAYBACK_MIXER \
1581{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1582 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
1583 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1584 .info = snd_hdsp_info_playback_mixer, \
1585 .get = snd_hdsp_get_playback_mixer, .put = snd_hdsp_put_playback_mixer }
1586
1587static int snd_hdsp_info_playback_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1588{
1589 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1590 uinfo->count = 1;
1591 uinfo->value.integer.min = 0;
1592 uinfo->value.integer.max = 65536;
1593 uinfo->value.integer.step = 1;
1594 return 0;
1595}
1596
1597static int snd_hdsp_get_playback_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1598{
1599 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1600 unsigned long flags;
1601 int addr;
1602 int chn;
1603
1604 chn = ucontrol->id.index - 1;
1605 addr = PLAYBACK_TO_OUTPUT_KEY(chn, chn);
1606
1607 spin_lock_irqsave(&hdsp->lock, flags);
1608 ucontrol->value.integer.value[0] = hdsp_read_gain (hdsp, addr);
1609 spin_unlock_irqrestore(&hdsp->lock, flags);
1610 return 0;
1611}
1612
1613static int snd_hdsp_put_playback_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1614{
1615 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1616 unsigned long flags;
1617 int change;
1618 int addr;
1619 int chn;
1620 int gain;
1621
1622 if (!snd_hdsp_use_is_exclusive(hdsp))
1623 return -EBUSY;
1624
1625 chn = ucontrol->id.index - 1;
1626 addr = PLAYBACK_TO_OUTPUT_KEY(chn, chn);
1627 gain = ucontrol->value.integer.value[0];
1628
1629
1630 spin_lock_irqsave(&hdsp->lock, flags);
1631 if ((change = gain != hdsp_read_gain(hdsp, addr)))
1632 hdsp_write_gain(hdsp, addr, gain);
1633 spin_unlock_irqrestore(&hdsp->lock, flags);
1634 return change;
1635}
1636
1637#define HDSP_PEAK_PLAYBACK \
1638{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1639 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1640 .info = snd_hdsp_info_peak_playback, \
1641 .get = snd_hdsp_get_peak_playback \
1642}
1643
1644static int snd_hdsp_info_peak_playback(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1645{
1646 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1647 uinfo->count = 2;
1648 return 0;
1649}
1650
1651static int snd_hdsp_get_peak_playback(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1652{
1653 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1654 unsigned int peakval = hdsp_read (hdsp, HDSP_playbackPeakLevel + (4 * (ucontrol->id.index-1)));
1655 ucontrol->value.integer.value[0] = peakval & 0xffffff00; /* peak */
1656 ucontrol->value.integer.value[1] = peakval & 0xf; /* overs */
1657 return 0;
1658}
1659
1660#define HDSP_PEAK_INPUT \
1661{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1662 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1663 .info = snd_hdsp_info_peak_input, \
1664 .get = snd_hdsp_get_peak_input \
1665}
1666
1667static int snd_hdsp_info_peak_input(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1668{
1669 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1670 uinfo->count = 2;
1671 return 0;
1672}
1673
1674static int snd_hdsp_get_peak_input(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1675{
1676 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1677 unsigned int peakval = hdsp_read (hdsp, HDSP_inputPeakLevel + (4 * (ucontrol->id.index-1)));
1678 ucontrol->value.integer.value[0] = peakval & 0xffffff00; /* peak */
1679 ucontrol->value.integer.value[1] = peakval & 0xf; /* overs */
1680 return 0;
1681}
1682
1683#define HDSP_PEAK_OUTPUT \
1684{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1685 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1686 .info = snd_hdsp_info_peak_output, \
1687 .get = snd_hdsp_get_peak_output \
1688}
1689
1690static int snd_hdsp_info_peak_output(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1691{
1692 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1693 uinfo->count = 2;
1694 return 0;
1695}
1696
1697static int snd_hdsp_get_peak_output(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1698{
1699 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1700 unsigned int peakval = hdsp_read (hdsp, HDSP_outputPeakLevel + (4 * (ucontrol->id.index-1)));
1701 ucontrol->value.integer.value[0] = peakval & 0xffffff00; /* peak */
1702 ucontrol->value.integer.value[1] = peakval & 0xf; /* overs */
1703 return 0;
1704}
1705
1706#define HDSP_RMS_INPUT \
1707{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1708 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1709 .info = snd_hdsp_info_rms_input, \
1710 .get = snd_hdsp_get_rms_input \
1711}
1712
1713static int snd_hdsp_info_rms_input(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1714{
1715 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER64;
1716 uinfo->count = 1;
1717 return 0;
1718}
1719
1720static int snd_hdsp_get_rms_input(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1721{
1722 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1723 ucontrol->value.integer64.value[0] = hdsp_read64 (hdsp, HDSP_inputRmsLevel + (8 * (ucontrol->id.index-1)));
1724 return 0;
1725}
1726
1727#define HDSP_RMS_PLAYBACK \
1728{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1729 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1730 .info = snd_hdsp_info_rms_playback, \
1731 .get = snd_hdsp_get_rms_playback \
1732}
1733
1734static int snd_hdsp_info_rms_playback(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1735{
1736 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER64;
1737 uinfo->count = 1;
1738 return 0;
1739}
1740
1741static int snd_hdsp_get_rms_playback(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1742{
1743 hdsp_t *hdsp = _snd_kcontrol_chip(kcontrol);
1744 ucontrol->value.integer64.value[0] = hdsp_read64 (hdsp, HDSP_playbackRmsLevel + (8 * (ucontrol->id.index-1)));
1745 return 0;
1746}
1747
1748static snd_kcontrol_new_t snd_hdsp_controls[] = {
1749{
1750 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1751 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1752 .info = snd_hdsp_control_spdif_info,
1753 .get = snd_hdsp_control_spdif_get,
1754 .put = snd_hdsp_control_spdif_put,
1755},
1756{
1757 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1758 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1759 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1760 .info = snd_hdsp_control_spdif_stream_info,
1761 .get = snd_hdsp_control_spdif_stream_get,
1762 .put = snd_hdsp_control_spdif_stream_put,
1763},
1764{
1765 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1766 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1767 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1768 .info = snd_hdsp_control_spdif_mask_info,
1769 .get = snd_hdsp_control_spdif_mask_get,
1770 .private_value = IEC958_AES0_NONAUDIO |
1771 IEC958_AES0_PROFESSIONAL |
1772 IEC958_AES0_CON_EMPHASIS,
1773},
1774{
1775 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1776 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1777 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
1778 .info = snd_hdsp_control_spdif_mask_info,
1779 .get = snd_hdsp_control_spdif_mask_get,
1780 .private_value = IEC958_AES0_NONAUDIO |
1781 IEC958_AES0_PROFESSIONAL |
1782 IEC958_AES0_PRO_EMPHASIS,
1783},
1784HDSP_MIXER("Mixer", 0),
1785HDSP_SPDIF_IN("IEC958 Input Connector", 0),
1786HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
1787HDSP_SYNC_PREF("Preferred Sync Source", 0),
1788HDSP_PASSTHRU("Passthru", 0),
1789HDSP_LINE_OUT("Line Out", 0),
1790};
1791
1792#define HDSP_CONTROLS (sizeof(snd_hdsp_controls)/sizeof(snd_kcontrol_new_t))
1793
1794static snd_kcontrol_new_t snd_hdsp_playback_mixer = HDSP_PLAYBACK_MIXER;
1795static snd_kcontrol_new_t snd_hdsp_input_peak = HDSP_PEAK_INPUT;
1796static snd_kcontrol_new_t snd_hdsp_output_peak = HDSP_PEAK_OUTPUT;
1797static snd_kcontrol_new_t snd_hdsp_playback_peak = HDSP_PEAK_PLAYBACK;
1798static snd_kcontrol_new_t snd_hdsp_input_rms = HDSP_RMS_INPUT;
1799static snd_kcontrol_new_t snd_hdsp_playback_rms = HDSP_RMS_PLAYBACK;
1800
1801int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp)
1802{
1803 int idx, err, limit;
1804 snd_kcontrol_t *kctl;
1805
1806 for (idx = 0; idx < HDSP_CONTROLS; idx++) {
1807 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
1808 return err;
1809 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1810 hdsp->spdif_ctl = kctl;
1811 }
1812
1813 if (hdsp->type == Digiface) {
1814 limit = DIGIFACE_SS_CHANNELS;
1815 } else {
1816 limit = MULTIFACE_SS_CHANNELS;
1817 }
1818
1819 /* The index values are one greater than the channel ID so that alsamixer
1820 will display them correctly. We want to use the index for fast lookup
1821 of the relevant channel, but if we use it at all, most ALSA software
1822 does the wrong thing with it ...
1823 */
1824
1825 snd_hdsp_playback_mixer.name = "Chn";
1826 snd_hdsp_input_peak.name = "Input Peak";
1827 snd_hdsp_output_peak.name = "Output Peak";
1828 snd_hdsp_playback_peak.name = "Playback Peak";
1829 snd_hdsp_playback_rms.name = "Playback RMS";
1830 snd_hdsp_input_rms.name = "Input RMS";
1831
1832 for (idx = 0; idx < limit; ++idx) {
1833 snd_hdsp_playback_mixer.index = idx+1;
1834 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_playback_mixer, hdsp)))) {
1835 return err;
1836 }
1837 snd_hdsp_input_peak.index = idx+1;
1838 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_input_peak, hdsp)))) {
1839 return err;
1840 }
1841 snd_hdsp_output_peak.index = idx+1;
1842 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_output_peak, hdsp)))) {
1843 return err;
1844 }
1845 snd_hdsp_playback_peak.index = idx+1;
1846 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_playback_peak, hdsp)))) {
1847 return err;
1848 }
1849 snd_hdsp_playback_rms.index = idx+1;
1850 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_playback_rms, hdsp)))) {
1851 return err;
1852 }
1853 snd_hdsp_input_rms.index = idx+1;
1854 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_input_rms, hdsp)))) {
1855 return err;
1856 }
1857 }
1858
1859 return 0;
1860}
1861
1862/*------------------------------------------------------------
1863 /proc interface
1864 ------------------------------------------------------------*/
1865
1866static void
1867snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1868{
1869 hdsp_t *hdsp = (hdsp_t *) entry->private_data;
1870 unsigned int status;
1871 unsigned int status2;
1872 char *requested_sync_ref;
1873 int x;
1874
1875 if (hdsp_check_for_iobox (hdsp)) {
1876 return;
1877 }
1878
1879 status = hdsp_read(hdsp, HDSP_statusRegister);
1880 status2 = hdsp_read(hdsp, HDSP_status2Register);
1881
1882 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
1883 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
1884 hdsp->capture_buffer, hdsp->playback_buffer);
1885 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
1886 hdsp->irq, hdsp->port, hdsp->iobase);
1887 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
1888 snd_iprintf(buffer, "Status register: 0x%x\n", status);
1889 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
1890 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
1891
1892 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
1893 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
1894 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
1895 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
1896
1897 snd_iprintf(buffer, "\n");
1898
1899 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
1900
1901 snd_iprintf(buffer, "Latency: %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
1902 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
1903 snd_iprintf(buffer, "Passthru: %s\n", hdsp->passthru ? "yes" : "no");
1904 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
1905
1906 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
1907
1908 switch (hdsp_sync_pref (hdsp)) {
1909 case HDSP_SYNC_FROM_WORD:
1910 requested_sync_ref = "Word";
1911 break;
1912 case HDSP_SYNC_FROM_ADAT_SYNC:
1913 requested_sync_ref = "ADAT Sync";
1914 break;
1915 case HDSP_SYNC_FROM_SPDIF:
1916 requested_sync_ref = "SPDIF";
1917 break;
1918 case HDSP_SYNC_FROM_ADAT1:
1919 requested_sync_ref = "ADAT1";
1920 break;
1921 case HDSP_SYNC_FROM_ADAT2:
1922 requested_sync_ref = "ADAT2";
1923 break;
1924 case HDSP_SYNC_FROM_ADAT3:
1925 requested_sync_ref = "ADAT3";
1926 break;
1927 case HDSP_SYNC_FROM_SELF:
1928 default:
1929 requested_sync_ref = "Master";
1930 break;
1931 }
1932
1933 if ((hdsp->control_register & HDSP_ClockModeMaster)) {
1934 snd_iprintf (buffer, "Sync reference: %s/Master (chosen)\n", requested_sync_ref);
1935 } else if (hdsp_system_sample_rate(hdsp) == 0) {
1936 snd_iprintf (buffer, "Sync reference: %s/Master (forced)\n", requested_sync_ref);
1937 } else {
1938 switch (status2 & HDSP_SelSyncRefMask) {
1939 case HDSP_SelSyncRef_ADAT1:
1940 snd_iprintf (buffer, "Sync reference: %s/ADAT1\n", requested_sync_ref);
1941 break;
1942 case HDSP_SelSyncRef_ADAT2:
1943 snd_iprintf (buffer, "Sync reference: %s/ADAT2\n", requested_sync_ref);
1944 break;
1945 case HDSP_SelSyncRef_ADAT3:
1946 snd_iprintf (buffer, "Sync reference: %s/ADAT3\n", requested_sync_ref);
1947 break;
1948 case HDSP_SelSyncRef_SPDIF:
1949 snd_iprintf (buffer, "Sync reference: %s/SPDIF\n", requested_sync_ref);
1950 break;
1951 case HDSP_SelSyncRef_WORD:
1952 snd_iprintf (buffer, "Sync reference: %s/WORD\n", requested_sync_ref);
1953 break;
1954 case HDSP_SelSyncRef_ADAT_SYNC:
1955 snd_iprintf (buffer, "Sync reference: %s/ADAT Sync\n", requested_sync_ref);
1956 break;
1957 default:
1958 snd_iprintf (buffer, "Sync reference: %s/Master (fallback)\n", requested_sync_ref);
1959 break;
1960 }
1961 }
1962 snd_iprintf (buffer, "Sample rate: %d\n", hdsp_system_sample_rate(hdsp));
1963
1964 snd_iprintf(buffer, "\n");
1965
1966 switch ((hdsp->control_register & HDSP_SPDIFInputMask) >> 14) {
1967 case HDSP_SPDIFIN_OPTICAL:
1968 snd_iprintf(buffer, "IEC958 input: ADAT1\n");
1969 break;
1970 case HDSP_SPDIFIN_COAXIAL:
1971 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
1972 break;
1973 case HDSP_SPDIFIN_INTERN:
1974 snd_iprintf(buffer, "IEC958 input: Internal\n");
1975 break;
1976 default:
1977 snd_iprintf(buffer, "IEC958 input: ???\n");
1978 break;
1979 }
1980
1981 if (hdsp->control_register & HDSP_SPDIFOpticalOut) {
1982 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
1983 } else {
1984 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
1985 }
1986
1987 if (hdsp->control_register & HDSP_SPDIFProfessional) {
1988 snd_iprintf(buffer, "IEC958 quality: Professional\n");
1989 } else {
1990 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
1991 }
1992
1993 if (hdsp->control_register & HDSP_SPDIFEmphasis) {
1994 snd_iprintf(buffer, "IEC958 emphasis: on\n");
1995 } else {
1996 snd_iprintf(buffer, "IEC958 emphasis: off\n");
1997 }
1998
1999 if (hdsp->control_register & HDSP_SPDIFNonAudio) {
2000 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
2001 } else {
2002 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
2003 }
2004
2005 snd_iprintf(buffer, "\n");
2006
2007 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) {
2008 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
2009 } else {
2010 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
2011 }
2012
2013 snd_iprintf(buffer, "\n");
2014
2015 /* Sync Check */
2016 x = status & HDSP_Sync0;
2017 if (status & HDSP_Lock0) {
2018 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
2019 } else {
2020 snd_iprintf(buffer, "ADAT1: No Lock\n");
2021 }
2022
2023 x = status & HDSP_Sync1;
2024 if (status & HDSP_Lock1) {
2025 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
2026 } else {
2027 snd_iprintf(buffer, "ADAT2: No Lock\n");
2028 }
2029
2030 if (hdsp->type == Digiface) {
2031 x = status & HDSP_Sync2;
2032 if (status & HDSP_Lock2) {
2033 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
2034 } else {
2035 snd_iprintf(buffer, "ADAT3: No Lock\n");
2036 }
2037 }
2038
2039 snd_iprintf(buffer, "\n");
2040
2041#if 0
2042 for (x = 0; x < 26; x++) {
2043 unsigned int val = hdsp_read (hdsp, HDSP_inputPeakLevel + (4 * x));
2044 snd_iprintf (buffer, "%d: input peak = %d overs = %d\n", x, val&0xffffff00, val&0xf);
2045 }
2046#endif
2047}
2048
2049static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp)
2050{
2051 snd_info_entry_t *entry;
2052
2053 if ((entry = snd_info_create_card_entry(hdsp->card, "hdsp", hdsp->card->proc_root)) !=
2054 NULL) {
2055 entry->content = SNDRV_INFO_CONTENT_TEXT;
2056 entry->private_data = hdsp;
2057 entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
2058 entry->c.text.read_size = 256;
2059 entry->c.text.read = snd_hdsp_proc_read;
2060 if (snd_info_register(entry) < 0) {
2061 snd_info_free_entry(entry);
2062 entry = NULL;
2063 }
2064 }
2065 hdsp->proc_entry = entry;
2066}
2067
2068static void snd_hdsp_proc_done(hdsp_t *hdsp)
2069{
2070 if (hdsp->proc_entry) {
2071 snd_info_unregister(hdsp->proc_entry);
2072 hdsp->proc_entry = NULL;
2073 }
2074}
2075
2076static void snd_hdsp_free_buffers(hdsp_t *hdsp)
2077{
2078 if (hdsp->capture_buffer_unaligned) {
2079#ifndef HDSP_PREALLOCATE_MEMORY
2080 snd_free_pci_pages(hdsp->pci,
2081 HDSP_DMA_AREA_BYTES,
2082 hdsp->capture_buffer_unaligned,
2083 hdsp->capture_buffer_addr);
2084#else
2085 snd_hammerfall_free_buffer(hdsp->pci, hdsp->capture_buffer_unaligned);
2086#endif
2087 }
2088
2089 if (hdsp->playback_buffer_unaligned) {
2090#ifndef HDSP_PREALLOCATE_MEMORY
2091 snd_free_pci_pages(hdsp->pci,
2092 HDSP_DMA_AREA_BYTES,
2093 hdsp->playback_buffer_unaligned,
2094 hdsp->playback_buffer_addr);
2095#else
2096 snd_hammerfall_free_buffer(hdsp->pci, hdsp->playback_buffer_unaligned);
2097#endif
2098 }
2099}
2100
2101static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp)
2102{
2103 void *pb, *cb;
2104 dma_addr_t pb_addr, cb_addr;
2105 unsigned long pb_bus, cb_bus;
2106
2107#ifndef HDSP_PREALLOCATE_MEMORY
2108 cb = snd_malloc_pci_pages(hdsp->pci, HDSP_DMA_AREA_BYTES, &cb_addr);
2109 pb = snd_malloc_pci_pages(hdsp->pci, HDSP_DMA_AREA_BYTES, &pb_addr);
2110#else
2111 cb = snd_hammerfall_get_buffer(hdsp->pci, &cb_addr);
2112 pb = snd_hammerfall_get_buffer(hdsp->pci, &pb_addr);
2113#endif
2114
2115 if (cb == 0 || pb == 0) {
2116 if (cb) {
2117#ifdef HDSP_PREALLOCATE_MEMORY
2118 snd_hammerfall_free_buffer(hdsp->pci, cb);
2119#else
2120 snd_free_pci_pages(hdsp->pci, HDSP_DMA_AREA_BYTES, cb, cb_addr);
2121#endif
2122 }
2123 if (pb) {
2124#ifdef HDSP_PREALLOCATE_MEMORY
2125 snd_hammerfall_free_buffer(hdsp->pci, pb);
2126#else
2127 snd_free_pci_pages(hdsp->pci, HDSP_DMA_AREA_BYTES, pb, pb_addr);
2128#endif
2129 }
2130
2131 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
2132 return -ENOMEM;
2133 }
2134
2135 /* save raw addresses for use when freeing memory later */
2136
2137 hdsp->capture_buffer_unaligned = cb;
2138 hdsp->playback_buffer_unaligned = pb;
2139 hdsp->capture_buffer_addr = cb_addr;
2140 hdsp->playback_buffer_addr = pb_addr;
2141
2142 /* Align to bus-space 64K boundary */
2143
2144 cb_bus = (cb_addr + 0xFFFF) & ~0xFFFFl;
2145 pb_bus = (pb_addr + 0xFFFF) & ~0xFFFFl;
2146
2147 /* Tell the card where it is */
2148
2149 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
2150 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
2151
2152 hdsp->capture_buffer = cb + (cb_bus - cb_addr);
2153 hdsp->playback_buffer = pb + (pb_bus - pb_addr);
2154
2155 return 0;
2156}
2157
2158static void snd_hdsp_set_defaults(hdsp_t *hdsp)
2159{
2160 unsigned int i;
2161
2162 /* ASSUMPTION: hdsp->lock is either held, or
2163 there is no need to hold it (e.g. during module
2164 initalization).
2165 */
2166
2167 /* set defaults:
2168
2169 SPDIF Input via Coax
2170 Master clock mode
2171 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
2172 which implies 2 4096 sample, 32Kbyte periods).
2173 Enable line out.
2174 */
2175
2176 hdsp->control_register = HDSP_ClockModeMaster |
2177 HDSP_SPDIFInputCoaxial |
2178 hdsp_encode_latency(7) |
2179 HDSP_LineOut;
2180
2181 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2182 hdsp_reset_hw_pointer(hdsp);
2183 hdsp_compute_period_size(hdsp);
2184
2185 /* silence everything */
2186
2187 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) {
2188 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
2189 }
2190
2191 for (i = 0; i < 2048; i++)
2192 hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN);
2193
2194 if (line_outs_monitor[hdsp->dev]) {
2195
2196 snd_printk ("sending all inputs and playback streams to line outs.\n");
2197
2198 /* route all inputs to the line outs for easy monitoring. send
2199 odd numbered channels to right, even to left.
2200 */
2201
2202 for (i = 0; i < HDSP_MAX_CHANNELS; i++) {
2203 if (i & 1) {
2204 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY (i, 26), UNITY_GAIN);
2205 hdsp_write_gain (hdsp, PLAYBACK_TO_OUTPUT_KEY (i, 26), UNITY_GAIN);
2206 } else {
2207 hdsp_write_gain (hdsp, INPUT_TO_OUTPUT_KEY (i, 27), UNITY_GAIN);
2208 hdsp_write_gain (hdsp, PLAYBACK_TO_OUTPUT_KEY (i, 27), UNITY_GAIN);
2209 }
2210 }
2211 }
2212
2213 hdsp->passthru = 0;
2214
2215 /* set a default rate so that the channel map is set up.
2216 */
2217
2218 hdsp_set_rate(hdsp, 48000);
2219}
2220
2221void snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2222{
2223 hdsp_t *hdsp = (hdsp_t *) dev_id;
2224 unsigned int status;
2225 int audio;
2226 int midi0;
2227 int midi1;
2228 unsigned int midi0status;
2229 unsigned int midi1status;
2230
2231 status = hdsp_read(hdsp, HDSP_statusRegister);
2232
2233 audio = status & HDSP_audioIRQPending;
2234 midi0 = status & HDSP_midi0IRQPending;
2235 midi1 = status & HDSP_midi1IRQPending;
2236
2237 if (!audio && !midi0 && !midi1) {
2238 return;
2239 }
2240
2241 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
2242
2243 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
2244 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
2245
2246 if (audio) {
2247 if (hdsp->capture_substream) {
2248 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
2249 }
2250
2251 if (hdsp->playback_substream) {
2252 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
2253 }
2254 }
2255
2256 /* note: snd_hdsp_midi_input_read() calls output_write() because
2257 output is not interrupt-driven ...
2258 */
2259
2260 if (midi0status)
2261 snd_hdsp_midi_input_read (&hdsp->midi[0]);
2262 if (midi1status)
2263 snd_hdsp_midi_input_read (&hdsp->midi[1]);
2264}
2265
2266static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream)
2267{
2268 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2269 return hdsp_hw_pointer(hdsp);
2270}
2271
2272static char *hdsp_channel_buffer_location(hdsp_t *hdsp,
2273 int stream,
2274 int channel)
2275
2276{
2277 int mapped_channel;
2278
2279 snd_assert(channel >= 0 || channel < HDSP_MAX_CHANNELS, return NULL);
2280
2281 if ((mapped_channel = hdsp->channel_map[channel]) < 0) {
2282 return NULL;
2283 }
2284
2285 if (stream == SNDRV_PCM_STREAM_CAPTURE) {
2286 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
2287 } else {
2288 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
2289 }
2290}
2291
2292static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel,
2293 snd_pcm_uframes_t pos, void *src, snd_pcm_uframes_t count)
2294{
2295 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2296 char *channel_buf;
2297
2298 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
2299
2300 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
2301 snd_assert(channel_buf != NULL, return -EIO);
2302 copy_from_user(channel_buf + pos * 4, src, count * 4);
2303 return count;
2304}
2305
2306static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel,
2307 snd_pcm_uframes_t pos, void *dst, snd_pcm_uframes_t count)
2308{
2309 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2310 char *channel_buf;
2311
2312 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
2313
2314 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
2315 snd_assert(channel_buf != NULL, return -EIO);
2316 copy_to_user(dst, channel_buf + pos * 4, count * 4);
2317 return count;
2318}
2319
2320static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel,
2321 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
2322{
2323 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2324 char *channel_buf;
2325
2326 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
2327 snd_assert(channel_buf != NULL, return -EIO);
2328 memset(channel_buf + pos * 4, 0, count * 4);
2329 return count;
2330}
2331
2332static int snd_hdsp_reset(snd_pcm_substream_t *substream)
2333{
2334 snd_pcm_runtime_t *runtime = substream->runtime;
2335 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2336 snd_pcm_substream_t *other;
2337 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2338 other = hdsp->capture_substream;
2339 else
2340 other = hdsp->playback_substream;
2341 if (hdsp->running)
2342 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
2343 else
2344 runtime->status->hw_ptr = 0;
2345 if (other) {
2346 snd_pcm_substream_t *s = substream;
2347 snd_pcm_runtime_t *oruntime = other->runtime;
2348 do {
2349 s = s->link_next;
2350 if (s == other) {
2351 oruntime->status->hw_ptr = runtime->status->hw_ptr;
2352 break;
2353 }
2354 } while (s != substream);
2355 }
2356 return 0;
2357}
2358
2359static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
2360 snd_pcm_hw_params_t *params)
2361{
2362 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2363 int err;
2364 pid_t this_pid;
2365 pid_t other_pid;
2366
2367 if (hdsp_check_for_iobox (hdsp)) {
2368 return -EIO;
2369 }
2370
2371 spin_lock_irq(&hdsp->lock);
2372
2373 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2374 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
2375 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
2376 this_pid = hdsp->playback_pid;
2377 other_pid = hdsp->capture_pid;
2378 } else {
2379 this_pid = hdsp->capture_pid;
2380 other_pid = hdsp->playback_pid;
2381 }
2382
2383 if ((other_pid > 0) && (this_pid != other_pid)) {
2384
2385 /* The other stream is open, and not by the same
2386 task as this one. Make sure that the parameters
2387 that matter are the same.
2388 */
2389
2390 if (params_rate(params) != hdsp_system_sample_rate(hdsp)) {
2391 spin_unlock_irq(&hdsp->lock);
2392 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
2393 return -EBUSY;
2394 }
2395
2396 if (params_period_size(params) != hdsp->period_bytes / 4) {
2397 spin_unlock_irq(&hdsp->lock);
2398 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
2399 return -EBUSY;
2400 }
2401
2402 /* We're fine. */
2403
2404 spin_unlock_irq(&hdsp->lock);
2405 return 0;
2406
2407 } else {
2408 spin_unlock_irq(&hdsp->lock);
2409 }
2410
2411 /* how to make sure that the rate matches an externally-set one ?
2412 */
2413
2414 if ((err = hdsp_set_rate(hdsp, params_rate(params))) < 0) {
2415 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
2416 return err;
2417 }
2418
2419 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
2420 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
2421 return err;
2422 }
2423
2424 return 0;
2425}
2426
2427static int snd_hdsp_channel_info(snd_pcm_substream_t *substream,
2428 snd_pcm_channel_info_t *info)
2429{
2430 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2431 int chn;
2432
2433 snd_assert(info->channel < HDSP_MAX_CHANNELS, return -EINVAL);
2434
2435 if ((chn = hdsp->channel_map[info->channel]) < 0) {
2436 return -EINVAL;
2437 }
2438
2439 info->offset = chn * HDSP_CHANNEL_BUFFER_BYTES;
2440 info->first = 0;
2441 info->step = 32;
2442 return 0;
2443}
2444
2445static int snd_hdsp_ioctl(snd_pcm_substream_t *substream,
2446 unsigned int cmd, void *arg)
2447{
2448 switch (cmd) {
2449 case SNDRV_PCM_IOCTL1_RESET:
2450 {
2451 return snd_hdsp_reset(substream);
2452 }
2453 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
2454 {
2455 snd_pcm_channel_info_t *info = arg;
2456 return snd_hdsp_channel_info(substream, info);
2457 }
2458 default:
2459 break;
2460 }
2461
2462 return snd_pcm_lib_ioctl(substream, cmd, arg);
2463}
2464
2465static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd)
2466{
2467 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2468 snd_pcm_substream_t *other;
2469 int running;
2470
2471 if (hdsp_check_for_iobox (hdsp)) {
2472 return -EIO;
2473 }
2474
2475 spin_lock(&hdsp->lock);
2476 running = hdsp->running;
2477 switch (cmd) {
2478 case SNDRV_PCM_TRIGGER_START:
2479 running |= 1 << substream->stream;
2480 break;
2481 case SNDRV_PCM_TRIGGER_STOP:
2482 running &= ~(1 << substream->stream);
2483 break;
2484 default:
2485 snd_BUG();
2486 spin_unlock(&hdsp->lock);
2487 return -EINVAL;
2488 }
2489 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2490 other = hdsp->capture_substream;
2491 else
2492 other = hdsp->playback_substream;
2493
2494 if (other) {
2495 snd_pcm_substream_t *s = substream;
2496 do {
2497 s = s->link_next;
2498 if (s == other) {
2499 snd_pcm_trigger_done(s, substream);
2500 if (cmd == SNDRV_PCM_TRIGGER_START)
2501 running |= 1 << s->stream;
2502 else
2503 running &= ~(1 << s->stream);
2504 goto _ok;
2505 }
2506 } while (s != substream);
2507 if (cmd == SNDRV_PCM_TRIGGER_START) {
2508 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
2509 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2510 hdsp_silence_playback(hdsp);
2511 } else {
2512 if (running &&
2513 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2514 hdsp_silence_playback(hdsp);
2515 }
2516 } else {
2517 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2518 hdsp_silence_playback(hdsp);
2519 }
2520 _ok:
2521 snd_pcm_trigger_done(substream, substream);
2522 if (!hdsp->running && running)
2523 hdsp_start_audio(hdsp);
2524 else if (hdsp->running && !running)
2525 hdsp_stop_audio(hdsp);
2526 hdsp->running = running;
2527 spin_unlock(&hdsp->lock);
2528
2529 return 0;
2530}
2531
2532static int snd_hdsp_prepare(snd_pcm_substream_t *substream)
2533{
2534 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2535 int result = 0;
2536
2537 if (hdsp_check_for_iobox (hdsp)) {
2538 return -EIO;
2539 }
2540
2541 spin_lock_irq(&hdsp->lock);
2542 if (!hdsp->running)
2543 hdsp_reset_hw_pointer(hdsp);
2544 spin_unlock_irq(&hdsp->lock);
2545 return result;
2546}
2547
2548static snd_pcm_hardware_t snd_hdsp_playback_subinfo =
2549{
2550 .info = (SNDRV_PCM_INFO_MMAP |
2551 SNDRV_PCM_INFO_MMAP_VALID |
2552 SNDRV_PCM_INFO_NONINTERLEAVED |
2553 SNDRV_PCM_INFO_SYNC_START |
2554 SNDRV_PCM_INFO_DOUBLE),
2555 .formats = SNDRV_PCM_FMTBIT_S32_LE,
2556 .rates = (SNDRV_PCM_RATE_32000 |
2557 SNDRV_PCM_RATE_44100 |
2558 SNDRV_PCM_RATE_48000 |
2559 SNDRV_PCM_RATE_64000 |
2560 SNDRV_PCM_RATE_88200 |
2561 SNDRV_PCM_RATE_96000),
2562 .rate_min = 32000,
2563 .rate_max = 96000,
2564 .channels_min = 10,
2565 .channels_max = HDSP_MAX_CHANNELS,
2566 .buffer_bytes_max = 1024*1024,
2567 .period_bytes_min = 1,
2568 .period_bytes_max = 1024*1024,
2569 .periods_min = 2,
2570 .periods_max = 2,
2571 .fifo_size = 0,
2572};
2573
2574static snd_pcm_hardware_t snd_hdsp_capture_subinfo =
2575{
2576 .info = (SNDRV_PCM_INFO_MMAP |
2577 SNDRV_PCM_INFO_MMAP_VALID |
2578 SNDRV_PCM_INFO_NONINTERLEAVED |
2579 SNDRV_PCM_INFO_SYNC_START),
2580 .formats = SNDRV_PCM_FMTBIT_S32_LE,
2581 .rates = (SNDRV_PCM_RATE_32000 |
2582 SNDRV_PCM_RATE_44100 |
2583 SNDRV_PCM_RATE_48000 |
2584 SNDRV_PCM_RATE_64000 |
2585 SNDRV_PCM_RATE_88200 |
2586 SNDRV_PCM_RATE_96000),
2587 .rate_min = 32000,
2588 .rate_max = 96000,
2589 .channels_min = 10,
2590 .channels_max = HDSP_MAX_CHANNELS,
2591 .buffer_bytes_max = 1024*1024,
2592 .period_bytes_min = 1,
2593 .period_bytes_max = 1024*1024,
2594 .periods_min = 2,
2595 .periods_max = 2,
2596 .fifo_size = 0,
2597};
2598
2599static unsigned int period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
2600
2601#define PERIOD_SIZES sizeof(period_sizes) / sizeof(period_sizes[0])
2602
2603static snd_pcm_hw_constraint_list_t hw_constraints_period_sizes = {
2604 .count = PERIOD_SIZES,
2605 .list = period_sizes,
2606 .mask = 0
2607};
2608
2609static int snd_hdsp_hw_rule_channels(snd_pcm_hw_params_t *params,
2610 snd_pcm_hw_rule_t *rule)
2611{
2612 hdsp_t *hdsp = rule->private;
2613 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2614 unsigned int list[2] = { hdsp->ds_channels, hdsp->ss_channels };
2615 return snd_interval_list(c, 2, list, 0);
2616}
2617
2618static int snd_hdsp_hw_rule_channels_rate(snd_pcm_hw_params_t *params,
2619 snd_pcm_hw_rule_t *rule)
2620{
2621 hdsp_t *hdsp = rule->private;
2622 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2623 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
2624 if (r->min > 48000) {
2625 snd_interval_t t = {
2626 min: hdsp->ds_channels,
2627 max: hdsp->ds_channels,
2628 integer: 1,
2629 };
2630 return snd_interval_refine(c, &t);
2631 } else if (r->max < 64000) {
2632 snd_interval_t t = {
2633 min: hdsp->ss_channels,
2634 max: hdsp->ss_channels,
2635 integer: 1,
2636 };
2637 return snd_interval_refine(c, &t);
2638 }
2639 return 0;
2640}
2641
2642static int snd_hdsp_hw_rule_rate_channels(snd_pcm_hw_params_t *params,
2643 snd_pcm_hw_rule_t *rule)
2644{
2645 hdsp_t *hdsp = rule->private;
2646 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2647 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
2648 if (c->min >= hdsp->ss_channels) {
2649 snd_interval_t t = {
2650 min: 32000,
2651 max: 48000,
2652 integer: 1,
2653 };
2654 return snd_interval_refine(r, &t);
2655 } else if (c->max <= hdsp->ds_channels) {
2656 snd_interval_t t = {
2657 min: 64000,
2658 max: 96000,
2659 integer: 1,
2660 };
2661 return snd_interval_refine(r, &t);
2662 }
2663 return 0;
2664}
2665
2666static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
2667{
2668 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2669 unsigned long flags;
2670 snd_pcm_runtime_t *runtime = substream->runtime;
2671
2672 if (hdsp_check_for_iobox (hdsp)) {
2673 return -EIO;
2674 }
2675
2676 spin_lock_irqsave(&hdsp->lock, flags);
2677
2678 snd_pcm_set_sync(substream);
2679
2680 runtime->hw = snd_hdsp_playback_subinfo;
2681 runtime->dma_area = hdsp->playback_buffer;
2682 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
2683
2684 if (hdsp->capture_substream == NULL) {
2685 hdsp_stop_audio(hdsp);
2686 hdsp_set_thru(hdsp, -1, 0);
2687 }
2688
2689 hdsp->playback_pid = current->pid;
2690 hdsp->playback_substream = substream;
2691
2692 spin_unlock_irqrestore(&hdsp->lock, flags);
2693
2694 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
2695 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);
2696 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2697 snd_hdsp_hw_rule_channels, hdsp,
2698 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2699 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2700 snd_hdsp_hw_rule_channels_rate, hdsp,
2701 SNDRV_PCM_HW_PARAM_RATE, -1);
2702 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
2703 snd_hdsp_hw_rule_rate_channels, hdsp,
2704 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2705
2706 hdsp->creg_spdif_stream = hdsp->creg_spdif;
2707 hdsp->spdif_ctl->access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2708 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
2709 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
2710 return 0;
2711}
2712
2713static int snd_hdsp_playback_release(snd_pcm_substream_t *substream)
2714{
2715 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2716 unsigned long flags;
2717
2718 spin_lock_irqsave(&hdsp->lock, flags);
2719
2720 hdsp->playback_pid = -1;
2721 hdsp->playback_substream = NULL;
2722
2723 spin_unlock_irqrestore(&hdsp->lock, flags);
2724
2725 hdsp->spdif_ctl->access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2726 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
2727 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
2728 return 0;
2729}
2730
2731
2732static int snd_hdsp_capture_open(snd_pcm_substream_t *substream)
2733{
2734 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2735 unsigned long flags;
2736 snd_pcm_runtime_t *runtime = substream->runtime;
2737
2738 if (hdsp_check_for_iobox (hdsp)) {
2739 return -EIO;
2740 }
2741
2742 spin_lock_irqsave(&hdsp->lock, flags);
2743
2744 snd_pcm_set_sync(substream);
2745
2746 runtime->hw = snd_hdsp_capture_subinfo;
2747 runtime->dma_area = hdsp->capture_buffer;
2748 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
2749
2750 if (hdsp->playback_substream == NULL) {
2751 hdsp_stop_audio(hdsp);
2752 hdsp_set_thru(hdsp, -1, 0);
2753 }
2754
2755 hdsp->capture_pid = current->pid;
2756 hdsp->capture_substream = substream;
2757
2758 spin_unlock_irqrestore(&hdsp->lock, flags);
2759
2760 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
2761 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);
2762 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2763 snd_hdsp_hw_rule_channels, hdsp,
2764 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2765 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2766 snd_hdsp_hw_rule_channels_rate, hdsp,
2767 SNDRV_PCM_HW_PARAM_RATE, -1);
2768 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
2769 snd_hdsp_hw_rule_rate_channels, hdsp,
2770 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2771 return 0;
2772}
2773
2774static int snd_hdsp_capture_release(snd_pcm_substream_t *substream)
2775{
2776 hdsp_t *hdsp = _snd_pcm_substream_chip(substream);
2777 unsigned long flags;
2778
2779 spin_lock_irqsave(&hdsp->lock, flags);
2780
2781 hdsp->capture_pid = -1;
2782 hdsp->capture_substream = NULL;
2783
2784 spin_unlock_irqrestore(&hdsp->lock, flags);
2785 return 0;
2786}
2787
2788static snd_pcm_ops_t snd_hdsp_playback_ops = {
2789 .open = snd_hdsp_playback_open,
2790 .close = snd_hdsp_playback_release,
2791 .ioctl = snd_hdsp_ioctl,
2792 .hw_params = snd_hdsp_hw_params,
2793 .prepare = snd_hdsp_prepare,
2794 .trigger = snd_hdsp_trigger,
2795 .pointer = snd_hdsp_hw_pointer,
2796 .copy = snd_hdsp_playback_copy,
2797 .silence = snd_hdsp_hw_silence,
2798};
2799
2800static snd_pcm_ops_t snd_hdsp_capture_ops = {
2801 .open = snd_hdsp_capture_open,
2802 .close = snd_hdsp_capture_release,
2803 .ioctl = snd_hdsp_ioctl,
2804 .hw_params = snd_hdsp_hw_params,
2805 .prepare = snd_hdsp_prepare,
2806 .trigger = snd_hdsp_trigger,
2807 .pointer = snd_hdsp_hw_pointer,
2808 .copy = snd_hdsp_capture_copy,
2809};
2810
2811static int __devinit snd_hdsp_create_pcm(snd_card_t *card,
2812 hdsp_t *hdsp)
2813{
2814 snd_pcm_t *pcm;
2815 int err;
2816
2817 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
2818 return err;
2819
2820 hdsp->pcm = pcm;
2821 pcm->private_data = hdsp;
2822 strcpy(pcm->name, hdsp->card_name);
2823
2824 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
2825 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
2826
2827 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
2828
2829 return 0;
2830}
2831
2832static int __devinit snd_hdsp_initialize_firmware (hdsp_t *hdsp)
2833{
2834 int i;
2835 u32 *firmware_ptr;
2836
2837 if (hdsp_check_for_iobox (hdsp)) {
2838 return -EIO;
2839 }
2840
2841 if (hdsp_fifo_wait (hdsp, 0, 100)) {
2842 return -EIO;
2843 }
2844
2845 /* enable all channels */
2846
2847 for (i = 0; i < HDSP_MAX_CHANNELS; ++i) {
2848 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
2849 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
2850 }
2851
2852 if (force_firmware[hdsp->dev] || (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
2853
2854 snd_printk ("loading firmware\n");
2855
2856 hdsp_write (hdsp, HDSP_jtagReg, HDSP_PROGRAM);
2857 hdsp_write (hdsp, HDSP_fifoData, 0);
2858 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) {
2859 snd_printk ("timeout waiting for firmware setup\n");
2860 return -EIO;
2861 }
2862
2863 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_LOAD);
2864 hdsp_write (hdsp, HDSP_fifoData, 0);
2865
2866 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
2867 hdsp->type = Multiface;
2868 hdsp_write (hdsp, HDSP_jtagReg, HDSP_VERSION_BIT);
2869 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_LOAD);
2870 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
2871 } else {
2872 hdsp->type = Digiface;
2873 }
2874
2875 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_PROGRAM);
2876 hdsp_write (hdsp, HDSP_fifoData, 0);
2877
2878 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
2879 snd_printk ("timeout waiting for download preparation\n");
2880 return -EIO;
2881 }
2882
2883 hdsp_write (hdsp, HDSP_jtagReg, HDSP_S_LOAD);
2884
2885 if (hdsp->type == Digiface) {
2886 firmware_ptr = (u32 *) digiface_firmware;
2887 } else {
2888 firmware_ptr = (u32 *) multiface_firmware;
2889 }
2890
2891 for (i = 0; i < 24413; ++i) {
2892 hdsp_write(hdsp, HDSP_fifoData, firmware_ptr[i]);
2893 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
2894 snd_printk ("timeout during firmware loading\n");
2895 return -EIO;
2896 }
2897 }
2898
2899 if (hdsp_fifo_wait (hdsp, 3, HDSP_LONG_WAIT)) {
2900 snd_printk ("timeout at end of firmware loading\n");
2901 return -EIO;
2902 }
2903
2904 } else {
2905
2906 /* firmware already loaded, but we need to know what type
2907 of I/O box is connected.
2908 */
2909
2910 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
2911 hdsp->type = Multiface;
2912 } else {
2913 hdsp->type = Digiface;
2914 }
2915 }
2916
2917 if (hdsp->type == Digiface) {
2918 snd_printk ("I/O Box is a Digiface\n");
2919 hdsp->card_name = "RME Hammerfall DSP (Digiface)";
2920 hdsp->ss_channels = DIGIFACE_SS_CHANNELS;
2921 hdsp->ds_channels = DIGIFACE_DS_CHANNELS;
2922 } else {
2923 snd_printk ("I/O Box is a Multiface\n");
2924 hdsp->card_name = "RME Hammerfall DSP (Multiface)";
2925 hdsp->ss_channels = MULTIFACE_SS_CHANNELS;
2926 hdsp->ds_channels = MULTIFACE_DS_CHANNELS;
2927 }
2928
2929 snd_hdsp_flush_midi_input (hdsp, 0);
2930 snd_hdsp_flush_midi_input (hdsp, 1);
2931
2932#ifdef SNDRV_BIG_ENDIAN
2933 hdsp_write(hdsp, HDSP_jtagReg, HDSP_BIGENDIAN_MODE);
2934#endif
2935
2936 return 0;
2937}
2938
2939static int __devinit snd_hdsp_create(snd_card_t *card,
2940 hdsp_t *hdsp,
2941 int precise_ptr)
2942{
2943 struct pci_dev *pci = hdsp->pci;
2944 int err;
2945 unsigned short rev;
2946
2947 hdsp->irq = -1;
2948 hdsp->midi[0].rmidi = 0;
2949 hdsp->midi[1].rmidi = 0;
2950 hdsp->midi[0].input = 0;
2951 hdsp->midi[1].input = 0;
2952 hdsp->midi[0].output = 0;
2953 hdsp->midi[1].output = 0;
2954 spin_lock_init(&hdsp->midi[0].lock);
2955 spin_lock_init(&hdsp->midi[1].lock);
2956 hdsp->iobase = 0;
2957 hdsp->res_port = 0;
2958
2959 hdsp->card = card;
2960
2961 spin_lock_init(&hdsp->lock);
2962
2963 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &rev);
2964 strcpy(card->driver, "H-DSP");
2965 strcpy(card->mixername, "Xilinx FPGA");
2966
2967 switch (rev & 0xff) {
2968 case 0xa:
2969 /* hdsp_initialize_firmware() will reset this */
2970 hdsp->card_name = "RME Hammerfall DSP";
2971 break;
2972
2973 default:
2974 return -ENODEV;
2975 }
2976
2977 if ((err = pci_enable_device(pci)) < 0)
2978 return err;
2979
2980 pci_set_master(hdsp->pci);
2981
2982 hdsp->port = pci_resource_start(pci, 0);
2983
2984 if ((hdsp->res_port = request_mem_region(hdsp->port, HDSP_IO_EXTENT, "hdsp")) == NULL) {
2985 snd_printk("unable to grab memory region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
2986 return -EBUSY;
2987 }
2988
2989 if ((hdsp->iobase = (unsigned long) ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == 0) {
2990 snd_printk("unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
2991 return -EBUSY;
2992 }
2993
2994 if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) {
2995 snd_printk("unable to use IRQ %d\n", pci->irq);
2996 return -EBUSY;
2997 }
2998
2999 hdsp->irq = pci->irq;
3000 hdsp->precise_ptr = precise_ptr;
3001
3002 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) {
3003 return err;
3004 }
3005
3006 if ((err = snd_hdsp_initialize_firmware(hdsp)) < 0) {
3007 return err;
3008 }
3009
3010 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
3011 return err;
3012 }
3013
3014 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
3015 return err;
3016 }
3017
3018 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
3019 return err;
3020 }
3021
3022 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
3023 return err;
3024 }
3025
3026 snd_hdsp_proc_init(hdsp);
3027
3028 hdsp->last_spdif_sample_rate = -1;
3029 hdsp->last_adat_sample_rate = -1;
3030 hdsp->playback_pid = -1;
3031 hdsp->capture_pid = -1;
3032 hdsp->capture_substream = NULL;
3033 hdsp->playback_substream = NULL;
3034
3035 snd_hdsp_set_defaults(hdsp);
3036
3037 return 0;
3038}
3039
3040static int snd_hdsp_free(hdsp_t *hdsp)
3041{
3042 /* stop the audio, and cancel all interrupts */
3043 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
3044 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
3045
3046 if (hdsp->irq >= 0)
3047 free_irq(hdsp->irq, (void *)hdsp);
3048
3049 snd_hdsp_proc_done(hdsp);
3050 snd_hdsp_free_buffers(hdsp);
3051
3052 if (hdsp->iobase)
3053 iounmap((void *) hdsp->iobase);
3054
3055 if (hdsp->res_port) {
3056 release_resource(hdsp->res_port);
3057 kfree_nocheck(hdsp->res_port);
3058 }
3059
3060 return 0;
3061}
3062
3063static void snd_hdsp_card_free(snd_card_t *card)
3064{
3065 hdsp_t *hdsp = (hdsp_t *) card->private_data;
3066
3067 if (hdsp)
3068 snd_hdsp_free(hdsp);
3069}
3070
3071static int __devinit snd_hdsp_probe(struct pci_dev *pci,
3072 const struct pci_device_id *pci_id)
3073{
3074 static int dev;
3075 hdsp_t *hdsp;
3076 snd_card_t *card;
3077 int err;
3078
3079 if (dev >= SNDRV_CARDS)
3080 return -ENODEV;
3081 if (!enable[dev]) {
3082 dev++;
3083 return -ENOENT;
3084 }
3085
3086 if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t))))
3087 return -ENOMEM;
3088
3089 hdsp = (hdsp_t *) card->private_data;
3090 card->private_free = snd_hdsp_card_free;
3091 hdsp->dev = dev;
3092 hdsp->pci = pci;
3093
3094 if ((err = snd_hdsp_create(card, hdsp, precise_ptr[dev])) < 0) {
3095 snd_card_free(card);
3096 return err;
3097 }
3098
3099 strcpy(card->shortname, "Hammerfall DSP");
3100 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
3101 hdsp->port, hdsp->irq);
3102
3103 if ((err = snd_card_register(card)) < 0) {
3104 snd_card_free(card);
3105 return err;
3106 }
3107 pci_set_drvdata(pci, card);
3108 dev++;
3109 return 0;
3110}
3111
3112static void __devexit snd_hdsp_remove(struct pci_dev *pci)
3113{
3114 snd_card_free(pci_get_drvdata(pci));
3115 pci_set_drvdata(pci, NULL);
3116}
3117
3118static struct pci_driver driver = {
3119 .name = "RME Hammerfall DSP",
3120 .id_table = snd_hdsp_ids,
3121 .probe = snd_hdsp_probe,
3122 .remove = __devexit_p(snd_hdsp_remove),
3123};
3124
3125static int __init alsa_card_hdsp_init(void)
3126{
3127 if (pci_module_init(&driver) < 0) {
3128#ifdef MODULE
3129 printk(KERN_ERR "RME Hammerfall-DSP: no cards found\n");
3130#endif
3131 return -ENODEV;
3132 }
3133
3134 return 0;
3135}
3136
3137static void __exit alsa_card_hdsp_exit(void)
3138{
3139 pci_unregister_driver(&driver);
3140}
3141
3142module_init(alsa_card_hdsp_init)
3143module_exit(alsa_card_hdsp_exit)
3144
3145#ifndef MODULE
3146
3147/* format is: snd-hdsp=enable,index,id */
3148
3149static int __init alsa_card_hdsp_setup(char *str)
3150{
3151 static unsigned __initdata nr_dev = 0;
3152
3153 if (nr_dev >= SNDRV_CARDS)
3154 return 0;
3155 (void)(get_option(&str,&enable[nr_dev]) == 2 &&
3156 get_option(&str,&index[nr_dev]) == 2 &&
3157 get_id(&str,&id[nr_dev]) == 2);
3158 nr_dev++;
3159 return 1;
3160}
3161
3162__setup("snd-hdsp=", alsa_card_hdsp_setup);
3163
3164#endif /* ifndef MODULE */
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