1 | /* |
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2 | * Intel ACPI Component Architecture |
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3 | * AML Disassembler version 20081204 |
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4 | * |
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5 | * Disassembly of facp_awrdacpi.dat, Tue May 11 08:47:42 2010 |
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6 | * |
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7 | * ACPI Data Table [FACP] |
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8 | * |
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9 | * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue |
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10 | */ |
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11 | |
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12 | [000h 000 4] Signature : "FACP" /* Fixed ACPI Description Table */ |
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13 | [004h 004 4] Table Length : 00000074 |
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14 | [008h 008 1] Revision : 01 |
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15 | [009h 009 1] Checksum : CC |
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16 | [00Ah 010 6] Oem ID : "AWARD " |
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17 | [010h 016 8] Oem Table ID : "AWRDACPI" |
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18 | [018h 024 4] Oem Revision : 42302E31 |
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19 | [01Ch 028 4] Asl Compiler ID : "AWRD" |
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20 | [020h 032 4] Asl Compiler Revision : 00000000 |
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21 | |
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22 | [024h 036 4] FACS Address : 7FFF0000 |
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23 | [028h 040 4] DSDT Address : 7FFF30C0 |
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24 | [02Ch 044 1] Model : 01 |
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25 | [02Dh 045 1] PM Profile : 00 |
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26 | [02Eh 046 2] SCI Interrupt : 0009 |
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27 | [030h 048 4] SMI Command Port : 00001048 |
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28 | [034h 052 1] ACPI Enable Value : 81 |
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29 | [035h 053 1] ACPI Disable Value : 80 |
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30 | [036h 054 1] S4BIOS Command : 00 |
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31 | [037h 055 1] P-State Control : 00 |
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32 | [038h 056 4] PM1A Event Block Address : 00001000 |
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33 | [03Ch 060 4] PM1B Event Block Address : 00000000 |
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34 | [040h 064 4] PM1A Control Block Address : 00001004 |
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35 | [044h 068 4] PM1B Control Block Address : 00000000 |
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36 | [048h 072 4] PM2 Control Block Address : 00001016 |
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37 | [04Ch 076 4] PM Timer Block Address : 00001008 |
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38 | [050h 080 4] GPE0 Block Address : 00001020 |
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39 | [054h 084 4] GPE1 Block Address : 00001030 |
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40 | [058h 088 1] PM1 Event Block Length : 04 |
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41 | [059h 089 1] PM1 Control Block Length : 02 |
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42 | [05Ah 090 1] PM2 Control Block Length : 01 |
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43 | [05Bh 091 1] PM Timer Block Length : 04 |
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44 | [05Ch 092 1] GPE0 Block Length : 04 |
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45 | [05Dh 093 1] GPE1 Block Length : 04 |
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46 | [05Eh 094 1] GPE1 Base Offset : 10 |
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47 | [05Fh 095 1] _CST Support : 00 |
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48 | [060h 096 2] C2 Latency : 005A |
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49 | [062h 098 2] C3 Latency : 0384 |
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50 | [064h 100 2] CPU Cache Size : 0000 |
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51 | [066h 102 2] Cache Flush Stride : 0000 |
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52 | [068h 104 1] Duty Cycle Offset : 01 |
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53 | [069h 105 1] Duty Cycle Width : 00 |
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54 | [06Ah 106 1] RTC Day Alarm Index : 7E |
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55 | [06Bh 107 1] RTC Month Alarm Index : 7F |
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56 | [06Ch 108 1] RTC Century Index : 00 |
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57 | [06Dh 109 2] Boot Architecture Flags : 0000 |
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58 | [06Fh 111 1] Reserved : 00 |
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59 | [070h 112 4] Flags (decoded below) : 000004A5 |
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60 | WBINVD is operational : 1 |
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61 | WBINVD does not invalidate : 0 |
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62 | All CPUs support C1 : 1 |
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63 | C2 works on MP system : 0 |
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64 | Power button is generic : 0 |
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65 | Sleep button is generic : 1 |
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66 | RTC wakeup not fixed : 0 |
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67 | RTC wakeup/S4 not possible : 1 |
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68 | 32-bit PM Timer : 0 |
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69 | Docking Supported : 0 |
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70 | |
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71 | Raw Table Data |
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72 | |
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73 | 0000: 46 41 43 50 74 00 00 00 01 CC 41 57 41 52 44 20 FACPt.....AWARD |
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74 | 0010: 41 57 52 44 41 43 50 49 31 2E 30 42 41 57 52 44 AWRDACPI1.0BAWRD |
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75 | 0020: 00 00 00 00 00 00 FF 7F C0 30 FF 7F 01 00 09 00 .........0...... |
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76 | 0030: 48 10 00 00 81 80 00 00 00 10 00 00 00 00 00 00 H............... |
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77 | 0040: 04 10 00 00 00 00 00 00 16 10 00 00 08 10 00 00 ................ |
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78 | 0050: 20 10 00 00 30 10 00 00 04 02 01 04 04 04 10 00 ...0........... |
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79 | 0060: 5A 00 84 03 00 00 00 00 01 00 7E 7F 00 00 00 00 Z.........~..... |
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80 | 0070: A5 04 00 00 .... |
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